LLVM: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Source File (original) (raw)
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40
41using namespace llvm;
43
44#define DEBUG_TYPE "amdgpu-disassembler"
45
46#define SGPR_MAX \
47 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
48 : AMDGPU::EncValues::SGPR_MAX_SI)
49
51
56
59 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
60 MAI(*Ctx.getAsmInfo()),
62 TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
63 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
64
65 if (.hasFeature(AMDGPU::FeatureGCN3Encoding) &&
())
67
69 createConstantSymbolExpr(Symbol, Code);
70
71 UCVersionW64Expr = createConstantSymbolExpr("UC_VERSION_W64_BIT", 0x2000);
72 UCVersionW32Expr = createConstantSymbolExpr("UC_VERSION_W32_BIT", 0x4000);
73 UCVersionMDPExpr = createConstantSymbolExpr("UC_VERSION_MDP_BIT", 0x8000);
74}
75
79
87
89 AMDGPU::OpName Name) {
90 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), Name);
91 if (OpIdx != -1) {
95 }
97}
98
103
104
106
107 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
110}
111
116 if (DAsm->isGFX12Plus()) {
118 } else if (DAsm->isVI()) {
119 Offset = Imm & 0xFFFFF;
120 } else {
122 }
124}
125
129 return addOperand(Inst, DAsm->decodeBoolReg(Inst, Val));
130}
131
136 return addOperand(Inst, DAsm->decodeSplitBarrier(Inst, Val));
137}
138
142 return addOperand(Inst, DAsm->decodeDpp8FI(Val));
143}
144
145#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
146 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
147 uint64_t , \
148 const MCDisassembler *Decoder) { \
149 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
150 return addOperand(Inst, DAsm->DecoderName(Imm)); \
151 }
152
153
154
155#define DECODE_OPERAND_REG_8(RegClass) \
156 static DecodeStatus Decode##RegClass##RegisterClass( \
157 MCInst &Inst, unsigned Imm, uint64_t , \
158 const MCDisassembler *Decoder) { \
159 assert(Imm < (1 << 8) && "8-bit encoding"); \
160 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
161 return addOperand( \
162 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
163 }
164
165#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm) \
166 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t , \
167 const MCDisassembler *Decoder) { \
168 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
169 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
170 return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm)); \
171 }
172
174 unsigned OpWidth, unsigned Imm, unsigned EncImm,
176 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");
178 return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm));
179}
180
181
182
183#define DECODE_OPERAND_SREG_7(RegClass, OpWidth) \
184 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm)
185
186#define DECODE_OPERAND_SREG_8(RegClass, OpWidth) \
187 DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm)
188
189
190
191
192
193template
199
200
201template
205 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, Decoder);
206}
207
208
209
210
211template
214 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
215}
216
217
218
219template
223 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, Decoder);
224}
225
226
227
228
229
230
231template
235 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, Decoder);
236}
237
238
239
240template
244 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
245}
246
247
248
249
250
264
278
280
287
292 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
293
294 bool IsHi = Imm & (1 << 9);
295 unsigned RegIdx = Imm & 0xff;
297 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
298}
299
304
305 bool IsHi = Imm & (1 << 7);
306 unsigned RegIdx = Imm & 0x7f;
308 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
309}
310
311template
316
319 bool IsHi = Imm & (1 << 7);
320 unsigned RegIdx = Imm & 0x7f;
321 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
322 }
323 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth, Imm & 0xFF));
324}
325
326template
331
334 bool IsHi = Imm & (1 << 9);
335 unsigned RegIdx = Imm & 0xff;
336 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
337 }
338 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth, Imm & 0xFF));
339}
340
346
348
349 bool IsHi = Imm & (1 << 9);
350 unsigned RegIdx = Imm & 0xff;
351 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
352}
353
358 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
359}
360
365 return addOperand(Inst, DAsm->decodeMandatoryLiteral64Constant(Imm));
366}
367
369 uint64_t Addr, const void *Decoder) {
371 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
372}
373
377 return addOperand(Inst, DAsm->decodeSrcOp(Inst, Opw, Imm | 256));
378}
379
380template
386
390 assert(Imm < (1 << 9) && "9-bit encoding");
392 return addOperand(Inst, DAsm->decodeSrcOp(Inst, 64, Imm));
393}
394
395#define DECODE_SDWA(DecName) \
396DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
397
401
406 return addOperand(Inst, DAsm->decodeVersionImm(Imm));
407}
408
409#include "AMDGPUGenDisassemblerTables.inc"
410
411namespace {
412
413template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;
414template <> constexpr uint32_t InsnBitWidth<uint64_t> = 64;
415template <> constexpr uint32_t InsnBitWidth<std::bitset<96>> = 96;
416template <> constexpr uint32_t InsnBitWidth<std::bitset<128>> = 128;
417}
418
419
420
421
422
423template
428 assert(MI.getNumOperands() == 0);
430 HasLiteral = false;
431 const auto SavedBytes = Bytes;
432
436
438 decodeInstruction(Table, TmpInst, Inst, Address, this, STI);
439
441
443 MI = TmpInst;
444 Comments << LocalComments;
446 }
447 Bytes = SavedBytes;
449}
450
451template
456 for (const uint8_t *T : {Table1, Table2}) {
458 return Res;
459 }
461}
462
465 const auto Res =
467 Bytes = Bytes.slice(sizeof(T));
468 return Res;
469}
470
475 Bytes = Bytes.slice(8);
477 Bytes = Bytes.slice(4);
479}
480
485 Bytes = Bytes.slice(8);
487 Bytes = Bytes.slice(8);
489}
490
491void AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
493 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
494 for (auto [OpNo, OpDesc] : enumerate(Desc.operands())) {
495 if (OpNo >= MI.getNumOperands())
496 continue;
497
498
499
503 continue;
504
505 MCOperand &Op = MI.getOperand(OpNo);
506 if (.isImm())
507 continue;
508 int64_t Imm = Op.getImm();
512 continue;
513 }
514
517 continue;
518 }
519
522 switch (OpDesc.OperandType) {
528 break;
536 break;
543 break;
544 default:
546 }
547 Op.setImm(Imm);
548 }
549 }
550}
551
556 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
557 Bytes = Bytes_.slice(0, MaxInstBytesNum);
558
559
560
561 Size = std::min((size_t)4, Bytes_.size());
562
563 do {
564
565
566
567
568
569 if (isGFX1250() && Bytes.size() >= 16) {
570 std::bitset<128> DecW = eat16Bytes(Bytes);
572 break;
573 Bytes = Bytes_.slice(0, MaxInstBytesNum);
574 }
575
576 if (isGFX11Plus() && Bytes.size() >= 12) {
577 std::bitset<96> DecW = eat12Bytes(Bytes);
578
580 tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
582 break;
583
585 tryDecodeInst(DecoderTableGFX125096, DecoderTableGFX1250_FAKE1696, MI,
587 break;
588
590 tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
592 break;
593
596 break;
597
598 if (STI.hasFeature(AMDGPU::Feature64BitLiterals)) {
599
600 Bytes = Bytes_.slice(4, MaxInstBytesNum - 4);
601
604 break;
605 }
606
607
608 Bytes = Bytes_.slice(0, MaxInstBytesNum);
609
610 } else if (Bytes.size() >= 16 &&
611 STI.hasFeature(AMDGPU::FeatureGFX950Insts)) {
612 std::bitset<128> DecW = eat16Bytes(Bytes);
614 break;
615
616
617 Bytes = Bytes_.slice(0, MaxInstBytesNum);
618 }
619
620 if (Bytes.size() >= 8) {
622
623 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) &&
625 break;
626
627 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) &&
629 break;
630
631 if (STI.hasFeature(AMDGPU::FeatureGFX950Insts) &&
633 break;
634
635
636
637
638 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts) &&
640 break;
641
642 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts) &&
644 break;
645
646 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) &&
648 break;
649
652 break;
653
655 break;
656
658 break;
659
661 tryDecodeInst(DecoderTableGFX125064, DecoderTableGFX1250_FAKE1664, MI,
663 break;
664
666 tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
668 break;
669
671 tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
673 break;
674
677 break;
678
681 break;
682
683
684 Bytes = Bytes_.slice(0, MaxInstBytesNum);
685 }
686
687
688 if (Bytes.size() >= 4) {
690
693 break;
694
696 break;
697
699 break;
700
701 if (STI.hasFeature(AMDGPU::FeatureGFX950Insts) &&
703 break;
704
705 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) &&
707 break;
708
709 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) &&
711 break;
712
714 break;
715
717 tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
719 break;
720
722 tryDecodeInst(DecoderTableGFX125032, DecoderTableGFX1250_FAKE1632, MI,
724 break;
725
727 tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
729 break;
730 }
731
733 } while (false);
734
736
737 decodeImmOperands(MI, *MCII);
738
742
749 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) !=
750 -1)
754 }
755
757
759
761 AMDGPU::OpName::src2_modifiers);
762 }
763
764 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp ||
765 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) {
766
768 AMDGPU::OpName::src2_modifiers);
769 }
770
774 }
775
776 if (MCII->get(MI.getOpcode()).TSFlags &
778 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
779 AMDGPU::OpName::cpol);
780 if (CPolPos != -1) {
781 unsigned CPol =
784 if (MI.getNumOperands() <= (unsigned)CPolPos) {
786 AMDGPU::OpName::cpol);
787 } else if (CPol) {
788 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
789 }
790 }
791 }
792
793 if ((MCII->get(MI.getOpcode()).TSFlags &
795 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) {
796
797 int TFEOpIdx =
798 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
799 if (TFEOpIdx != -1) {
800 auto *TFEIter = MI.begin();
801 std::advance(TFEIter, TFEOpIdx);
803 }
804 }
805
806
808 int OffsetIdx =
809 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::offset);
810 if (OffsetIdx != -1) {
811 uint32_t Imm = MI.getOperand(OffsetIdx).getImm();
813 if (SignedOffset < 0)
815 }
816 }
817
818 if (MCII->get(MI.getOpcode()).TSFlags &
820 int SWZOpIdx =
821 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
822 if (SWZOpIdx != -1) {
823 auto *SWZIter = MI.begin();
824 std::advance(SWZIter, SWZOpIdx);
826 }
827 }
828
831 int VAddr0Idx =
832 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
833 int RsrcIdx =
834 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
835 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
836 if (VAddr0Idx >= 0 && NSAArgs > 0) {
837 unsigned NSAWords = (NSAArgs + 3) / 4;
838 if (Bytes.size() < 4 * NSAWords)
840 for (unsigned i = 0; i < NSAArgs; ++i) {
841 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
842 auto VAddrRCID =
843 MCII->getOpRegClassID(Desc.operands()[VAddrIdx], HwModeRegClass);
845 }
846 Bytes = Bytes.slice(4 * NSAWords);
847 }
848
850 }
851
852 if (MCII->get(MI.getOpcode()).TSFlags &
855
858
861
864
867
870
871 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
872 AMDGPU::OpName::vdst_in);
873 if (VDstIn_Idx != -1) {
874 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
876 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
877 .getOperand(VDstIn_Idx).isReg() ||
878 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
879 if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
880 MI.erase(&MI.getOperand(VDstIn_Idx));
883 AMDGPU::OpName::vdst_in);
884 }
885 }
886
890
891
892
893
895 MCII->get(MI.getOpcode()).getNumDefs() == 0 &&
896 MCII->get(MI.getOpcode()).hasImplicitDefOfPhysReg(AMDGPU::EXEC)) {
897 auto ExecEncoding = MRI.getEncodingValue(AMDGPU::EXEC_LO);
898 if (Bytes_[0] != ExecEncoding)
900 }
901
902 Size = MaxInstBytesNum - Bytes.size();
904}
905
907 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) {
908
909
912 }
913}
914
917 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11 ||
918 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11 ||
919 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12 ||
920 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12 ||
921 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11 ||
922 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11 ||
923 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12 ||
924 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12 ||
925 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11 ||
926 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11 ||
927 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12 ||
928 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12 ||
929 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11 ||
930 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11 ||
931 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12 ||
932 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12) {
933
934
936 }
937}
938
940 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
941 STI.hasFeature(AMDGPU::FeatureGFX10)) {
943
945 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
946 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
947 if (SDst != -1) {
948
950 AMDGPU::OpName::sdst);
951 } else {
952
954 }
955 }
956}
957
958
959
962 switch (NumRegs) {
963 case 4:
964 return MO.setReg(MRI.getSubReg(MO.getReg(), AMDGPU::sub0_sub1_sub2_sub3));
965 case 6:
967 MRI.getSubReg(MO.getReg(), AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5));
968 case 8:
970 MO.getReg(), AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7)) {
972 }
973 return;
974 case 12: {
975
978 BaseReg, AMDGPU::sub0, &MRI.getRegClass(AMDGPU::VReg_384RegClassID));
979 return MO.setReg(NewReg);
980 }
981 case 16:
982
983 return;
984 default:
985 llvm_unreachable("Unexpected size for mfma/wmma f8f6f4 operand");
986 }
987}
988
989
990
991
992
993
995 int BlgpIdx =
996 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::blgp);
997 if (BlgpIdx == -1)
998 return;
999
1000 int CbszIdx =
1001 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::cbsz);
1002
1003 unsigned CBSZ = MI.getOperand(CbszIdx).getImm();
1004 unsigned BLGP = MI.getOperand(BlgpIdx).getImm();
1005
1008 if (!AdjustedRegClassOpcode ||
1009 AdjustedRegClassOpcode->Opcode == MI.getOpcode())
1010 return;
1011
1012 MI.setOpcode(AdjustedRegClassOpcode->Opcode);
1013 int Src0Idx =
1014 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
1015 int Src1Idx =
1016 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);
1021}
1022
1024 int FmtAIdx =
1025 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::matrix_a_fmt);
1026 if (FmtAIdx == -1)
1027 return;
1028
1029 int FmtBIdx =
1030 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::matrix_b_fmt);
1031
1032 unsigned FmtA = MI.getOperand(FmtAIdx).getImm();
1033 unsigned FmtB = MI.getOperand(FmtBIdx).getImm();
1034
1037 if (!AdjustedRegClassOpcode ||
1038 AdjustedRegClassOpcode->Opcode == MI.getOpcode())
1039 return;
1040
1041 MI.setOpcode(AdjustedRegClassOpcode->Opcode);
1042 int Src0Idx =
1043 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
1044 int Src1Idx =
1045 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);
1050}
1051
1058
1059
1060
1061
1063 bool IsVOP3P = false) {
1065 unsigned Opc = MI.getOpcode();
1066 const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
1067 AMDGPU::OpName::src1_modifiers,
1068 AMDGPU::OpName::src2_modifiers};
1069 for (int J = 0; J < 3; ++J) {
1070 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
1071 if (OpIdx == -1)
1072 continue;
1073
1074 unsigned Val = MI.getOperand(OpIdx).getImm();
1075
1077 if (IsVOP3P) {
1081 } else if (J == 0) {
1083 }
1084 }
1085
1086 return Modifiers;
1087}
1088
1089
1090
1092 const unsigned Opc = MI.getOpcode();
1094 MRI.getRegClass(AMDGPU::VGPR_16RegClassID);
1095 constexpr std::array<std::tuple<AMDGPU::OpName, AMDGPU::OpName, unsigned>, 4>
1096 OpAndOpMods = {{{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers,
1098 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers,
1100 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers,
1102 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers,
1104 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) {
1105 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1106 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName);
1107 if (OpIdx == -1 || OpModsIdx == -1)
1108 continue;
1110 if (.isReg())
1111 continue;
1112 if (!ConversionRC.contains(Op.getReg()))
1113 continue;
1114 unsigned OpEnc = MRI.getEncodingValue(Op.getReg());
1115 const MCOperand &OpMods = MI.getOperand(OpModsIdx);
1116 unsigned ModVal = OpMods.getImm();
1117 if (ModVal & OpSelMask) {
1119 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1));
1120 }
1121 }
1122}
1123
1124
1125
1127 constexpr int DST_IDX = 0;
1128 auto Opcode = MI.getOpcode();
1129 const auto &Desc = MCII->get(Opcode);
1130 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old);
1131
1132 if (OldIdx != -1 && Desc.getOperandConstraint(
1136 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2),
1138 (void)DST_IDX;
1139 return true;
1140 }
1141
1142 return false;
1143}
1144
1145
1147 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands());
1150 AMDGPU::OpName::src2_modifiers);
1151}
1152
1154 unsigned Opc = MI.getOpcode();
1155
1156 int VDstInIdx =
1157 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
1158 if (VDstInIdx != -1)
1160
1161 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1162 if (MI.getNumOperands() < DescNumOps &&
1167 AMDGPU::OpName::op_sel);
1168 } else {
1169
1170 if (MI.getNumOperands() < DescNumOps &&
1173 AMDGPU::OpName::src0_modifiers);
1174
1175 if (MI.getNumOperands() < DescNumOps &&
1178 AMDGPU::OpName::src1_modifiers);
1179 }
1180}
1181
1184
1185 int VDstInIdx =
1186 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
1187 if (VDstInIdx != -1)
1189
1190 unsigned Opc = MI.getOpcode();
1191 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1192 if (MI.getNumOperands() < DescNumOps &&
1196 AMDGPU::OpName::op_sel);
1197 }
1198}
1199
1200
1201
1206 if (!Sub0)
1207 return Reg;
1208
1210 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(Sub0))
1211 BaseReg = AMDGPU::VGPR0;
1212 else if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Sub0))
1213 BaseReg = AMDGPU::AGPR0;
1214
1215 assert(BaseReg && "Only vector registers expected");
1216
1217 return (Sub0 - BaseReg + NumRegs <= 256) ? Reg : MCRegister();
1218}
1219
1220
1221
1222
1224 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags;
1225
1226 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
1227 AMDGPU::OpName::vdst);
1228
1229 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
1230 AMDGPU::OpName::vdata);
1231 int VAddr0Idx =
1232 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
1234 ? AMDGPU::OpName::srsrc
1235 : AMDGPU::OpName::rsrc;
1236 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);
1237 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
1238 AMDGPU::OpName::dmask);
1239
1240 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
1241 AMDGPU::OpName::tfe);
1242 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
1243 AMDGPU::OpName::d16);
1244
1248
1249 assert(VDataIdx != -1);
1250 if (BaseOpcode->BVH) {
1251
1253 return;
1254 }
1255
1256 bool IsAtomic = (VDstIdx != -1);
1259 bool IsNSA = false;
1260 bool IsPartialNSA = false;
1261 unsigned AddrSize = Info->VAddrDwords;
1262
1264 unsigned DimIdx =
1265 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
1266 int A16Idx =
1267 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);
1270 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm());
1271
1272 AddrSize =
1274
1275
1276
1277 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
1278 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA ||
1279 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12;
1280 if (!IsNSA) {
1281 if (!IsVSample && AddrSize > 12)
1282 AddrSize = 16;
1283 } else {
1284 if (AddrSize > Info->VAddrDwords) {
1285 if (.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) {
1286
1287
1288 return;
1289 }
1290 IsPartialNSA = true;
1291 }
1292 }
1293 }
1294
1295 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
1296 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1);
1297
1298 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
1300 DstSize = (DstSize + 1) / 2;
1301 }
1302
1303 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
1304 DstSize += 1;
1305
1306 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
1307 return;
1308
1309 int NewOpcode =
1311 if (NewOpcode == -1)
1312 return;
1313
1314
1316 if (DstSize != Info->VDataDwords) {
1317 auto DataRCID = MCII->getOpRegClassID(
1318 MCII->get(NewOpcode).operands()[VDataIdx], HwModeRegClass);
1319
1320
1321 MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg();
1322 MCRegister VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
1323 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
1324
1325 const MCRegisterClass &NewRC = MRI.getRegClass(DataRCID);
1326 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, &NewRC);
1328 if (!NewVdata) {
1329
1330
1331 return;
1332 }
1333 }
1334
1335
1336
1337 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
1339 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
1340 AddrSize != Info->VAddrDwords) {
1341 MCRegister VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
1342 MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
1343 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
1344
1345 auto AddrRCID = MCII->getOpRegClassID(
1346 MCII->get(NewOpcode).operands()[VAddrSAIdx], HwModeRegClass);
1347
1348 const MCRegisterClass &NewRC = MRI.getRegClass(AddrRCID);
1349 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, &NewRC);
1351 if (!NewVAddrSA)
1352 return;
1353 }
1354
1355 MI.setOpcode(NewOpcode);
1356
1357 if (NewVdata != AMDGPU::NoRegister) {
1359
1360 if (IsAtomic) {
1361
1363 }
1364 }
1365
1366 if (NewVAddrSA) {
1368 } else if (IsNSA) {
1369 assert(AddrSize <= Info->VAddrDwords);
1370 MI.erase(MI.begin() + VAddr0Idx + AddrSize,
1371 MI.begin() + VAddr0Idx + Info->VAddrDwords);
1372 }
1373}
1374
1375
1376
1377
1379 unsigned Opc = MI.getOpcode();
1380 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1382
1383 if (MI.getNumOperands() < DescNumOps &&
1386
1387 if (MI.getNumOperands() < DescNumOps &&
1390 AMDGPU::OpName::op_sel);
1391 if (MI.getNumOperands() < DescNumOps &&
1394 AMDGPU::OpName::op_sel_hi);
1395 if (MI.getNumOperands() < DescNumOps &&
1398 AMDGPU::OpName::neg_lo);
1399 if (MI.getNumOperands() < DescNumOps &&
1402 AMDGPU::OpName::neg_hi);
1403}
1404
1405
1407 unsigned Opc = MI.getOpcode();
1408 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1409
1410 if (MI.getNumOperands() < DescNumOps &&
1413
1414 if (MI.getNumOperands() < DescNumOps &&
1417 AMDGPU::OpName::src0_modifiers);
1418
1419 if (MI.getNumOperands() < DescNumOps &&
1422 AMDGPU::OpName::src1_modifiers);
1423}
1424
1426 unsigned Opc = MI.getOpcode();
1427 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1428
1430
1431 if (MI.getNumOperands() < DescNumOps &&
1435 AMDGPU::OpName::op_sel);
1436 }
1437}
1438
1440 assert(HasLiteral && "Should have decoded a literal");
1442}
1443
1448
1449inline
1451 const Twine& ErrMsg) const {
1453
1454
1455
1457}
1458
1462
1463inline
1465 unsigned Val) const {
1466 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1467 if (Val >= RegCl.getNumRegs())
1469 ": unknown register " + Twine(Val));
1471}
1472
1473inline
1475 unsigned Val) const {
1476
1477
1478 int shift = 0;
1479 switch (SRegClassID) {
1480 case AMDGPU::SGPR_32RegClassID:
1481 case AMDGPU::TTMP_32RegClassID:
1482 break;
1483 case AMDGPU::SGPR_64RegClassID:
1484 case AMDGPU::TTMP_64RegClassID:
1485 shift = 1;
1486 break;
1487 case AMDGPU::SGPR_96RegClassID:
1488 case AMDGPU::TTMP_96RegClassID:
1489 case AMDGPU::SGPR_128RegClassID:
1490 case AMDGPU::TTMP_128RegClassID:
1491
1492
1493 case AMDGPU::SGPR_256RegClassID:
1494 case AMDGPU::TTMP_256RegClassID:
1495
1496
1497 case AMDGPU::SGPR_288RegClassID:
1498 case AMDGPU::TTMP_288RegClassID:
1499 case AMDGPU::SGPR_320RegClassID:
1500 case AMDGPU::TTMP_320RegClassID:
1501 case AMDGPU::SGPR_352RegClassID:
1502 case AMDGPU::TTMP_352RegClassID:
1503 case AMDGPU::SGPR_384RegClassID:
1504 case AMDGPU::TTMP_384RegClassID:
1505 case AMDGPU::SGPR_512RegClassID:
1506 case AMDGPU::TTMP_512RegClassID:
1507 shift = 2;
1508 break;
1509
1510
1511 default:
1513 }
1514
1515 if (Val % (1 << shift)) {
1517 << ": scalar reg isn't aligned " << Val;
1518 }
1519
1521}
1522
1524 bool IsHi) const {
1525 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0);
1526 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16);
1527}
1528
1529
1532 if (HasLiteral) {
1535 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1536 if (Literal != Val)
1537 return errOperand(Val, "More than one unique literal is illegal");
1538 }
1539 HasLiteral = true;
1540 Literal = Val;
1542}
1543
1546 if (HasLiteral) {
1547 if (Literal != Val)
1548 return errOperand(Val, "More than one unique literal is illegal");
1549 }
1550 HasLiteral = true;
1551 Literal = Val;
1552
1553 bool UseLit64 = Hi_32(Literal) == 0;
1557}
1558
1562
1563
1564
1565 if (!HasLiteral) {
1566 if (Bytes.size() < 4) {
1567 return errOperand(0, "cannot read literal, inst bytes left " +
1568 Twine(Bytes.size()));
1569 }
1570 HasLiteral = true;
1572 }
1573
1574
1575 bool HasInv2Pi = true;
1576
1577
1578
1579 int64_t Val = Literal;
1580 bool UseLit = false;
1582 default:
1588 break;
1591 break;
1596 break;
1599 break;
1601 break;
1606 break;
1609 break;
1620 break;
1624 Val <<= 32;
1625 break;
1629 break;
1631
1632
1633
1634
1635 break;
1636 }
1637
1641}
1642
1644 assert(STI.hasFeature(AMDGPU::Feature64BitLiterals));
1645
1646 if (!HasLiteral) {
1647 if (Bytes.size() < 8) {
1648 return errOperand(0, "cannot read literal64, inst bytes left " +
1649 Twine(Bytes.size()));
1650 }
1651 HasLiteral = true;
1653 }
1654
1655 bool UseLit64 = Hi_32(Literal) == 0;
1659}
1660
1663
1664 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1666 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1667 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1668
1669}
1670
1672 switch (Imm) {
1673 case 240:
1675 case 241:
1677 case 242:
1679 case 243:
1681 case 244:
1683 case 245:
1685 case 246:
1687 case 247:
1689 case 248:
1690 return 0x3e22f983;
1691 default:
1693 }
1694}
1695
1697 switch (Imm) {
1698 case 240:
1700 case 241:
1702 case 242:
1704 case 243:
1706 case 244:
1708 case 245:
1710 case 246:
1712 case 247:
1714 case 248:
1715 return 0x3fc45f306dc9c882;
1716 default:
1718 }
1719}
1720
1722 switch (Imm) {
1723 case 240:
1724 return 0x3800;
1725 case 241:
1726 return 0xB800;
1727 case 242:
1728 return 0x3C00;
1729 case 243:
1730 return 0xBC00;
1731 case 244:
1732 return 0x4000;
1733 case 245:
1734 return 0xC000;
1735 case 246:
1736 return 0x4400;
1737 case 247:
1738 return 0xC400;
1739 case 248:
1740 return 0x3118;
1741 default:
1743 }
1744}
1745
1747 switch (Imm) {
1748 case 240:
1749 return 0x3F00;
1750 case 241:
1751 return 0xBF00;
1752 case 242:
1753 return 0x3F80;
1754 case 243:
1755 return 0xBF80;
1756 case 244:
1757 return 0x4000;
1758 case 245:
1759 return 0xC000;
1760 case 246:
1761 return 0x4080;
1762 case 247:
1763 return 0xC080;
1764 case 248:
1765 return 0x3E22;
1766 default:
1768 }
1769}
1770
1772 using namespace AMDGPU;
1773
1774 switch (Width) {
1775 case 16:
1776 case 32:
1777 return VGPR_32RegClassID;
1778 case 64:
1779 return VReg_64RegClassID;
1780 case 96:
1781 return VReg_96RegClassID;
1782 case 128:
1783 return VReg_128RegClassID;
1784 case 160:
1785 return VReg_160RegClassID;
1786 case 192:
1787 return VReg_192RegClassID;
1788 case 256:
1789 return VReg_256RegClassID;
1790 case 288:
1791 return VReg_288RegClassID;
1792 case 320:
1793 return VReg_320RegClassID;
1794 case 352:
1795 return VReg_352RegClassID;
1796 case 384:
1797 return VReg_384RegClassID;
1798 case 512:
1799 return VReg_512RegClassID;
1800 case 1024:
1801 return VReg_1024RegClassID;
1802 }
1804}
1805
1807 using namespace AMDGPU;
1808
1809 switch (Width) {
1810 case 16:
1811 case 32:
1812 return AGPR_32RegClassID;
1813 case 64:
1814 return AReg_64RegClassID;
1815 case 96:
1816 return AReg_96RegClassID;
1817 case 128:
1818 return AReg_128RegClassID;
1819 case 160:
1820 return AReg_160RegClassID;
1821 case 256:
1822 return AReg_256RegClassID;
1823 case 288:
1824 return AReg_288RegClassID;
1825 case 320:
1826 return AReg_320RegClassID;
1827 case 352:
1828 return AReg_352RegClassID;
1829 case 384:
1830 return AReg_384RegClassID;
1831 case 512:
1832 return AReg_512RegClassID;
1833 case 1024:
1834 return AReg_1024RegClassID;
1835 }
1837}
1838
1840 using namespace AMDGPU;
1841
1842 switch (Width) {
1843 case 16:
1844 case 32:
1845 return SGPR_32RegClassID;
1846 case 64:
1847 return SGPR_64RegClassID;
1848 case 96:
1849 return SGPR_96RegClassID;
1850 case 128:
1851 return SGPR_128RegClassID;
1852 case 160:
1853 return SGPR_160RegClassID;
1854 case 256:
1855 return SGPR_256RegClassID;
1856 case 288:
1857 return SGPR_288RegClassID;
1858 case 320:
1859 return SGPR_320RegClassID;
1860 case 352:
1861 return SGPR_352RegClassID;
1862 case 384:
1863 return SGPR_384RegClassID;
1864 case 512:
1865 return SGPR_512RegClassID;
1866 }
1868}
1869
1871 using namespace AMDGPU;
1872
1873 switch (Width) {
1874 case 16:
1875 case 32:
1876 return TTMP_32RegClassID;
1877 case 64:
1878 return TTMP_64RegClassID;
1879 case 128:
1880 return TTMP_128RegClassID;
1881 case 256:
1882 return TTMP_256RegClassID;
1883 case 288:
1884 return TTMP_288RegClassID;
1885 case 320:
1886 return TTMP_320RegClassID;
1887 case 352:
1888 return TTMP_352RegClassID;
1889 case 384:
1890 return TTMP_384RegClassID;
1891 case 512:
1892 return TTMP_512RegClassID;
1893 }
1895}
1896
1899
1900 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1901 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1902
1903 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1904}
1905
1907 unsigned Val) const {
1909
1910 assert(Val < 1024);
1911
1912 bool IsAGPR = Val & 512;
1913 Val &= 511;
1914
1915 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1918 }
1920}
1921
1923 unsigned Width,
1924 unsigned Val) const {
1925
1926
1927 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0");
1929
1931
1932 static_assert(SGPR_MIN == 0);
1934 }
1935
1937 if (TTmpIdx >= 0) {
1939 }
1940
1941 if ((INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) ||
1942 (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) ||
1943 Val == LITERAL_CONST)
1945
1946 if (Val == LITERAL64_CONST && STI.hasFeature(AMDGPU::Feature64BitLiterals)) {
1948 }
1949
1950 switch (Width) {
1951 case 32:
1952 case 16:
1954 case 64:
1956 case 96:
1957 case 128:
1958 case 256:
1959 case 512:
1961 default:
1963 }
1964}
1965
1966
1967
1969 unsigned Val) const {
1970 int VDstXInd =
1971 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);
1972 assert(VDstXInd != -1);
1974 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
1975 Val |= ~XDstReg & 1;
1977}
1978
1980 using namespace AMDGPU;
1981
1982 switch (Val) {
1983
1994 case 124:
1996 case 125:
2000 case 230: return createRegOperand(SRC_FLAT_SCRATCH_BASE_LO);
2001 case 231: return createRegOperand(SRC_FLAT_SCRATCH_BASE_HI);
2006 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
2011 default: break;
2012
2013 }
2014 return errOperand(Val, "unknown operand encoding " + Twine(Val));
2015}
2016
2018 using namespace AMDGPU;
2019
2020 switch (Val) {
2026 case 124:
2029 break;
2030 case 125:
2033 break;
2035 case 230: return createRegOperand(SRC_FLAT_SCRATCH_BASE_LO);
2040 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
2044 default: break;
2045 }
2046 return errOperand(Val, "unknown operand encoding " + Twine(Val));
2047}
2048
2050 using namespace AMDGPU;
2051
2052 switch (Val) {
2053 case 124:
2056 break;
2057 case 125:
2060 break;
2061 default:
2062 break;
2063 }
2064 return errOperand(Val, "unknown operand encoding " + Twine(Val));
2065}
2066
2068 const unsigned Val) const {
2071
2072 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
2073 STI.hasFeature(AMDGPU::FeatureGFX10)) {
2074
2075
2076 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
2077 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
2079 Val - SDWA9EncValues::SRC_VGPR_MIN);
2080 }
2081 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
2082 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
2083 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
2085 Val - SDWA9EncValues::SRC_SGPR_MIN);
2086 }
2087 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
2088 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
2090 Val - SDWA9EncValues::SRC_TTMP_MIN);
2091 }
2092
2093 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
2094
2095 if ((INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) ||
2096 (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX))
2098
2100 }
2101 if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands))
2104}
2105
2109
2113
2116
2117 assert((STI.hasFeature(AMDGPU::FeatureGFX9) ||
2118 STI.hasFeature(AMDGPU::FeatureGFX10)) &&
2119 "SDWAVopcDst should be present only on GFX9+");
2120
2121 bool IsWave32 = STI.hasFeature(AMDGPU::FeatureWavefrontSize32);
2122
2123 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
2124 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
2125
2127 if (TTmpIdx >= 0) {
2128 auto TTmpClsId = getTtmpClassId(IsWave32 ? 32 : 64);
2130 }
2133 }
2135 }
2136 return createRegOperand(IsWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);
2137}
2138
2140 unsigned Val) const {
2141 return STI.hasFeature(AMDGPU::FeatureWavefrontSize32)
2144}
2145
2147 unsigned Val) const {
2149}
2150
2156
2163
2164 auto [Version, W64, W32, MDP] = Encoding::decode(Imm);
2165
2166
2167 if (Encoding::encode(Version, W64, W32, MDP) != Imm)
2169
2173 return V.Code == Version;
2174 });
2177 if (I == Versions.end())
2179 else
2181
2182 if (W64)
2184 if (W32)
2186 if (MDP)
2188
2190}
2191
2193 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2194}
2195
2197
2199 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2200}
2201
2203
2205
2209
2211 return STI.hasFeature(AMDGPU::FeatureGFX11);
2212}
2213
2217
2219 return STI.hasFeature(AMDGPU::FeatureGFX12);
2220}
2221
2225
2227
2229 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2230}
2231
2235
2236
2237
2238
2239
2240
2241
2242
2243
2247
2250
2251 if (PopCount == 1) {
2252 S << "bit (" << (TrailingZeros + BaseBytes * CHAR_BIT) << ')';
2253 } else {
2254 S << "bits in range ("
2255 << (TrailingZeros + PopCount - 1 + BaseBytes * CHAR_BIT) << ':'
2256 << (TrailingZeros + BaseBytes * CHAR_BIT) << ')';
2257 }
2258
2259 return Result;
2260}
2261
2262#define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK))
2263#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
2264 do { \
2265 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \
2266 } while (0)
2267#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \
2268 do { \
2269 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \
2270 << GET_FIELD(MASK) << '\n'; \
2271 } while (0)
2272
2273#define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG) \
2274 do { \
2275 if (FourByteBuffer & (MASK)) { \
2276 return createStringError(std::errc::invalid_argument, \
2277 "kernel descriptor " DESC \
2278 " reserved %s set" MSG, \
2279 getBitRangeFromMask((MASK), 0).c_str()); \
2280 } \
2281 } while (0)
2282
2283#define CHECK_RESERVED_BITS(MASK) CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "")
2284#define CHECK_RESERVED_BITS_MSG(MASK, MSG) \
2285 CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG)
2286#define CHECK_RESERVED_BITS_DESC(MASK, DESC) \
2287 CHECK_RESERVED_BITS_IMPL(MASK, DESC, "")
2288#define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG) \
2289 CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG)
2290
2291
2294 using namespace amdhsa;
2296
2297
2298
2299
2300
2301
2302 uint32_t GranulatedWorkitemVGPRCount =
2303 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT);
2304
2306 (GranulatedWorkitemVGPRCount + 1) *
2308
2309 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330 uint32_t GranulatedWavefrontSGPRCount =
2331 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT);
2332
2335 "must be zero on gfx10+");
2336
2337 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
2339
2340 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
2342 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
2343 bool ReservedXnackMask = STI.hasFeature(AMDGPU::FeatureXNACK);
2344 assert(!ReservedXnackMask || STI.hasFeature(AMDGPU::FeatureSupportsXNACK));
2345 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << ReservedXnackMask
2346 << '\n';
2347 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
2348
2350
2352 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
2354 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
2356 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
2358 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
2359
2361
2364 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP);
2365
2367
2370 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE);
2371
2374
2375
2377 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
2378 } else {
2380 "COMPUTE_PGM_RSRC1", "must be zero pre-gfx9");
2381 }
2382
2383
2386 COMPUTE_PGM_RSRC1_GFX125_FLAT_SCRATCH_IS_NV);
2387 } else {
2389 "COMPUTE_PGM_RSRC1");
2390 }
2391
2392
2394
2395
2397
2400 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
2401 }
2402 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
2403 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
2404 } else {
2406 "COMPUTE_PGM_RSRC1");
2407 }
2408
2411 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN);
2412
2413 return true;
2414}
2415
2416
2419 using namespace amdhsa;
2423 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
2424 else
2425 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset",
2426 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
2428 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
2430 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
2432 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
2434 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
2436 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
2437
2441
2443 ".amdhsa_exception_fp_ieee_invalid_op",
2444 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
2446 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
2448 ".amdhsa_exception_fp_ieee_div_zero",
2449 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
2451 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
2453 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
2455 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
2457 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
2458
2460
2461 return true;
2462}
2463
2464
2467 using namespace amdhsa;
2470 KdStream << Indent << ".amdhsa_accum_offset "
2471 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
2472 << '\n';
2473
2474 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
2475
2477 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a");
2479 "COMPUTE_PGM_RSRC3", "must be zero on gfx90a");
2481
2483 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) {
2485 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT);
2486 } else {
2488 "SHARED_VGPR_COUNT",
2489 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT);
2490 }
2491 } else {
2493 "COMPUTE_PGM_RSRC3",
2494 "must be zero on gfx12+");
2495 }
2496
2497
2500 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE);
2502 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START);
2504 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END);
2507 COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE);
2508 } else {
2510 "COMPUTE_PGM_RSRC3",
2511 "must be zero on gfx10");
2512 }
2513
2514
2516 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+");
2517
2518
2521 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN);
2522 } else {
2524 "COMPUTE_PGM_RSRC3",
2525 "must be zero on gfx10 or gfx11");
2526 }
2527
2528
2531 COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT);
2533 "ENABLE_DYNAMIC_VGPR", COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR);
2535 COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT);
2537 "ENABLE_DIDT_THROTTLE",
2538 COMPUTE_PGM_RSRC3_GFX125_ENABLE_DIDT_THROTTLE);
2539 } else {
2541 "COMPUTE_PGM_RSRC3",
2542 "must be zero on gfx10+");
2543 }
2544
2545
2547 "COMPUTE_PGM_RSRC3", "must be zero on gfx10+");
2548
2549
2552 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP);
2553 } else {
2555 "COMPUTE_PGM_RSRC3",
2556 "must be zero on gfx10");
2557 }
2558 } else if (FourByteBuffer) {
2560 std::errc::invalid_argument,
2561 "kernel descriptor COMPUTE_PGM_RSRC3 must be all zero before gfx9");
2562 }
2563 return true;
2564}
2565#undef PRINT_PSEUDO_DIRECTIVE_COMMENT
2566#undef PRINT_DIRECTIVE
2567#undef GET_FIELD
2568#undef CHECK_RESERVED_BITS_IMPL
2569#undef CHECK_RESERVED_BITS
2570#undef CHECK_RESERVED_BITS_MSG
2571#undef CHECK_RESERVED_BITS_DESC
2572#undef CHECK_RESERVED_BITS_DESC_MSG
2573
2574
2575
2577 const char *Msg = "") {
2579 std::errc::invalid_argument, "kernel descriptor reserved %s set%s%s",
2581}
2582
2583
2584
2586 unsigned WidthInBytes) {
2587
2588
2590 std::errc::invalid_argument,
2591 "kernel descriptor reserved bits in range (%u:%u) set",
2592 (BaseInBytes + WidthInBytes) * CHAR_BIT - 1, BaseInBytes * CHAR_BIT);
2593}
2594
2598#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
2599 do { \
2600 KdStream << Indent << DIRECTIVE " " \
2601 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
2602 } while (0)
2603
2605 uint32_t FourByteBuffer = 0;
2606
2609
2610 assert(Bytes.size() == 64);
2611 DataExtractor DE(Bytes, true, 8);
2612
2613 switch (Cursor.tell()) {
2615 FourByteBuffer = DE.getU32(Cursor);
2616 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
2617 << '\n';
2618 return true;
2619
2621 FourByteBuffer = DE.getU32(Cursor);
2622 KdStream << Indent << ".amdhsa_private_segment_fixed_size "
2623 << FourByteBuffer << '\n';
2624 return true;
2625
2627 FourByteBuffer = DE.getU32(Cursor);
2628 KdStream << Indent << ".amdhsa_kernarg_size "
2629 << FourByteBuffer << '\n';
2630 return true;
2631
2633
2634 ReservedBytes = DE.getBytes(Cursor, 4);
2635 for (int I = 0; I < 4; ++I) {
2636 if (ReservedBytes[I] != 0)
2638 }
2639 return true;
2640
2642
2643
2644
2645 DE.skip(Cursor, 8);
2646 return true;
2647
2649
2650 ReservedBytes = DE.getBytes(Cursor, 20);
2651 for (int I = 0; I < 20; ++I) {
2652 if (ReservedBytes[I] != 0)
2654 }
2655 return true;
2656
2658 FourByteBuffer = DE.getU32(Cursor);
2660
2662 FourByteBuffer = DE.getU32(Cursor);
2664
2666 FourByteBuffer = DE.getU32(Cursor);
2668
2670 using namespace amdhsa;
2671 TwoByteBuffer = DE.getU16(Cursor);
2672
2674 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
2675 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
2677 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
2679 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
2680 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
2681 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
2683 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
2686 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
2687 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
2688 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
2689
2690 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
2693
2694
2696 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
2698 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
2700 }
2703 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2704 }
2705
2708 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
2709
2710 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) {
2713 }
2714
2715 return true;
2716
2718 using namespace amdhsa;
2719 TwoByteBuffer = DE.getU16(Cursor);
2720 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) {
2721 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length",
2722 KERNARG_PRELOAD_SPEC_LENGTH);
2723 }
2724
2725 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) {
2726 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset",
2727 KERNARG_PRELOAD_SPEC_OFFSET);
2728 }
2729 return true;
2730
2732
2733 ReservedBytes = DE.getBytes(Cursor, 4);
2734 for (int I = 0; I < 4; ++I) {
2735 if (ReservedBytes[I] != 0)
2737 }
2738 return true;
2739
2740 default:
2741 llvm_unreachable("Unhandled index. Case statements cover everything.");
2742 return true;
2743 }
2744#undef PRINT_DIRECTIVE
2745}
2746
2749
2750
2751 if (Bytes.size() != 64 || KdAddress % 64 != 0)
2753 "kernel descriptor must be 64-byte aligned");
2754
2755
2756
2757
2758
2759
2761 uint16_t KernelCodeProperties =
2764 EnableWavefrontSize32 =
2766 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2767 }
2768
2769 std::string Kd;
2771 KdStream << ".amdhsa_kernel " << KdName << '\n';
2772
2774 while (C && C.tell() < Bytes.size()) {
2776
2778
2779 if (!Res)
2780 return Res;
2781 }
2782 KdStream << ".end_amdhsa_kernel\n";
2783 outs() << KdStream.str();
2784 return true;
2785}
2786
2791
2792
2793
2794
2795
2796
2797
2801 "code object v2 is not supported");
2802 }
2803
2804
2807 Size = 64;
2809 }
2810
2811 return false;
2812}
2813
2814const MCExpr *AMDGPUDisassembler::createConstantSymbolExpr(StringRef Id,
2815 int64_t Val) {
2817 MCSymbol *Sym = Ctx.getOrCreateSymbol(Id);
2818
2819
2822 } else {
2823 int64_t Res = ~Val;
2824 bool Valid = Sym->getVariableValue()->evaluateAsAbsolute(Res);
2825 if (!Valid || Res != Val)
2826 Ctx.reportWarning(SMLoc(), "unsupported redefinition of " + Id);
2827 }
2829}
2830
2832 const uint64_t TSFlags = MCII->get(MI.getOpcode()).TSFlags;
2833
2834
2836 return true;
2837
2838
2840 return true;
2841
2842 return false;
2843}
2844
2845
2846
2847
2848
2849
2854
2855 if (!IsBranch) {
2856 return false;
2857 }
2858
2860 if (!Symbols)
2861 return false;
2862
2866 });
2867 if (Result != Symbols->end()) {
2868 auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
2871 return true;
2872 }
2873
2874 ReferencedAddresses.push_back(static_cast<uint64_t>(Value));
2875 return false;
2876}
2877
2883
2884
2885
2886
2887
2891 void *DisInfo,
2893 std::unique_ptr &&RelInfo) {
2894 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
2895}
2896
2902
unsigned const MachineRegisterInfo * MRI
MCDisassembler::DecodeStatus DecodeStatus
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
#define CHECK_RESERVED_BITS_DESC(MASK, DESC)
Definition AMDGPUDisassembler.cpp:2286
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
Definition AMDGPUDisassembler.cpp:1062
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, AMDGPU::OpName Name)
Definition AMDGPUDisassembler.cpp:88
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
Definition AMDGPUDisassembler.cpp:2904
static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:312
static DecodeStatus decodeOperand_KImmFP64(MCInst &Inst, uint64_t Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:361
static SmallString< 32 > getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes)
Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in e...
Definition AMDGPUDisassembler.cpp:2244
#define DECODE_OPERAND_SREG_8(RegClass, OpWidth)
Definition AMDGPUDisassembler.cpp:186
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:112
static std::bitset< 128 > eat16Bytes(ArrayRef< uint8_t > &Bytes)
Definition AMDGPUDisassembler.cpp:481
static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:402
#define DECODE_OPERAND_SREG_7(RegClass, OpWidth)
Definition AMDGPUDisassembler.cpp:183
static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:212
static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:341
#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
Definition AMDGPUDisassembler.cpp:2267
static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, unsigned OpWidth, unsigned Imm, unsigned EncImm, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:173
static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:139
static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:387
static MCRegister CheckVGPROverflow(MCRegister Reg, const MCRegisterClass &RC, const MCRegisterInfo &MRI)
Definition AMDGPUDisassembler.cpp:1202
static int64_t getInlineImmValBF16(unsigned Imm)
Definition AMDGPUDisassembler.cpp:1746
#define DECODE_SDWA(DecName)
Definition AMDGPUDisassembler.cpp:395
static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:99
#define DECODE_OPERAND_REG_8(RegClass)
Definition AMDGPUDisassembler.cpp:155
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
Definition AMDGPUDisassembler.cpp:2263
static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:232
static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:288
static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:202
static int64_t getInlineImmVal32(unsigned Imm)
Definition AMDGPUDisassembler.cpp:1671
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition AMDGPUDisassembler.cpp:81
#define CHECK_RESERVED_BITS(MASK)
Definition AMDGPUDisassembler.cpp:2283
static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:220
#define SGPR_MAX
Definition AMDGPUDisassembler.cpp:46
static int64_t getInlineImmVal64(unsigned Imm)
Definition AMDGPUDisassembler.cpp:1696
static T eatBytes(ArrayRef< uint8_t > &Bytes)
Definition AMDGPUDisassembler.cpp:463
static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:354
static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, unsigned Opw, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:374
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition AMDGPUDisassembler.cpp:2897
static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:241
static DecodeStatus DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:301
#define CHECK_RESERVED_BITS_MSG(MASK, MSG)
Definition AMDGPUDisassembler.cpp:2284
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
Definition AMDGPUDisassembler.cpp:368
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition AMDGPUDisassembler.cpp:2888
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:126
static int64_t getInlineImmValF16(unsigned Imm)
Definition AMDGPUDisassembler.cpp:1721
#define GET_FIELD(MASK)
Definition AMDGPUDisassembler.cpp:2262
static std::bitset< 96 > eat12Bytes(ArrayRef< uint8_t > &Bytes)
Definition AMDGPUDisassembler.cpp:471
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:327
static Error createReservedKDBytesError(unsigned BaseInBytes, unsigned WidthInBytes)
Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.
Definition AMDGPUDisassembler.cpp:2585
static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:132
static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
Definition AMDGPUDisassembler.cpp:194
#define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG)
Definition AMDGPUDisassembler.cpp:2288
static Error createReservedKDBitsError(uint32_t Mask, unsigned BaseBytes, const char *Msg="")
Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.
Definition AMDGPUDisassembler.cpp:2576
static void adjustMFMA_F8F6F4OpRegClass(const MCRegisterInfo &MRI, MCOperand &MO, uint8_t NumRegs)
Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister fo...
Definition AMDGPUDisassembler.cpp:960
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
#define LLVM_EXTERNAL_VISIBILITY
MachineInstr unsigned OpIdx
Interface definition for SIRegisterInfo.
MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const
Definition AMDGPUDisassembler.cpp:1922
MCOperand decodeLiteral64Constant() const
Definition AMDGPUDisassembler.cpp:1643
void convertVOPC64DPPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1425
bool isBufferInstruction(const MCInst &MI) const
Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
Definition AMDGPUDisassembler.cpp:2831
bool hasKernargPreload() const
Definition AMDGPUDisassembler.cpp:2232
void convertEXPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:906
MCOperand decodeSpecialReg64(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2017
const char * getRegClassName(unsigned RegClassID) const
Definition AMDGPUDisassembler.cpp:1444
bool isGFX12() const
Definition AMDGPUDisassembler.cpp:2218
Expected< bool > decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition AMDGPUDisassembler.cpp:2292
MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const
Definition AMDGPUDisassembler.cpp:2146
Expected< bool > decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition AMDGPUDisassembler.cpp:2595
void convertVOPCDPPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1406
MCOperand decodeSpecialReg96Plus(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2049
MCOperand decodeSDWASrc32(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2110
void setABIVersion(unsigned Version) override
ELF-specific, set the ABI version from the object header.
Definition AMDGPUDisassembler.cpp:76
Expected< bool > decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition AMDGPUDisassembler.cpp:2417
bool isGFX11() const
Definition AMDGPUDisassembler.cpp:2210
unsigned getAgprClassId(unsigned Width) const
Definition AMDGPUDisassembler.cpp:1806
MCOperand decodeDpp8FI(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2151
MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const
Definition AMDGPUDisassembler.cpp:2067
bool isGFX9Plus() const
Definition AMDGPUDisassembler.cpp:2202
void convertFMAanyK(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1439
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
Definition AMDGPUDisassembler.cpp:424
void convertMacDPPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1146
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
Definition AMDGPUDisassembler.cpp:1968
bool isGFX10Plus() const
Definition AMDGPUDisassembler.cpp:2206
void convertDPP8Inst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1153
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const
Definition AMDGPUDisassembler.cpp:1523
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition AMDGPUDisassembler.cpp:1450
MCOperand decodeVersionImm(unsigned Imm) const
Definition AMDGPUDisassembler.cpp:2157
Expected< bool > decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition AMDGPUDisassembler.cpp:2747
void convertVOP3DPPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1182
void convertTrue16OpSel(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1091
MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const
Definition AMDGPUDisassembler.cpp:1906
bool isVI() const
Definition AMDGPUDisassembler.cpp:2192
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition AMDGPUDisassembler.cpp:1531
MCOperand decodeLiteralConstant(const MCInstrDesc &Desc, const MCOperandInfo &OpDesc) const
Definition AMDGPUDisassembler.cpp:1560
Expected< bool > decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
Definition AMDGPUDisassembler.cpp:2465
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition AMDGPUDisassembler.cpp:57
MCOperand decodeSpecialReg32(unsigned Val) const
Definition AMDGPUDisassembler.cpp:1979
MCOperand createRegOperand(MCRegister Reg) const
Definition AMDGPUDisassembler.cpp:1459
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2114
void convertVINTERPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:915
void convertSDWAInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:939
bool isGFX12Plus() const
Definition AMDGPUDisassembler.cpp:2222
unsigned getSgprClassId(unsigned Width) const
Definition AMDGPUDisassembler.cpp:1839
static MCOperand decodeIntImmed(unsigned Imm)
Definition AMDGPUDisassembler.cpp:1661
void convertWMMAInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1023
bool isGFX9() const
Definition AMDGPUDisassembler.cpp:2196
MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const
Definition AMDGPUDisassembler.cpp:2139
unsigned getVgprClassId(unsigned Width) const
Definition AMDGPUDisassembler.cpp:1771
void convertMAIInst(MCInst &MI) const
f8f6f4 instructions have different pseudos depending on the used formats.
Definition AMDGPUDisassembler.cpp:994
bool hasArchitectedFlatScratch() const
Definition AMDGPUDisassembler.cpp:2228
unsigned getTtmpClassId(unsigned Width) const
Definition AMDGPUDisassembler.cpp:1870
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition AMDGPUDisassembler.cpp:552
bool isGFX90A() const
Definition AMDGPUDisassembler.cpp:2198
MCOperand decodeMandatoryLiteral64Constant(uint64_t Imm) const
Definition AMDGPUDisassembler.cpp:1545
void convertMIMGInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1223
bool isMacDPP(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1126
int getTTmpIdx(unsigned Val) const
Definition AMDGPUDisassembler.cpp:1897
bool isGFX10() const
Definition AMDGPUDisassembler.cpp:2204
void convertVOP3PDPPInst(MCInst &MI) const
Definition AMDGPUDisassembler.cpp:1378
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition AMDGPUDisassembler.cpp:1474
bool isGFX11Plus() const
Definition AMDGPUDisassembler.cpp:2214
MCOperand decodeSDWASrc16(unsigned Val) const
Definition AMDGPUDisassembler.cpp:2106
bool isGFX1250() const
Definition AMDGPUDisassembler.cpp:2226
Expected< bool > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition AMDGPUDisassembler.cpp:2787
static const AMDGPUMCExpr * createLit(LitModifier Lit, int64_t Value, MCContext &Ctx)
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition AMDGPUDisassembler.cpp:2850
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition AMDGPUDisassembler.cpp:2878
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Lightweight error class with error context and mandatory checking.
Tagged union holding either a T or a Error.
static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Superclass for all disassemblers.
MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
This holds information about one operand of a machine instruction, indicating the register class for ...
uint8_t OperandType
Information about the type of the operand.
Instances of this class represent operands of the MCInst class.
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
void setReg(MCRegister Reg)
Set the register number.
MCRegister getReg() const
Returns the register number.
MCRegisterClass - Base class of TargetRegisterClass.
MCRegister getRegister(unsigned i) const
getRegister - Return the specified register in the class.
unsigned getSizeInBits() const
Return the size of the physical register in bits if we are able to determine it.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
bool isVariable() const
isVariable - Check if this is a variable symbol.
LLVM_ABI void setVariableValue(const MCExpr *Value)
const MCExpr * getVariableValue() const
Get the expression of the variable symbol.
Symbolize and annotate disassembled instructions.
Represents a location in source code.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
A raw_ostream that writes to an SmallVector or SmallString.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
ArrayRef< GFXVersion > getGFXVersions()
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
EncodingField< Bit, Bit, D > EncodingBit
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isInlinableLiteralV2I16(uint32_t Literal)
bool isGFX10(const MCSubtargetInfo &STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool getSMEMIsBuffer(unsigned Opc)
bool isVOPC64DPP(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const MFMA_F8F6F4_Info * getWMMA_F8F6F4_WithFormatArgs(unsigned FmtA, unsigned FmtB, unsigned F8F8Opcode)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_BF16
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_INT32
Operands with register, 32-bit, or 64-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_IMM_NOINLINE_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_INT32
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
bool hasGDS(const MCSubtargetInfo &STI)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool isGFX1250(const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
const MFMA_F8F6F4_Info * getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
@ C
The default llvm calling convention, compatible with C.
@ KERNEL_CODE_PROPERTIES_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
value_type read(const void *memory, endianness endian)
Read a value of a particular endianness from memory.
uint16_t read16(const void *P, endianness E)
This is an optimization pass for GlobalISel generic memory operations.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are tuples (A, B,...
LLVM_ABI raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
Error createStringError(std::error_code EC, char const *Fmt, const Ts &... Vals)
Create formatted StringError object.
constexpr int popcount(T Value) noexcept
Count the number of set bits in a value.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
FunctionAddr VTableAddr uintptr_t uintptr_t Version
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Target & getTheGCNTarget()
The target for GCN GPUs.
To bit_cast(const From &from) noexcept
DWARFExpression::Operation Op
unsigned M0(unsigned Val)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
std::vector< SymbolInfoTy > SectionSymbolsTy
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
unsigned NegHi
Definition AMDGPUDisassembler.cpp:1056
unsigned OpSel
Definition AMDGPUDisassembler.cpp:1053
unsigned NegLo
Definition AMDGPUDisassembler.cpp:1055
unsigned OpSelHi
Definition AMDGPUDisassembler.cpp:1054
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.