LLVM: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp File Reference (original) (raw)

This file contains definition for AMDGPU ISA disassembler. More...

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Macros
#define DEBUG_TYPE "amdgpu-disassembler"
#define SGPR_MAX
#define DECODE_OPERAND(StaticDecoderName, DecoderName)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)
#define DECODE_OPERAND_SREG_7(RegClass, OpWidth)
#define DECODE_OPERAND_SREG_8(RegClass, OpWidth)
#define DECODE_SDWA(DecName)
#define GET_FIELD(MASK)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG)
#define CHECK_RESERVED_BITS(MASK)
#define CHECK_RESERVED_BITS_MSG(MASK, MSG)
#define CHECK_RESERVED_BITS_DESC(MASK, DESC)
#define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
Functions
static int64_t getInlineImmValF16 (unsigned Imm)
static int64_t getInlineImmValBF16 (unsigned Imm)
static int64_t getInlineImmVal32 (unsigned Imm)
static int64_t getInlineImmVal64 (unsigned Imm)
static MCDisassembler::DecodeStatus addOperand (MCInst &Inst, const MCOperand &Opnd)
static int insertNamedMCOperand (MCInst &MI, const MCOperand &Op, AMDGPU::OpName Name)
static DecodeStatus decodeSOPPBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSplitBarrier (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeDpp8FI (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSrcOp (MCInst &Inst, unsigned EncSize, unsigned OpWidth, unsigned Imm, unsigned EncImm, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcReg9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImm9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImmA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus DecodeVGPR_16RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus DecodeVGPR_16_Lo128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16_Lo128 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VGPR_16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_KImmFP (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_KImmFP64 (MCInst &Inst, uint64_t Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static DecodeStatus decodeAVLdSt (MCInst &Inst, unsigned Imm, unsigned Opw, const MCDisassembler *Decoder)
template<unsigned Opw>
static DecodeStatus decodeAVLdSt (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VSrc_f64 (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeVersionImm (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<typename T>
static T eatBytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 96 > eat12Bytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 128 > eat16Bytes (ArrayRef< uint8_t > &Bytes)
static void adjustMFMA_F8F6F4OpRegClass (const MCRegisterInfo &MRI, MCOperand &MO, uint8_t NumRegs)
Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister for the used format width.
static VOPModifiers collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
static MCRegister CheckVGPROverflow (MCRegister Reg, const MCRegisterClass &RC, const MCRegisterInfo &MRI)
static SmallString< 32 > getBitRangeFromMask (uint32_t Mask, unsigned BaseBytes)
Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.
static Error createReservedKDBitsError (uint32_t Mask, unsigned BaseBytes, const char *Msg="")
Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.
static Error createReservedKDBytesError (unsigned BaseInBytes, unsigned WidthInBytes)
Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.
static MCSymbolizer * createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static MCDisassembler * createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler ()

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

◆ CHECK_RESERVED_BITS

#define CHECK_RESERVED_BITS ( MASK )

◆ CHECK_RESERVED_BITS_DESC

#define CHECK_RESERVED_BITS_DESC ( MASK,
DESC )

◆ CHECK_RESERVED_BITS_DESC_MSG

#define CHECK_RESERVED_BITS_DESC_MSG ( MASK,
DESC,
MSG )

◆ CHECK_RESERVED_BITS_IMPL

#define CHECK_RESERVED_BITS_IMPL ( MASK,
DESC,
MSG )

Value:

do { \

if (FourByteBuffer & (MASK)) { \

"kernel descriptor " DESC \

" reserved %s set" MSG, \

} \

} while (0)

static SmallString< 32 > getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes)

Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in e...

SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)

Error createStringError(std::error_code EC, char const *Fmt, const Ts &... Vals)

Create formatted StringError object.

Definition at line 2273 of file AMDGPUDisassembler.cpp.

◆ CHECK_RESERVED_BITS_MSG

#define CHECK_RESERVED_BITS_MSG ( MASK,
MSG )

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-disassembler"

◆ DECODE_OPERAND

#define DECODE_OPERAND ( StaticDecoderName,
DecoderName )

Value:

return addOperand(Inst, DAsm->DecoderName(Imm)); \

}

MCDisassembler::DecodeStatus DecodeStatus

static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)

Superclass for all disassemblers.

Instances of this class represent a single low-level machine instruction.

Definition at line 145 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8 ( RegClass )

Value:

static DecodeStatus Decode##RegClass##RegisterClass( \

assert(Imm < (1 << 8) && "8-bit encoding"); \

return addOperand( \

Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \

}

Definition at line 155 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SREG_7

#define DECODE_OPERAND_SREG_7 ( RegClass,
OpWidth )

Value:

DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm)

#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)

Definition at line 183 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SREG_8

#define DECODE_OPERAND_SREG_8 ( RegClass,
OpWidth )

◆ DECODE_SDWA

#define DECODE_SDWA ( DecName )

Value:

DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)

#define DECODE_OPERAND(StaticDecoderName, DecoderName)

Definition at line 395 of file AMDGPUDisassembler.cpp.

◆ DECODE_SrcOp

#define DECODE_SrcOp ( Name,
EncSize,
OpWidth,
EncImm )

Value:

assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \

return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm)); \

}

Definition at line 165 of file AMDGPUDisassembler.cpp.

◆ GET_FIELD

#define GET_FIELD ( MASK )

◆ PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE ( DIRECTIVE,
MASK )

◆ PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE ( DIRECTIVE,
MASK )

Value:

do { \

KdStream << Indent << DIRECTIVE " " \

<< ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \

} while (0)

Definition at line 2263 of file AMDGPUDisassembler.cpp.

◆ PRINT_PSEUDO_DIRECTIVE_COMMENT

#define PRINT_PSEUDO_DIRECTIVE_COMMENT ( DIRECTIVE,
MASK )

◆ SGPR_MAX

◆ DecodeStatus

◆ addOperand()

Definition at line 81 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeAVLdSt(), decodeBoolReg(), decodeDpp8FI(), decodeOperand_KImmFP(), decodeOperand_KImmFP64(), decodeOperand_VGPR_16(), decodeOperand_VSrc_f64(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), decodeSplitBarrier(), decodeSrcOp(), decodeVersionImm(), DecodeVGPR_16_Lo128RegisterClass(), DecodeVGPR_16RegisterClass(), llvm::LoongArchAsmPrinter::LowerSTATEPOINT(), llvm::VPWidenMemoryRecipe::setMask(), llvm::VPInterleaveBase::VPInterleaveBase(), llvm::VPReductionRecipe::VPReductionRecipe(), llvm::VPWidenInductionRecipe::VPWidenInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), and llvm::VPWidenPointerInductionRecipe::VPWidenPointerInductionRecipe().

◆ adjustMFMA_F8F6F4OpRegClass()

◆ CheckVGPROverflow()

◆ collectVOPModifiers()

Definition at line 1062 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, OpIdx, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), and llvm::AMDGPUDisassembler::convertVOPC64DPPInst().

◆ createAMDGPUDisassembler()

◆ createAMDGPUSymbolizer()

◆ createReservedKDBitsError()

◆ createReservedKDBytesError()

◆ decodeAV10()

◆ decodeAVLdSt() [1/2]

◆ decodeAVLdSt() [2/2]

◆ decodeBoolReg()

◆ decodeDpp8FI()

◆ decodeOperand_KImmFP()

◆ decodeOperand_KImmFP64()

◆ decodeOperand_VGPR_16()

◆ decodeOperand_VSrc_f64()

◆ decodeOperand_VSrcT16()

◆ decodeOperand_VSrcT16_Lo128()

◆ decodeOperandVOPDDstY()

◆ decodeSMEMOffset()

◆ decodeSOPPBrTarget()

◆ decodeSplitBarrier()

◆ decodeSrcA9()

◆ decodeSrcAV10()

◆ decodeSrcOp()

◆ decodeSrcReg9()

◆ decodeSrcRegOrImm9()

◆ decodeSrcRegOrImmA9()

◆ decodeVersionImm()

◆ DecodeVGPR_16_Lo128RegisterClass()

◆ DecodeVGPR_16RegisterClass()

◆ eat12Bytes()

◆ eat16Bytes()

◆ eatBytes()

◆ getBitRangeFromMask()

◆ getInlineImmVal32()

int64_t getInlineImmVal32 ( unsigned Imm) static

◆ getInlineImmVal64()

int64_t getInlineImmVal64 ( unsigned Imm) static

◆ getInlineImmValBF16()

int64_t getInlineImmValBF16 ( unsigned Imm) static

◆ getInlineImmValF16()

int64_t getInlineImmValF16 ( unsigned Imm) static

◆ insertNamedMCOperand()

Definition at line 88 of file AMDGPUDisassembler.cpp.

References I, MI, and OpIdx.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPC64DPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

◆ LLVMInitializeAMDGPUDisassembler()