LLVM: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp File Reference (original) (raw)

This file contains definition for AMDGPU ISA disassembler. More...

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This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

◆ CHECK_RESERVED_BITS

◆ CHECK_RESERVED_BITS_DESC

◆ CHECK_RESERVED_BITS_DESC_MSG

◆ CHECK_RESERVED_BITS_IMPL

| #define CHECK_RESERVED_BITS_IMPL | ( | | MASK, | | ---------------------------------------------------------------------------- | - | | ----- | | | DESC, | | | | | | MSG | | | | | ) | | | |

Value:

do { \

if (FourByteBuffer & (MASK)) { \

"kernel descriptor " DESC \

" reserved %s set" MSG, \

} \

} while (0)

static SmallString< 32 > getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes)

Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in e...

SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)

Error createStringError(std::error_code EC, char const *Fmt, const Ts &... Vals)

Create formatted StringError object.

Definition at line 2027 of file AMDGPUDisassembler.cpp.

◆ CHECK_RESERVED_BITS_MSG

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-disassembler"

◆ DECODE_OPERAND

| #define DECODE_OPERAND | ( | | StaticDecoderName, | | ----------------------- | - | | ------------------ | | | DecoderName | | | | | ) | | | |

Value:

return addOperand(Inst, DAsm->DecoderName(Imm)); \

}

static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)

Superclass for all disassemblers.

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

Definition at line 134 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_7

| #define DECODE_OPERAND_REG_7 | ( | | RegClass, | | ------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------- | | --------- | | | OpWidth | | | | | ) | DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) | | |

◆ DECODE_OPERAND_REG_8

| #define DECODE_OPERAND_REG_8 | ( | | RegClass | ) | | ------------------------------- | - | | -------- | - |

Value:

static DecodeStatus Decode##RegClass##RegisterClass( \

assert(Imm < (1 << 8) && "8-bit encoding"); \

Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \

}

Definition at line 144 of file AMDGPUDisassembler.cpp.

◆ DECODE_SDWA

| #define DECODE_SDWA | ( | | DecName | ) | DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) | | -------------------- | - | | ------- | - | ----------------------------------------------------------------------------------------------------------------------------- |

◆ DECODE_SrcOp

| #define DECODE_SrcOp | ( | | Name, | | --------------------- | - | | -------------------------------------------------------------------- | | | EncSize, | | | | | | OpWidth, | | | | | | EncImm, | | | | | | MandatoryLiteral, | | | | | | ImmWidth | | | | | ) | | | |

Value:

assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \

DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \

MandatoryLiteral, ImmWidth)); \

}

Definition at line 154 of file AMDGPUDisassembler.cpp.

◆ GET_FIELD

◆ PRINT_DIRECTIVE [1/2]

| #define PRINT_DIRECTIVE | ( | | DIRECTIVE, | | ------------------------ | - | | ---------- | | | MASK | | | | | ) | | | |

◆ PRINT_DIRECTIVE [2/2]

| #define PRINT_DIRECTIVE | ( | | DIRECTIVE, | | ------------------------ | - | | ---------- | | | MASK | | | | | ) | | | |

Value:

do { \

KdStream << Indent << DIRECTIVE " " \

<< ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \

} while (0)

Definition at line 2017 of file AMDGPUDisassembler.cpp.

◆ PRINT_PSEUDO_DIRECTIVE_COMMENT

| #define PRINT_PSEUDO_DIRECTIVE_COMMENT | ( | | DIRECTIVE, | | ----------------------------------------- | - | | ---------- | | | MASK | | | | | ) | | | |

Value:

do { \

KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \

} while (0)

Definition at line 2021 of file AMDGPUDisassembler.cpp.

◆ SGPR_MAX

◆ DecodeStatus

◆ addOperand()

Definition at line 70 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeAVLdSt(), decodeBoolReg(), decodeDpp8FI(), decodeOperand_KImmFP(), decodeOperand_VGPR_16(), decodeOperand_VSrc_f64(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperand_VSrcT16_Lo128_Deferred(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), decodeSplitBarrier(), decodeSrcOp(), decodeVersionImm(), DecodeVGPR_16_Lo128RegisterClass(), DecodeVGPR_16RegisterClass(), llvm::LoongArchAsmPrinter::LowerSTATEPOINT(), llvm::VPReplicateRecipe::VPReplicateRecipe(), llvm::VPScalarPHIRecipe::VPScalarPHIRecipe(), llvm::VPWidenEVLRecipe::VPWidenEVLRecipe(), llvm::VPWidenInductionRecipe::VPWidenInductionRecipe(), and llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe().

◆ adjustMFMA_F8F6F4OpRegClass()

◆ collectVOPModifiers()

Definition at line 921 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, llvm::AMDGPU::getNamedOperandIdx(), MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), and llvm::AMDGPUDisassembler::convertVOPC64DPPInst().

◆ createAMDGPUDisassembler()

◆ createAMDGPUSymbolizer()

◆ createReservedKDBitsError()

◆ createReservedKDBytesError()

◆ decodeAV10()

◆ decodeAVLdSt() [1/2]

◆ decodeAVLdSt() [2/2]

◆ decodeBoolReg()

◆ decodeDpp8FI()

◆ decodeOperand_KImmFP()

◆ decodeOperand_VGPR_16()

◆ decodeOperand_VSrc_f64()

◆ decodeOperand_VSrcT16()

◆ decodeOperand_VSrcT16_Lo128()

◆ decodeOperand_VSrcT16_Lo128_Deferred()

◆ decodeOperandVOPDDstY()

◆ decodeSMEMOffset()

◆ decodeSOPPBrTarget()

◆ decodeSplitBarrier()

◆ decodeSrcA9()

◆ decodeSrcAV10()

◆ decodeSrcOp()

◆ decodeSrcReg9()

◆ decodeSrcRegOrImm9()

◆ decodeSrcRegOrImmA9()

◆ decodeSrcRegOrImmDeferred9()

◆ decodeVersionImm()

◆ DecodeVGPR_16_Lo128RegisterClass()

◆ DecodeVGPR_16RegisterClass()

◆ eat12Bytes()

◆ eat16Bytes()

◆ eatBytes()

◆ getBitRangeFromMask()

◆ getInlineImmVal16()

◆ getInlineImmVal32()

◆ getInlineImmVal64()

◆ getInlineImmValBF16()

◆ getInlineImmValF16()

◆ insertNamedMCOperand()

Definition at line 77 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), I, and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPC64DPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

◆ IsAGPROperand()

◆ LLVMInitializeAMDGPUDisassembler()