LLVM: llvm::AMDGPUDisassembler Class Reference (original) (raw)

#include "[Target/AMDGPU/Disassembler/AMDGPUDisassembler.h](AMDGPUDisassembler%5F8h%5Fsource.html)"

Public Types
enum OpWidthTy { OPW32, OPW64, OPW96, OPW128, OPW160, OPW192, OPW256, OPW288, OPW320, OPW352, OPW384, OPW512, OPW1024, OPW16, OPWV216, OPWV232, OPW_LAST_, OPW_FIRST_ = OPW32 }
- Public Types inherited from llvm::MCDisassembler
enum DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 }
Ternary decode status. More...
Public Member Functions
AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
~AMDGPUDisassembler () override=default
void setABIVersion (unsigned Version) override
ELF-specific, set the ABI version from the object header.
DecodeStatus getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
const char * getRegClassName (unsigned RegClassID) const
MCOperand createRegOperand (unsigned int RegId) const
MCOperand createRegOperand (unsigned RegClassID, unsigned Val) const
MCOperand createSRegOperand (unsigned SRegClassID, unsigned Val) const
MCOperand createVGPR16Operand (unsigned RegIdx, bool IsHi) const
MCOperand errOperand (unsigned V, const Twine &ErrMsg) const
template
DecodeStatus tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
template
DecodeStatus tryDecodeInst (const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
Expected< bool > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Used to perform separate target specific disassembly for a particular symbol.
Expected< bool > decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Expected< bool > decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Expected< bool > decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Expected< bool > decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Expected< bool > decodeCOMPUTE_PGM_RSRC3 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
void convertEXPInst (MCInst &MI) const
void convertVINTERPInst (MCInst &MI) const
void convertFMAanyK (MCInst &MI, int ImmLitIdx) const
void convertSDWAInst (MCInst &MI) const
void convertMAIInst (MCInst &MI) const
f8f6f4 instructions have different pseudos depending on the used formats.
void convertDPP8Inst (MCInst &MI) const
void convertMIMGInst (MCInst &MI) const
void convertVOP3DPPInst (MCInst &MI) const
void convertVOP3PDPPInst (MCInst &MI) const
void convertVOPCDPPInst (MCInst &MI) const
void convertVOPC64DPPInst (MCInst &MI) const
void convertMacDPPInst (MCInst &MI) const
void convertTrue16OpSel (MCInst &MI) const
unsigned getVgprClassId (const OpWidthTy Width) const
unsigned getAgprClassId (const OpWidthTy Width) const
unsigned getSgprClassId (const OpWidthTy Width) const
unsigned getTtmpClassId (const OpWidthTy Width) const
MCOperand decodeMandatoryLiteralConstant (unsigned Imm) const
MCOperand decodeLiteralConstant (bool ExtendFP64) const
MCOperand decodeSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
MCOperand decodeNonVGPRSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
MCOperand decodeVOPDDstYOp (MCInst &Inst, unsigned Val) const
MCOperand decodeSpecialReg32 (unsigned Val) const
MCOperand decodeSpecialReg64 (unsigned Val) const
MCOperand decodeSpecialReg96Plus (unsigned Val) const
MCOperand decodeSDWASrc (const OpWidthTy Width, unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const
MCOperand decodeSDWASrc16 (unsigned Val) const
MCOperand decodeSDWASrc32 (unsigned Val) const
MCOperand decodeSDWAVopcDst (unsigned Val) const
MCOperand decodeBoolReg (unsigned Val) const
MCOperand decodeSplitBarrier (unsigned Val) const
MCOperand decodeDpp8FI (unsigned Val) const
MCOperand decodeVersionImm (unsigned Imm) const
int getTTmpIdx (unsigned Val) const
const MCInstrInfo * getMCII () const
bool isVI () const
bool isGFX9 () const
bool isGFX90A () const
bool isGFX9Plus () const
bool isGFX10 () const
bool isGFX10Plus () const
bool isGFX11 () const
bool isGFX11Plus () const
bool isGFX12 () const
bool isGFX12Plus () const
bool hasArchitectedFlatScratch () const
bool hasKernargPreload () const
bool isMacDPP (MCInst &MI) const
- Public Member Functions inherited from llvm::MCDisassembler
MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
virtual ~MCDisassembler ()
virtual DecodeStatus getInstruction (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
virtual Expected< bool > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const
Used to perform separate target specific disassembly for a particular symbol.
virtual uint64_t suggestBytesToSkip (ArrayRef< uint8_t > Bytes, uint64_t Address) const
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an instruction.
bool tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
void setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
Set Symzer as the current symbolizer.
MCContext & getContext () const
const MCSubtargetInfo & getSubtargetInfo () const
virtual void setABIVersion (unsigned Version)
ELF-specific, set the ABI version from the object header.
Additional Inherited Members
- Public Attributes inherited from llvm::MCDisassembler
raw_ostream * CommentStream = nullptr
- Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo & STI
std::unique_ptr< MCSymbolizer > Symbolizer

Definition at line 93 of file AMDGPUDisassembler.h.

◆ OpWidthTy

Enumerator
OPW32
OPW64
OPW96
OPW128
OPW160
OPW192
OPW256
OPW288
OPW320
OPW352
OPW384
OPW512
OPW1024
OPW16
OPWV216
OPWV232
OPW_LAST_
OPW_FIRST_

Definition at line 217 of file AMDGPUDisassembler.h.

◆ ~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( ) overridedefault

◆ convertDPP8Inst()

void AMDGPUDisassembler::convertDPP8Inst ( MCInst & MI ) const

◆ convertEXPInst()

void AMDGPUDisassembler::convertEXPInst ( MCInst & MI ) const

◆ convertFMAanyK()

void AMDGPUDisassembler::convertFMAanyK ( MCInst & MI,
int ImmLitIdx
) const

◆ convertMacDPPInst()

void AMDGPUDisassembler::convertMacDPPInst ( MCInst & MI ) const

◆ convertMAIInst()

void AMDGPUDisassembler::convertMAIInst ( MCInst & MI ) const

◆ convertMIMGInst()

void AMDGPUDisassembler::convertMIMGInst ( MCInst & MI ) const

Definition at line 1062 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::SIInstrFlags::MIMG, llvm::popcount(), llvm::MCDisassembler::STI, and llvm::SIInstrFlags::VSAMPLE.

Referenced by getInstruction().

◆ convertSDWAInst()

void AMDGPUDisassembler::convertSDWAInst ( MCInst & MI ) const

◆ convertTrue16OpSel()

void AMDGPUDisassembler::convertTrue16OpSel ( MCInst & MI ) const

Definition at line 950 of file AMDGPUDisassembler.cpp.

References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by convertDPP8Inst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOPC64DPPInst(), and getInstruction().

◆ convertVINTERPInst()

void AMDGPUDisassembler::convertVINTERPInst ( MCInst & MI ) const

◆ convertVOP3DPPInst()

void AMDGPUDisassembler::convertVOP3DPPInst ( MCInst & MI ) const

◆ convertVOP3PDPPInst()

void AMDGPUDisassembler::convertVOP3PDPPInst ( MCInst & MI ) const

◆ convertVOPC64DPPInst()

void AMDGPUDisassembler::convertVOPC64DPPInst ( MCInst & MI ) const

◆ convertVOPCDPPInst()

void AMDGPUDisassembler::convertVOPCDPPInst ( MCInst & MI ) const

◆ createRegOperand() [1/2]

Definition at line 1306 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().

◆ createRegOperand() [2/2]

◆ createSRegOperand()

◆ createVGPR16Operand()

◆ decodeBoolReg()

◆ decodeCOMPUTE_PGM_RSRC1()

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters

FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream - Stream to write the disassembled directives to.

Definition at line 2046 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, CHECK_RESERVED_BITS_DESC_MSG, CHECK_RESERVED_BITS_MSG, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC2()

◆ decodeCOMPUTE_PGM_RSRC3()

◆ decodeDpp8FI()

◆ decodeFPImmed()

◆ decodeIntImmed()

◆ decodeKernelDescriptor()

Definition at line 2467 of file AMDGPUDisassembler.cpp.

References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), llvm::createStringError(), decodeKernelDescriptorDirective(), isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), and llvm::raw_string_ostream::str().

Referenced by onSymbolStart().

◆ decodeKernelDescriptorDirective()

Definition at line 2315 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, createReservedKDBitsError(), createReservedKDBytesError(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), and llvm::DataExtractor::Cursor::tell().

Referenced by decodeKernelDescriptor().

◆ decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant ( bool ExtendFP64 ) const

◆ decodeMandatoryLiteralConstant()

◆ decodeNonVGPRSrcOp()

Definition at line 1672 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), llvm::AMDGPU::FP64, getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW128, OPW16, OPW256, OPW32, OPW512, OPW64, OPW96, OPWV216, OPWV232, and SGPR_MAX.

Referenced by decodeSrcOp().

◆ decodeSDWASrc()

Definition at line 1822 of file AMDGPUDisassembler.cpp.

References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

◆ decodeSDWASrc16()

◆ decodeSDWASrc32()

◆ decodeSDWAVopcDst()

Definition at line 1872 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, SGPR_MAX, and llvm::MCDisassembler::STI.

◆ decodeSpecialReg32()

◆ decodeSpecialReg64()

◆ decodeSpecialReg96Plus()

◆ decodeSplitBarrier()

◆ decodeSrcOp()

◆ decodeVersionImm()

◆ decodeVOPDDstYOp()

◆ errOperand()

◆ getAgprClassId()

Definition at line 1571 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSrcOp().

◆ getInstruction()

Returns the disassembly of a single instruction.

Parameters

Instr - An MCInst to populate with the contents of the instruction.
Size - A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address - The address, in the memory space of region, of the first byte of the instruction.
Bytes - A reference to the actual bytes of the instruction.
CStream - The stream to print comments and annotations on.

Returns

- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 513 of file AMDGPUDisassembler.cpp.

References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMAIInst(), convertMIMGInst(), convertSDWAInst(), convertTrue16OpSel(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPC64DPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, eat12Bytes(), eat16Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasGDS(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX10(), isGFX11(), isGFX11Plus(), isGFX12(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), llvm::SIInstrFlags::IsMAI, isVI(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::SDWA, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.

◆ getMCII()

◆ getRegClassName()

◆ getSgprClassId()

Definition at line 1597 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTtmpClassId()

Definition at line 1621 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx ( unsigned Val ) const

◆ getVgprClassId()

Definition at line 1545 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW192, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().

◆ hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch ( ) const

◆ hasKernargPreload()

bool AMDGPUDisassembler::hasKernargPreload ( ) const

◆ isGFX10()

bool AMDGPUDisassembler::isGFX10 ( ) const

◆ isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus ( ) const

◆ isGFX11()

bool AMDGPUDisassembler::isGFX11 ( ) const

◆ isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus ( ) const

◆ isGFX12()

bool AMDGPUDisassembler::isGFX12 ( ) const

◆ isGFX12Plus()

bool AMDGPUDisassembler::isGFX12Plus ( ) const

◆ isGFX9()

bool AMDGPUDisassembler::isGFX9 ( ) const

◆ isGFX90A()

bool AMDGPUDisassembler::isGFX90A ( ) const

◆ isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus ( ) const

◆ isMacDPP()

bool AMDGPUDisassembler::isMacDPP ( MCInst & MI ) const

◆ isVI()

bool AMDGPUDisassembler::isVI ( ) const

◆ onSymbolStart()

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns false. So all targets by default decline to treat symbols separately.

Parameters

Symbol - The symbol.
Size - The number of bytes consumed.
Address - The address, in the memory space of region, of the first byte of the symbol.
Bytes - A reference to the actual bytes at the symbol location.

Returns

- True if this symbol triggered some target specific disassembly for this symbol. Size must be set with the number of bytes consumed.

Reimplemented from llvm::MCDisassembler.

Definition at line 2507 of file AMDGPUDisassembler.cpp.

References llvm::Address, llvm::createStringError(), decodeKernelDescriptor(), Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.

◆ setABIVersion()

void AMDGPUDisassembler::setABIVersion ( unsigned Version) overridevirtual

◆ tryDecodeInst() [1/2]

template

◆ tryDecodeInst() [2/2]

template

The documentation for this class was generated from the following files: