LLVM: lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Source File (original) (raw)
1
2
3
4
5
6
7
8
9
24
25using namespace llvm;
27
29
30
31
32
33
34
35
36
37
38
39
40
41 OS << Reg.id();
42}
43
50
51void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
55 if (Op.isExpr()) {
57 return;
58 }
59
60
61
64 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
65 else
66 printU32ImmOperand(MI, OpNo, STI, O);
67}
68
69void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
71 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
72}
73
74void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
77 const MCOperand &Op = MI->getOperand(OpNo);
78 if (Op.isExpr()) {
79 MAI.printExpr(O, *Op.getExpr());
80 return;
81 }
82
84}
85
86void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
89
90 const MCOperand &Op = MI->getOperand(OpNo);
91 if (Op.isExpr()) {
92 MAI.printExpr(O, *Op.getExpr());
93 return;
94 }
95
96 printLiteral64(Op.getImm(), O, true);
97}
98
99void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
101 if (MI->getOperand(OpNo).getImm()) {
102 O << ' ' << BitName;
103 }
104}
105
106void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
109 uint32_t Imm = MI->getOperand(OpNo).getImm();
110 if (Imm != 0) {
111 O << " offset:";
112
113
114 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
117 O << formatDec(SignExtend32<24>(Imm));
118 else
119 printU16ImmDecOperand(MI, OpNo, O);
120 }
121}
122
123void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
126 uint32_t Imm = MI->getOperand(OpNo).getImm();
127 if (Imm != 0) {
128 O << " offset:";
129
130 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
134
135 if (AllowNegative)
137 else
138 printU16ImmDecOperand(MI, OpNo, O);
139 }
140}
141
142void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
145 printU32ImmOperand(MI, OpNo, STI, O);
146}
147
148void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
151 O << formatHex(MI->getOperand(OpNo).getImm());
152}
153
154void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
157 printU32ImmOperand(MI, OpNo, STI, O);
158}
159
160void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
162 auto Imm = MI->getOperand(OpNo).getImm();
163
167
169 O << " scale_offset";
170
171 printTH(MI, TH, Scope, O);
172 printScope(Scope, O);
173
175 O << " nv";
176
177 return;
178 }
179
183 : " glc");
187 O << " dlc";
191 O << " /* unexpected cache policy bit */";
192}
193
194void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
196
197 if (TH == 0)
198 return;
199
200 const unsigned Opcode = MI->getOpcode();
201 const MCInstrDesc &TID = MII.get(Opcode);
204
205 O << " th:";
206
208 O << "TH_ATOMIC_";
212 else
217 O << "RETURN";
218 else
220 } else {
223 else {
224 O << (IsStore ? "TH_STORE_" : "TH_LOAD_");
225 switch (TH) {
227 O << "NT";
228 break;
230 O << "HT";
231 break;
234 : (IsStore ? "WB" : "LU"));
235 break;
237 O << "NT_RT";
238 break;
240 O << "RT_NT";
241 break;
243 O << "NT_HT";
244 break;
246 O << "NT_WB";
247 break;
248 default:
250 }
251 }
252 }
253}
254
255void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
257 return;
258
259 O << " scope:";
260
262 O << "SCOPE_SE";
264 O << "SCOPE_DEV";
266 O << "SCOPE_SYS";
267 else
269}
270
271void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
273 unsigned Dim = MI->getOperand(OpNo).getImm();
274 O << " dim:SQ_RSRC_IMG_";
275
277 if (DimInfo)
279 else
280 O << Dim;
281}
282
283void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
285 if (STI.hasFeature(AMDGPU::FeatureR128A16))
286 printNamedBit(MI, OpNo, O, "a16");
287 else
288 printNamedBit(MI, OpNo, O, "r128");
289}
290
291void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
294}
295
296void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
299 using namespace llvm::AMDGPU::MTBUFFormat;
300
301 int OpNo =
302 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
304
305 unsigned Val = MI->getOperand(OpNo).getImm();
307 if (Val == UFMT_DEFAULT)
308 return;
311 } else {
312 O << " format:" << Val;
313 }
314 } else {
315 if (Val == DFMT_NFMT_DEFAULT)
316 return;
318 unsigned Dfmt;
319 unsigned Nfmt;
321 O << " format:[";
322 if (Dfmt != DFMT_DEFAULT) {
324 if (Nfmt != NFMT_DEFAULT) {
325 O << ',';
326 }
327 }
328 if (Nfmt != NFMT_DEFAULT) {
330 }
331 O << ']';
332 } else {
333 O << " format:" << Val;
334 }
335 }
336}
337
338
339
341 unsigned Enc = MRI.getEncodingValue(Reg);
343 if (Idx < 0x100)
344 return Reg;
345
346 unsigned RegNo = Idx % 0x100;
348 if (RC->getID() == AMDGPU::VGPR_16RegClassID) {
349
350 RegNo *= 2;
352 ++RegNo;
353 }
354
356}
357
358
364 if (!VgprMSBs)
365 return Reg;
366
367 unsigned Enc = MRI.getEncodingValue(Reg);
369 return Reg;
370
372 if (.first)
373 return Reg;
374 unsigned Opc = Desc.getOpcode();
375 unsigned I;
377 if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
378 (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.first[I]) == OpNo)
379 break;
380 if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
381 (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.second[I]) == OpNo)
382 break;
383 }
384 if (I == 4)
385 return Reg;
386 unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3;
387 if (!OpMSBs)
388 return Reg;
390 return NewReg;
391 return Reg;
392}
393
396#if !defined(NDEBUG)
397 switch (Reg.id()) {
398 case AMDGPU::FP_REG:
399 case AMDGPU::SP_REG:
400 case AMDGPU::PRIVATE_RSRC_REG:
401 llvm_unreachable("pseudo-register should not ever be emitted");
402 default:
403 break;
404 }
405#endif
406
409
410 if (PrintReg != Reg)
412}
413
422
423void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
425 auto Opcode = MI->getOpcode();
427 if (OpNo == 0) {
429 O << "_e64_dpp";
432 O << "_e64";
434 O << "_dpp";
436 O << "_sdwa";
439 O << "_e32";
440 O << " ";
441 }
442
443 printRegularOperand(MI, OpNo, STI, O);
444
445
446 switch (Opcode) {
447 default: break;
448
449 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
450 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
451 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
452 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
453 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
454 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
455 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
456 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
457 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
458 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
459 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
460 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
461 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
462 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
463 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
464 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
465 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
466 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
467 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
468 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
469 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
470 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
471 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
472 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
473 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
474 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
475 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
476 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
477 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
478 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
479 printDefaultVccOperand(false, STI, O);
480 break;
481 }
482}
483
484void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
487 O << " ";
488 else
489 O << "_e32 ";
490
491 printRegularOperand(MI, OpNo, STI, O);
492}
493
494void AMDGPUInstPrinter::printAVLdSt32Align2RegOp(const MCInst *MI,
495 unsigned OpNo,
498 MCRegister Reg = MI->getOperand(OpNo).getReg();
499
500
501 if (MCRegister SubReg = MRI.getSubReg(Reg, AMDGPU::sub0))
504}
505
506void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
509 int32_t SImm = static_cast<int32_t>(Imm);
511 O << SImm;
512 return;
513 }
514
515 if (printImmediateFloat32(Imm, STI, O))
516 return;
517
518 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
519}
520
523 if (Imm == 0x3C00)
524 O << "1.0";
525 else if (Imm == 0xBC00)
526 O << "-1.0";
527 else if (Imm == 0x3800)
528 O << "0.5";
529 else if (Imm == 0xB800)
530 O << "-0.5";
531 else if (Imm == 0x4000)
532 O << "2.0";
533 else if (Imm == 0xC000)
534 O << "-2.0";
535 else if (Imm == 0x4400)
536 O << "4.0";
537 else if (Imm == 0xC400)
538 O << "-4.0";
539 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
540 O << "0.15915494";
541 else
542 return false;
543
544 return true;
545}
546
549 if (Imm == 0x3F80)
550 O << "1.0";
551 else if (Imm == 0xBF80)
552 O << "-1.0";
553 else if (Imm == 0x3F00)
554 O << "0.5";
555 else if (Imm == 0xBF00)
556 O << "-0.5";
557 else if (Imm == 0x4000)
558 O << "2.0";
559 else if (Imm == 0xC000)
560 O << "-2.0";
561 else if (Imm == 0x4080)
562 O << "4.0";
563 else if (Imm == 0xC080)
564 O << "-4.0";
565 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
566 O << "0.15915494";
567 else
568 return false;
569
570 return true;
571}
572
573void AMDGPUInstPrinter::printImmediateBF16(uint32_t Imm,
576 int16_t SImm = static_cast<int16_t>(Imm);
578 O << SImm;
579 return;
580 }
581
583 return;
584
585 O << formatHex(static_cast<uint64_t>(Imm));
586}
587
588void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
591 int16_t SImm = static_cast<int16_t>(Imm);
593 O << SImm;
594 return;
595 }
596
597 uint16_t HImm = static_cast<uint16_t>(Imm);
599 return;
600
601 uint64_t Imm16 = static_cast<uint16_t>(Imm);
603}
604
605void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, uint8_t OpType,
608 int32_t SImm = static_cast<int32_t>(Imm);
610 O << SImm;
611 return;
612 }
613
614 switch (OpType) {
617 if (printImmediateFloat32(Imm, STI, O))
618 return;
619 break;
624 return;
625 break;
630 return;
631 break;
633 break;
634 default:
636 }
637
638 O << formatHex(static_cast<uint64_t>(Imm));
639}
640
641bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
645 O << "0.0";
647 O << "1.0";
649 O << "-1.0";
651 O << "0.5";
653 O << "-0.5";
655 O << "2.0";
657 O << "-2.0";
659 O << "4.0";
661 O << "-4.0";
662 else if (Imm == 0x3e22f983 &&
663 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
664 O << "0.15915494";
665 else
666 return false;
667
668 return true;
669}
670
671void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
674 int32_t SImm = static_cast<int32_t>(Imm);
676 O << SImm;
677 return;
678 }
679
680 if (printImmediateFloat32(Imm, STI, O))
681 return;
682
683 O << formatHex(static_cast<uint64_t>(Imm));
684}
685
686void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
689 int64_t SImm = static_cast<int64_t>(Imm);
690 if (SImm >= -16 && SImm <= 64) {
691 O << SImm;
692 return;
693 }
694
696 O << "0.0";
698 O << "1.0";
700 O << "-1.0";
702 O << "0.5";
704 O << "-0.5";
706 O << "2.0";
708 O << "-2.0";
710 O << "4.0";
712 O << "-4.0";
713 else if (Imm == 0x3fc45f306dc9c882 &&
714 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
715 O << "0.15915494309189532";
716 else
717 printLiteral64(Imm, O, IsFP);
718}
719
720void AMDGPUInstPrinter::printLiteral64(uint64_t Imm, raw_ostream &O,
721 bool IsFP) {
723 O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
724 else
726}
727
728void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
731 unsigned Imm = MI->getOperand(OpNo).getImm();
732 if ()
733 return;
734
736 switch (MI->getOpcode()) {
737 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
738 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
739 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
740 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
741 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
742 << ((Imm >> 2) & 1) << ']';
743 return;
744 }
745 }
746
748}
749
750void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
753 if (!FirstOperand)
754 O << ", ";
756 ? AMDGPU::VCC_LO
757 : AMDGPU::VCC,
759 if (FirstOperand)
760 O << ", ";
761}
762
763bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
764 unsigned OpNo) const {
768 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
769 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
770}
771
772
773void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
776 unsigned Opc = MI->getOpcode();
777 const MCInstrDesc &Desc = MII.get(Opc);
778 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
779
780
781
782 if ((OpNo == 0 ||
785 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
786 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
787 printDefaultVccOperand(true, STI, O);
788
789 printRegularOperand(MI, OpNo, STI, O);
790}
791
792
793void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
796 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
797
798 if (OpNo >= MI->getNumOperands()) {
799 O << "/*Missing OP" << OpNo << "*/";
800 return;
801 }
802
803 const MCOperand &Op = MI->getOperand(OpNo);
804 if (Op.isReg()) {
806
807
808
809
810 const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
812 int16_t RCID = MII.getOpRegClassID(
814 const MCRegisterClass &RC = MRI.getRegClass(RCID);
818 (OpInfo.RegClass == AMDGPU::SReg_1 ||
819 OpInfo.RegClass == AMDGPU::SReg_1_XEXEC);
820
821
822
823
824
825 if (!IsWaveSizeOp) {
826 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC)
827 << "\' register class*/";
828 }
829 }
830 }
831 } else if (Op.isImm()) {
832 const uint8_t OpTy = Desc.operands()[OpNo].OperandType;
833 switch (OpTy) {
844 printImmediate32(Op.getImm(), STI, O);
845 break;
848 printImmediate64(Op.getImm(), STI, O, false);
849 break;
853 printImmediate64(Op.getImm(), STI, O, true);
854 break;
857 printImmediateInt16(Op.getImm(), STI, O);
858 break;
861 printImmediateF16(Op.getImm(), STI, O);
862 break;
865 printImmediateBF16(Op.getImm(), STI, O);
866 break;
874 printImmediateV216(Op.getImm(), OpTy, STI, O);
875 break;
879 break;
881
882
883 printImmediate32(Op.getImm(), STI, O);
884 O << "/*Invalid immediate*/";
885 break;
886 default:
887
888
890 }
891 } else if (Op.isExpr()) {
892 const MCExpr *Exp = Op.getExpr();
893 MAI.printExpr(O, *Exp);
894 } else {
895 O << "/*INV_OP*/";
896 }
897
898
899 switch (MI->getOpcode()) {
900 default: break;
901
902 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
903 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
904 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
905 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
906 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
907 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
908 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
909 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
910 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
911 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
912 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
913 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
914 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
915 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
916 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
917 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
918 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
919 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
920 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
921 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
922 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
923 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
924 case AMDGPU::V_CNDMASK_B32_e32_gfx12:
925 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
926 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
927 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
928 case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
929 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
930 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
931 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
932 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
933 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
934 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
935 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
936
937 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
938 case AMDGPU::V_CNDMASK_B32_e32_vi:
939 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
940 AMDGPU::OpName::src1))
941 printDefaultVccOperand(OpNo == 0, STI, O);
942 break;
943 }
944
946 int SOffsetIdx =
947 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
948 assert(SOffsetIdx != -1);
949 if ((int)OpNo == SOffsetIdx)
950 printSymbolicFormat(MI, STI, O);
951 }
952}
953
954void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
955 unsigned OpNo,
958 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
959 if (needsImpliedVcc(Desc, OpNo))
960 printDefaultVccOperand(true, STI, O);
961
962 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
963
964
965
966
967 bool NegMnemo = false;
968
970 if (OpNo + 1 < MI->getNumOperands() &&
972 const MCOperand &Op = MI->getOperand(OpNo + 1);
973 NegMnemo = Op.isImm();
974 }
975 if (NegMnemo) {
976 O << "neg(";
977 } else {
978 O << '-';
979 }
980 }
981
983 O << '|';
984 printRegularOperand(MI, OpNo + 1, STI, O);
986 O << '|';
987
988 if (NegMnemo) {
989 O << ')';
990 }
991
992
993 switch (MI->getOpcode()) {
994 default:
995 break;
996
997 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
998 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
999 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
1000 if ((int)OpNo + 1 ==
1001 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
1002 printDefaultVccOperand(OpNo == 0, STI, O);
1003 break;
1004 }
1005}
1006
1007void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
1008 unsigned OpNo,
1011 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
1012 if (needsImpliedVcc(Desc, OpNo))
1013 printDefaultVccOperand(true, STI, O);
1014
1015 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
1017 O << "sext(";
1018 printRegularOperand(MI, OpNo + 1, STI, O);
1020 O << ')';
1021
1022
1023 switch (MI->getOpcode()) {
1024 default: break;
1025
1026 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
1027 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
1028 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
1029 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1030 AMDGPU::OpName::src1))
1031 printDefaultVccOperand(OpNo == 0, STI, O);
1032 break;
1033 }
1034}
1035
1036void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
1040 llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
1041
1042 unsigned Imm = MI->getOperand(OpNo).getImm();
1044 for (size_t i = 1; i < 8; ++i) {
1046 }
1047 O << ']';
1048}
1049
1050void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
1053 using namespace AMDGPU::DPP;
1054
1055 unsigned Imm = MI->getOperand(OpNo).getImm();
1056 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
1057
1060 O << " /* DP ALU dpp only supports "
1061 << (isGFX12(STI) ? "row_share" : "row_newbcast") << " */";
1062 return;
1063 }
1064 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
1065 O << "quad_perm:[";
1070 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
1071 (Imm <= DppCtrl::ROW_SHL_LAST)) {
1072 O << "row_shl:" << formatDec(Imm - DppCtrl::ROW_SHL0);
1073 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
1074 (Imm <= DppCtrl::ROW_SHR_LAST)) {
1075 O << "row_shr:" << formatDec(Imm - DppCtrl::ROW_SHR0);
1076 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
1077 (Imm <= DppCtrl::ROW_ROR_LAST)) {
1078 O << "row_ror:" << formatDec(Imm - DppCtrl::ROW_ROR0);
1079 } else if (Imm == DppCtrl::WAVE_SHL1) {
1081 O << "/* wave_shl is not supported starting from GFX10 */";
1082 return;
1083 }
1084 O << "wave_shl:1";
1085 } else if (Imm == DppCtrl::WAVE_ROL1) {
1087 O << "/* wave_rol is not supported starting from GFX10 */";
1088 return;
1089 }
1090 O << "wave_rol:1";
1091 } else if (Imm == DppCtrl::WAVE_SHR1) {
1093 O << "/* wave_shr is not supported starting from GFX10 */";
1094 return;
1095 }
1096 O << "wave_shr:1";
1097 } else if (Imm == DppCtrl::WAVE_ROR1) {
1099 O << "/* wave_ror is not supported starting from GFX10 */";
1100 return;
1101 }
1102 O << "wave_ror:1";
1103 } else if (Imm == DppCtrl::ROW_MIRROR) {
1104 O << "row_mirror";
1105 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1106 O << "row_half_mirror";
1107 } else if (Imm == DppCtrl::BCAST15) {
1109 O << "/* row_bcast is not supported starting from GFX10 */";
1110 return;
1111 }
1112 O << "row_bcast:15";
1113 } else if (Imm == DppCtrl::BCAST31) {
1115 O << "/* row_bcast is not supported starting from GFX10 */";
1116 return;
1117 }
1118 O << "row_bcast:31";
1119 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1120 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1122 O << "row_newbcast:";
1124 O << "row_share:";
1125 } else {
1126 O << " /* row_newbcast/row_share is not supported on ASICs earlier "
1127 "than GFX90A/GFX10 */";
1128 return;
1129 }
1131 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1132 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1134 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
1135 return;
1136 }
1137 O << "row_xmask:" << formatDec(Imm - DppCtrl::ROW_XMASK_FIRST);
1138 } else {
1139 O << "/* Invalid dpp_ctrl value */";
1140 }
1141}
1142
1143void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1146 unsigned Imm = MI->getOperand(OpNo).getImm();
1147 if (Imm) {
1148 O << " bound_ctrl:1";
1149 }
1150}
1151
1152void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
1154 using namespace llvm::AMDGPU::DPP;
1155 unsigned Imm = MI->getOperand(OpNo).getImm();
1156 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1157 O << " fi:1";
1158 }
1159}
1160
1161void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
1163 using namespace llvm::AMDGPU::SDWA;
1164
1165 unsigned Imm = MI->getOperand(OpNo).getImm();
1166 switch (Imm) {
1167 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1168 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1169 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1170 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1171 case SdwaSel::WORD_0: O << "WORD_0"; break;
1172 case SdwaSel::WORD_1: O << "WORD_1"; break;
1173 case SdwaSel::DWORD: O << "DWORD"; break;
1174 default: llvm_unreachable("Invalid SDWA data select operand");
1175 }
1176}
1177
1178void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1181 O << "dst_sel:";
1182 printSDWASel(MI, OpNo, O);
1183}
1184
1185void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1188 O << "src0_sel:";
1189 printSDWASel(MI, OpNo, O);
1190}
1191
1192void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1195 O << "src1_sel:";
1196 printSDWASel(MI, OpNo, O);
1197}
1198
1199void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1202 using namespace llvm::AMDGPU::SDWA;
1203
1204 O << "dst_unused:";
1205 unsigned Imm = MI->getOperand(OpNo).getImm();
1206 switch (Imm) {
1207 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1208 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1209 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1210 default: llvm_unreachable("Invalid SDWA dest_unused operand");
1211 }
1212}
1213
1214void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1216 unsigned N) {
1217 unsigned Opc = MI->getOpcode();
1218 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1219 unsigned En = MI->getOperand(EnIdx).getImm();
1220
1221 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1222
1223
1224 if (MI->getOperand(ComprIdx).getImm())
1226
1227 if (En & (1 << N))
1229 else
1230 O << "off";
1231}
1232
1233void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1236 printExpSrcN(MI, OpNo, STI, O, 0);
1237}
1238
1239void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1242 printExpSrcN(MI, OpNo, STI, O, 1);
1243}
1244
1245void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1248 printExpSrcN(MI, OpNo, STI, O, 2);
1249}
1250
1251void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1254 printExpSrcN(MI, OpNo, STI, O, 3);
1255}
1256
1257void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1260 using namespace llvm::AMDGPU::Exp;
1261
1262
1263 unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1264
1266 StringRef TgtName;
1268 O << ' ' << TgtName;
1269 if (Index >= 0)
1271 } else {
1272 O << " invalid_target_" << Id;
1273 }
1274}
1275
1277 bool IsPacked, bool HasDstSel) {
1279
1280 for (int I = 0; I < NumOps; ++I) {
1281 if (!!(Ops[I] & Mod) != DefaultValue)
1282 return false;
1283 }
1284
1286 return false;
1287
1288 return true;
1289}
1290
1291void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1293 unsigned Mod,
1295 unsigned Opc = MI->getOpcode();
1297 int Ops[3];
1298
1299 std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
1300 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
1301 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
1302 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
1304
1305 for (auto [SrcMod, Src] : MOps) {
1307 break;
1308
1309 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, SrcMod);
1311 (ModIdx != -1) ? MI->getOperand(ModIdx).getImm() : DefaultValue;
1312 }
1313
1314
1315
1318 Ops[NumOps++] = DefaultValue;
1319 int Mod2Idx =
1320 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
1321 assert(Mod2Idx != -1);
1322 Ops[NumOps++] = MI->getOperand(Mod2Idx).getImm();
1323 }
1324
1325 const bool HasDst =
1326 (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1) ||
1327 (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst) != -1);
1328
1329
1330
1335 for (AMDGPU::OpName OpName :
1336 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
1337 AMDGPU::OpName::src2_modifiers}) {
1338 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1339 if (Idx != -1)
1340 Ops[NumOps++] = MI->getOperand(Idx).getImm();
1341 else
1343 }
1344 }
1345
1346 const bool HasDstSel =
1349
1352
1354 return;
1355
1357 ListSeparator Sep(",");
1358 for (int I = 0; I < NumOps; ++I)
1359 O << Sep << !!(Ops[I] & Mod);
1360
1361 if (HasDstSel) {
1363 }
1364
1365 O << ']';
1366}
1367
1368void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1371 unsigned Opc = MI->getOpcode();
1373 auto SrcMod =
1374 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1375 unsigned Mod = MI->getOperand(SrcMod).getImm();
1378 if (Index0 || Index1)
1379 O << " op_sel:[" << Index0 << ',' << Index1 << ']';
1380 return;
1381 }
1383 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1384 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1387 if (FI || BC)
1388 O << " op_sel:[" << FI << ',' << BC << ']';
1389 return;
1390 }
1391
1393}
1394
1395void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1399}
1400
1401void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1405}
1406
1407void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1411}
1412
1413void AMDGPUInstPrinter::printIndexKey8bit(const MCInst *MI, unsigned OpNo,
1416 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1417 if (Imm == 0)
1418 return;
1419
1420 O << " index_key:" << Imm;
1421}
1422
1423void AMDGPUInstPrinter::printIndexKey16bit(const MCInst *MI, unsigned OpNo,
1426 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1427 if (Imm == 0)
1428 return;
1429
1430 O << " index_key:" << Imm;
1431}
1432
1433void AMDGPUInstPrinter::printIndexKey32bit(const MCInst *MI, unsigned OpNo,
1436 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1437 if (Imm == 0)
1438 return;
1439
1440 O << " index_key:" << Imm;
1441}
1442
1443void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo,
1446 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1447 if (Imm == 0)
1448 return;
1449
1450 O << " matrix_" << AorB << "_fmt:";
1451 switch (Imm) {
1452 default:
1454 break;
1455 case WMMA::MatrixFMT::MATRIX_FMT_FP8:
1456 O << "MATRIX_FMT_FP8";
1457 break;
1458 case WMMA::MatrixFMT::MATRIX_FMT_BF8:
1459 O << "MATRIX_FMT_BF8";
1460 break;
1461 case WMMA::MatrixFMT::MATRIX_FMT_FP6:
1462 O << "MATRIX_FMT_FP6";
1463 break;
1464 case WMMA::MatrixFMT::MATRIX_FMT_BF6:
1465 O << "MATRIX_FMT_BF6";
1466 break;
1467 case WMMA::MatrixFMT::MATRIX_FMT_FP4:
1468 O << "MATRIX_FMT_FP4";
1469 break;
1470 }
1471}
1472
1473void AMDGPUInstPrinter::printMatrixAFMT(const MCInst *MI, unsigned OpNo,
1476 printMatrixFMT(MI, OpNo, STI, O, 'a');
1477}
1478
1479void AMDGPUInstPrinter::printMatrixBFMT(const MCInst *MI, unsigned OpNo,
1482 printMatrixFMT(MI, OpNo, STI, O, 'b');
1483}
1484
1485void AMDGPUInstPrinter::printMatrixScale(const MCInst *MI, unsigned OpNo,
1488 auto Imm = MI->getOperand(OpNo).getImm() & 1;
1489 if (Imm == 0)
1490 return;
1491
1492 O << " matrix_" << AorB << "_scale:";
1493 switch (Imm) {
1494 default:
1496 break;
1497 case WMMA::MatrixScale::MATRIX_SCALE_ROW0:
1498 O << "MATRIX_SCALE_ROW0";
1499 break;
1500 case WMMA::MatrixScale::MATRIX_SCALE_ROW1:
1501 O << "MATRIX_SCALE_ROW1";
1502 break;
1503 }
1504}
1505
1506void AMDGPUInstPrinter::printMatrixAScale(const MCInst *MI, unsigned OpNo,
1509 printMatrixScale(MI, OpNo, STI, O, 'a');
1510}
1511
1512void AMDGPUInstPrinter::printMatrixBScale(const MCInst *MI, unsigned OpNo,
1515 printMatrixScale(MI, OpNo, STI, O, 'b');
1516}
1517
1518void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo,
1521 auto Imm = MI->getOperand(OpNo).getImm() & 3;
1522 if (Imm == 0)
1523 return;
1524
1525 O << " matrix_" << AorB << "_scale_fmt:";
1526 switch (Imm) {
1527 default:
1529 break;
1530 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E8:
1531 O << "MATRIX_SCALE_FMT_E8";
1532 break;
1533 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E5M3:
1534 O << "MATRIX_SCALE_FMT_E5M3";
1535 break;
1536 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E4M3:
1537 O << "MATRIX_SCALE_FMT_E4M3";
1538 break;
1539 }
1540}
1541
1542void AMDGPUInstPrinter::printMatrixAScaleFmt(const MCInst *MI, unsigned OpNo,
1545 printMatrixScaleFmt(MI, OpNo, STI, O, 'a');
1546}
1547
1548void AMDGPUInstPrinter::printMatrixBScaleFmt(const MCInst *MI, unsigned OpNo,
1551 printMatrixScaleFmt(MI, OpNo, STI, O, 'b');
1552}
1553
1554void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1557 unsigned Imm = MI->getOperand(OpNum).getImm();
1558 switch (Imm) {
1559 case 0:
1560 O << "p10";
1561 break;
1562 case 1:
1563 O << "p20";
1564 break;
1565 case 2:
1566 O << "p0";
1567 break;
1568 default:
1569 O << "invalid_param_" << Imm;
1570 }
1571}
1572
1573void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1576 unsigned Attr = MI->getOperand(OpNum).getImm();
1577 O << "attr" << Attr;
1578}
1579
1580void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1583 unsigned Chan = MI->getOperand(OpNum).getImm();
1584 O << '.' << "xyzw"[Chan & 0x3];
1585}
1586
1587void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
1590 using namespace llvm::AMDGPU::VGPRIndexMode;
1591 unsigned Val = MI->getOperand(OpNo).getImm();
1592
1593 if ((Val & ~ENABLE_MASK) != 0) {
1594 O << formatHex(static_cast<uint64_t>(Val));
1595 } else {
1596 O << "gpr_idx(";
1597 ListSeparator Sep(",");
1598 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1599 if (Val & (1 << ModeId))
1601 }
1602 O << ')';
1603 }
1604}
1605
1606void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1609 printRegularOperand(MI, OpNo, STI, O);
1610 O << ", ";
1611 printRegularOperand(MI, OpNo + 1, STI, O);
1612}
1613
1619 if (Op.getImm() == 1) {
1620 O << Asm;
1621 } else {
1623 }
1624}
1625
1630 if (Op.getImm() == 1)
1631 O << Asm;
1632}
1633
1637 int Imm = MI->getOperand(OpNo).getImm();
1639 O << " mul:2";
1641 O << " mul:4";
1643 O << " div:2";
1644}
1645
1650
1651 const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1652
1657
1659
1662 O << "sendmsg(" << MsgName;
1664 O << ", " << getMsgOpName(MsgId, OpId, STI);
1667 }
1668 }
1669 O << ')';
1671 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1672 } else {
1673 O << Imm16;
1674 }
1675}
1676
1682
1683 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1685
1686 O << "\"";
1687
1688 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1689 uint16_t p0 = Probe0 & Mask;
1690 uint16_t p1 = Probe1 & Mask;
1691
1692 if (p0 == p1) {
1693 if (p0 == 0) {
1694 O << "0";
1695 } else {
1696 O << "1";
1697 }
1698 } else {
1699 if (p0 == 0) {
1700 O << "p";
1701 } else {
1702 O << "i";
1703 }
1704 }
1705 }
1706
1707 O << "\"";
1708}
1709
1714
1716 if (Imm == 0) {
1717 return;
1718 }
1719
1720 O << " offset:";
1721
1722
1726 << ')';
1731 }
1732 return;
1733 }
1734
1735
1738 for (unsigned I = 0; I < LANE_NUM; ++I) {
1739 O << ",";
1742 }
1743 O << ")";
1744
1746
1750
1752
1754 O << ",";
1756 O << ")";
1757
1758 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1760
1762 O << ",";
1764 O << ")";
1765
1766 } else {
1767
1769 if (GroupSize > 1 &&
1771 OrMask < GroupSize &&
1772 XorMask == 0) {
1773
1775 O << ",";
1777 O << ",";
1779 O << ")";
1780
1781 } else {
1783 O << ",";
1785 O << ")";
1786 }
1787 }
1788 } else {
1789 printU16ImmDecOperand(MI, OpNo, O);
1790 }
1791}
1792
1797
1798 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1799 unsigned Vmcnt, Expcnt, Lgkmcnt;
1800 decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1801
1805 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1806
1808
1809 if (!IsDefaultVmcnt || PrintAll)
1810 O << Sep << "vmcnt(" << Vmcnt << ')';
1811
1812 if (!IsDefaultExpcnt || PrintAll)
1813 O << Sep << "expcnt(" << Expcnt << ')';
1814
1815 if (!IsDefaultLgkmcnt || PrintAll)
1816 O << Sep << "lgkmcnt(" << Lgkmcnt << ')';
1817}
1818
1823
1824 uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1825
1826 bool HasNonDefaultVal = false;
1828 int Id = 0;
1830 unsigned Val;
1831 bool IsDefault;
1833 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1834 if (!IsDefault || !HasNonDefaultVal)
1835 O << Sep << Name << '(' << Val << ')';
1836 }
1837 } else {
1839 }
1840}
1841
1845 const char *BadInstId = "/* invalid instid value */";
1846 static const std::array<const char *, 12> InstIds = {
1847 "NO_DEP", "VALU_DEP_1", "VALU_DEP_2",
1848 "VALU_DEP_3", "VALU_DEP_4", "TRANS32_DEP_1",
1849 "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1850 "SALU_CYCLE_1", "SALU_CYCLE_2", "SALU_CYCLE_3"};
1851
1852 const char *BadInstSkip = "/* invalid instskip value */";
1853 static const std::array<const char *, 6> InstSkips = {
1854 "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1855
1856 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1857 const char *Prefix = "";
1858
1859 unsigned Value = SImm16 & 0xF;
1861 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1862 O << Prefix << "instid0(" << Name << ')';
1863 Prefix = " | ";
1864 }
1865
1866 Value = (SImm16 >> 4) & 7;
1868 const char *Name =
1869 Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1870 O << Prefix << "instskip(" << Name << ')';
1871 Prefix = " | ";
1872 }
1873
1874 Value = (SImm16 >> 7) & 0xF;
1876 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1877 O << Prefix << "instid1(" << Name << ')';
1878 Prefix = " | ";
1879 }
1880
1881 if (!*Prefix)
1882 O << "0";
1883}
1884
1888 unsigned Val = MI->getOperand(OpNo).getImm();
1891
1892 O << "hwreg(";
1893 if (!HwRegName.empty()) {
1894 O << HwRegName;
1895 } else {
1896 O << Id;
1897 }
1899 O << ", " << Offset << ", " << Width;
1900 O << ')';
1901}
1902
1907 if (Imm == 0) {
1908 return;
1909 }
1910
1912}
1913
1914void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
1917 bool PrintInHex, bool AlwaysPrint) {
1918 int64_t V = MI->getOperand(OpNo).getImm();
1919 if (AlwaysPrint || V != 0)
1920 O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
1921}
1922
1923void AMDGPUInstPrinter::printBitOp3(const MCInst *MI, unsigned OpNo,
1926 uint8_t Imm = MI->getOperand(OpNo).getImm();
1927 if ()
1928 return;
1929
1930 O << " bitop3:";
1931 if (Imm <= 10)
1933 else
1934 O << formatHex(static_cast<uint64_t>(Imm));
1935}
1936
1937void AMDGPUInstPrinter::printScaleSel(const MCInst *MI, unsigned OpNo,
1940 uint8_t Imm = MI->getOperand(OpNo).getImm();
1941 if ()
1942 return;
1943
1945}
1946
1947#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1677
static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:547
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
Definition AMDGPUInstPrinter.cpp:1276
static MCRegister getRegForPrinting(MCRegister Reg, const MCRegisterInfo &MRI)
Definition AMDGPUInstPrinter.cpp:340
static MCRegister getRegFromMIA(MCRegister Reg, unsigned OpNo, const MCInstrDesc &Desc, const MCRegisterInfo &MRI, const AMDGPUMCInstrAnalysis &MIA)
Definition AMDGPUInstPrinter.cpp:359
static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:521
Provides AMDGPU specific target descriptions.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
if(auto Err=PB.parsePassPipeline(MPM, Passes)) return wrap(std MPM run * Mod
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1710
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1903
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
Definition AMDGPUInstPrinter.cpp:1614
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1819
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1885
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1646
static void printRegOperand(MCRegister Reg, raw_ostream &O, const MCRegisterInfo &MRI)
Definition AMDGPUInstPrinter.cpp:394
void printRegName(raw_ostream &OS, MCRegister Reg) override
Print the assembler register name.
Definition AMDGPUInstPrinter.cpp:28
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition AMDGPUInstPrinter.cpp:44
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1793
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1634
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Definition AMDGPUInstPrinter.cpp:1842
unsigned getVgprMSBs() const
A helper class to return the specified delimiter string after the first invocation of operator String...
void printExpr(raw_ostream &, const MCExpr &) const
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCInstrAnalysis * MIA
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool isLookupRegClassByHwMode() const
Set if this operand is a value that requires the current hwmode to look up its register class.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
MCRegister getRegister(unsigned i) const
getRegister - Return the specified register in the class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
virtual unsigned getHwMode(enum HwModeType type=HwMode_Default) const
HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current s...
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
StringRef getHwreg(uint64_t Encoding, const MCSubtargetInfo &STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
StringRef getMsgName(uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a msg_id immediate.
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
const char *const IdSymbolic[]
bool isInlineValue(MCRegister Reg)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isVOPCAsmOnly(unsigned Opc)
unsigned getTemporalHintType(const MCInstrDesc TID)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool isGFX12Plus(const MCSubtargetInfo &STI)
const MCRegisterClass * getVGPRPhysRegClass(MCRegister Reg, const MCRegisterInfo &MRI)
bool isGFX940(const MCSubtargetInfo &STI)
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)
LLVM_READNONE bool isLegalDPALU_DPPControl(const MCSubtargetInfo &ST, unsigned DC)
bool isSI(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isGFX12(const MCSubtargetInfo &STI)
MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs, const MCRegisterInfo &MRI)
If Reg is a low VGPR return a corresponding high VGPR with MSBs set.
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > getVGPRLoweringOperandTables(const MCInstrDesc &Desc)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_BF16
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_INT32
Operands with register, 32-bit, or 64-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_IMM_NOINLINE_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_INT32
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
MCRegister mc2PseudoReg(MCRegister Reg)
Convert hardware register Reg to a pseudo register.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
This is an optimization pass for GlobalISel generic memory operations.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
constexpr int popcount(T Value) noexcept
Count the number of set bits in a value.
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
@ Mod
The access may modify the value stored in memory.
To bit_cast(const From &from) noexcept
DWARFExpression::Operation Op
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
static constexpr ValueType Default
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
Instruction set architecture version.