ARMMCTargetDesc.cpp Source File (original) (raw)

34using namespace llvm;

36#define GET_REGINFO_MC_DESC

37#include "ARMGenRegisterInfo.inc"

40 std::string &Info) {

41 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&

42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&

43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&

46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {

47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {

48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {

49 Info = "deprecated since v7, use 'isb'";

50 return true;

51 }

55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {

56 Info = "deprecated since v7, use 'dsb'";

57 return true;

58 }

59 }

62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&

63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {

64 Info = "deprecated since v7, use 'dmb'";

65 return true;

66 }

67 }

68 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&

69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||

70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {

71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "

72 "point instructions";

73 return true;

74 }

75 return false;

76}

79 std::string &Info) {

80 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&

81 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 10) ||

82 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 11))) {

83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "

84 "point instructions";

85 return true;

86 }

87 return false;

88}

91 std::string &Info) {

93 "cannot predicate thumb instructions");

95 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");

96 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {

97 assert(MI.getOperand(OI).isReg() && "expected register");

98 if (MI.getOperand(OI).getReg() == ARM::PC) {

99 Info = "use of PC in the list is deprecated";

100 return true;

101 }

102 }

103 return false;

104}

105

107 std::string &Info) {

109 "cannot predicate thumb instructions");

110

111 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");

112 bool ListContainsPC = false, ListContainsLR = false;

113 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {

114 assert(MI.getOperand(OI).isReg() && "expected register");

115 switch (MI.getOperand(OI).getReg().id()) {

116 default:

117 break;

118 case ARM::LR:

119 ListContainsLR = true;

120 break;

121 case ARM::PC:

122 ListContainsPC = true;

123 break;

124 }

125 }

126

127 if (ListContainsPC && ListContainsLR) {

128 Info = "use of LR and PC simultaneously in the list is deprecated";

129 return true;

130 }

131

132 return false;

133}

134

135#define GET_INSTRINFO_MC_DESC

136#define ENABLE_INSTR_PREDICATE_VERIFIER

137#include "ARMGenInstrInfo.inc"

138

139#define GET_SUBTARGETINFO_MC_DESC

140#include "ARMGenSubtargetInfo.inc"

141

143 std::string ARMArchFeature;

144

146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))

147 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();

148

149 if (TT.isThumb()) {

150 if (!ARMArchFeature.empty())

151 ARMArchFeature += ",";

152 ARMArchFeature += "+thumb-mode,+v4t";

153 }

154

155 if (TT.isOSWindows()) {

156 if (!ARMArchFeature.empty())

157 ARMArchFeature += ",";

158 ARMArchFeature += "+noarm";

159 }

160

161 return ARMArchFeature;

162}

163

166 int PredOpIdx = Desc.findFirstPredOperandIdx();

167 return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;

168}

169

172 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {

174 if (MO.isReg() && MO.getReg() == ARM::CPSR &&

175 Desc.operands()[I].isOptionalDef())

176 return true;

177 }

178 return false;

179}

180

182 uint64_t Addr, int64_t Imm) {

183

184

187

188

189

190

191

192

193 if (InstDesc.getOpcode() == ARM::tBLXi)

194 Addr &= ~0x3;

195

196 return Addr + Imm + Offset;

197}

198

202 if (!FS.empty()) {

203 if (!ArchFS.empty())

204 ArchFS = (Twine(ArchFS) + "," + FS).str();

205 else

206 ArchFS = std::string(FS);

207 }

208

209 return createARMMCSubtargetInfoImpl(TT, CPU, CPU, ArchFS);

210}

211

214 InitARMMCInstrInfo(X);

215 return X;

216}

217

219

220 static const struct {

223 } RegMap[] = {

224 {codeview::RegisterId::ARM_R0, ARM::R0},

225 {codeview::RegisterId::ARM_R1, ARM::R1},

226 {codeview::RegisterId::ARM_R2, ARM::R2},

227 {codeview::RegisterId::ARM_R3, ARM::R3},

228 {codeview::RegisterId::ARM_R4, ARM::R4},

229 {codeview::RegisterId::ARM_R5, ARM::R5},

230 {codeview::RegisterId::ARM_R6, ARM::R6},

231 {codeview::RegisterId::ARM_R7, ARM::R7},

232 {codeview::RegisterId::ARM_R8, ARM::R8},

233 {codeview::RegisterId::ARM_R9, ARM::R9},

234 {codeview::RegisterId::ARM_R10, ARM::R10},

235 {codeview::RegisterId::ARM_R11, ARM::R11},

236 {codeview::RegisterId::ARM_R12, ARM::R12},

237 {codeview::RegisterId::ARM_SP, ARM::SP},

238 {codeview::RegisterId::ARM_LR, ARM::LR},

239 {codeview::RegisterId::ARM_PC, ARM::PC},

240 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},

241 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},

242 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},

243 {codeview::RegisterId::ARM_FS0, ARM::S0},

244 {codeview::RegisterId::ARM_FS1, ARM::S1},

245 {codeview::RegisterId::ARM_FS2, ARM::S2},

246 {codeview::RegisterId::ARM_FS3, ARM::S3},

247 {codeview::RegisterId::ARM_FS4, ARM::S4},

248 {codeview::RegisterId::ARM_FS5, ARM::S5},

249 {codeview::RegisterId::ARM_FS6, ARM::S6},

250 {codeview::RegisterId::ARM_FS7, ARM::S7},

251 {codeview::RegisterId::ARM_FS8, ARM::S8},

252 {codeview::RegisterId::ARM_FS9, ARM::S9},

253 {codeview::RegisterId::ARM_FS10, ARM::S10},

254 {codeview::RegisterId::ARM_FS11, ARM::S11},

255 {codeview::RegisterId::ARM_FS12, ARM::S12},

256 {codeview::RegisterId::ARM_FS13, ARM::S13},

257 {codeview::RegisterId::ARM_FS14, ARM::S14},

258 {codeview::RegisterId::ARM_FS15, ARM::S15},

259 {codeview::RegisterId::ARM_FS16, ARM::S16},

260 {codeview::RegisterId::ARM_FS17, ARM::S17},

261 {codeview::RegisterId::ARM_FS18, ARM::S18},

262 {codeview::RegisterId::ARM_FS19, ARM::S19},

263 {codeview::RegisterId::ARM_FS20, ARM::S20},

264 {codeview::RegisterId::ARM_FS21, ARM::S21},

265 {codeview::RegisterId::ARM_FS22, ARM::S22},

266 {codeview::RegisterId::ARM_FS23, ARM::S23},

267 {codeview::RegisterId::ARM_FS24, ARM::S24},

268 {codeview::RegisterId::ARM_FS25, ARM::S25},

269 {codeview::RegisterId::ARM_FS26, ARM::S26},

270 {codeview::RegisterId::ARM_FS27, ARM::S27},

271 {codeview::RegisterId::ARM_FS28, ARM::S28},

272 {codeview::RegisterId::ARM_FS29, ARM::S29},

273 {codeview::RegisterId::ARM_FS30, ARM::S30},

274 {codeview::RegisterId::ARM_FS31, ARM::S31},

275 {codeview::RegisterId::ARM_ND0, ARM::D0},

276 {codeview::RegisterId::ARM_ND1, ARM::D1},

277 {codeview::RegisterId::ARM_ND2, ARM::D2},

278 {codeview::RegisterId::ARM_ND3, ARM::D3},

279 {codeview::RegisterId::ARM_ND4, ARM::D4},

280 {codeview::RegisterId::ARM_ND5, ARM::D5},

281 {codeview::RegisterId::ARM_ND6, ARM::D6},

282 {codeview::RegisterId::ARM_ND7, ARM::D7},

283 {codeview::RegisterId::ARM_ND8, ARM::D8},

284 {codeview::RegisterId::ARM_ND9, ARM::D9},

285 {codeview::RegisterId::ARM_ND10, ARM::D10},

286 {codeview::RegisterId::ARM_ND11, ARM::D11},

287 {codeview::RegisterId::ARM_ND12, ARM::D12},

288 {codeview::RegisterId::ARM_ND13, ARM::D13},

289 {codeview::RegisterId::ARM_ND14, ARM::D14},

290 {codeview::RegisterId::ARM_ND15, ARM::D15},

291 {codeview::RegisterId::ARM_ND16, ARM::D16},

292 {codeview::RegisterId::ARM_ND17, ARM::D17},

293 {codeview::RegisterId::ARM_ND18, ARM::D18},

294 {codeview::RegisterId::ARM_ND19, ARM::D19},

295 {codeview::RegisterId::ARM_ND20, ARM::D20},

296 {codeview::RegisterId::ARM_ND21, ARM::D21},

297 {codeview::RegisterId::ARM_ND22, ARM::D22},

298 {codeview::RegisterId::ARM_ND23, ARM::D23},

299 {codeview::RegisterId::ARM_ND24, ARM::D24},

300 {codeview::RegisterId::ARM_ND25, ARM::D25},

301 {codeview::RegisterId::ARM_ND26, ARM::D26},

302 {codeview::RegisterId::ARM_ND27, ARM::D27},

303 {codeview::RegisterId::ARM_ND28, ARM::D28},

304 {codeview::RegisterId::ARM_ND29, ARM::D29},

305 {codeview::RegisterId::ARM_ND30, ARM::D30},

306 {codeview::RegisterId::ARM_ND31, ARM::D31},

307 {codeview::RegisterId::ARM_NQ0, ARM::Q0},

308 {codeview::RegisterId::ARM_NQ1, ARM::Q1},

309 {codeview::RegisterId::ARM_NQ2, ARM::Q2},

310 {codeview::RegisterId::ARM_NQ3, ARM::Q3},

311 {codeview::RegisterId::ARM_NQ4, ARM::Q4},

312 {codeview::RegisterId::ARM_NQ5, ARM::Q5},

313 {codeview::RegisterId::ARM_NQ6, ARM::Q6},

314 {codeview::RegisterId::ARM_NQ7, ARM::Q7},

315 {codeview::RegisterId::ARM_NQ8, ARM::Q8},

316 {codeview::RegisterId::ARM_NQ9, ARM::Q9},

317 {codeview::RegisterId::ARM_NQ10, ARM::Q10},

318 {codeview::RegisterId::ARM_NQ11, ARM::Q11},

319 {codeview::RegisterId::ARM_NQ12, ARM::Q12},

320 {codeview::RegisterId::ARM_NQ13, ARM::Q13},

321 {codeview::RegisterId::ARM_NQ14, ARM::Q14},

322 {codeview::RegisterId::ARM_NQ15, ARM::Q15},

323 };

324 for (const auto &I : RegMap)

325 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));

326}

327

330 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);

332 return X;

333}

334

336 const Triple &TheTriple,

345 else

347

348 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);

350

351 return MAI;

352}

353

355 std::unique_ptr &&MAB,

356 std::unique_ptr &&OW,

357 std::unique_ptr &&Emitter) {

359 Ctx, std::move(MAB), std::move(OW), std::move(Emitter),

361 T.isAndroid());

362}

363

366 std::unique_ptr &&OW,

367 std::unique_ptr &&Emitter) {

369 std::move(Emitter), false);

370}

371

373 unsigned SyntaxVariant,

377 if (SyntaxVariant == 0)

379 return nullptr;

380}

381

384 if (TT.isOSBinFormatMachO())

386

388}

389

390namespace {

391

393public:

394 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}

395

397

399 return true;

401 }

402

403 bool isConditionalBranch(const MCInst &Inst) const override {

404

406 return false;

408 }

409

410 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,

411 uint64_t &Target) const override {

413

414

415 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {

420 return true;

421 }

422 }

423 return false;

424 }

425

426 std::optional<uint64_t>

427 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,

428 uint64_t Addr, uint64_t Size) const override;

429

430 std::vector<std::pair<uint64_t, uint64_t>>

431 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,

432 const MCSubtargetInfo &STI) const override;

433};

434

435}

436

437static std::optional<uint64_t>

438

440 unsigned MemOpIndex, uint64_t Addr) {

441 if (MemOpIndex + 1 >= Desc.getNumOperands())

442 return std::nullopt;

443

447 return std::nullopt;

448

449 int32_t OffImm = (int32_t)MO2.getImm();

450

451 if (OffImm == INT32_MIN)

452 OffImm = 0;

453 return Addr + OffImm;

454}

455

456static std::optional<uint64_t>

458 unsigned MemOpIndex, uint64_t Addr) {

459 if (MemOpIndex + 2 >= Desc.getNumOperands())

460 return std::nullopt;

461

466 return std::nullopt;

467

470

472 return Addr - ImmOffs;

473 return Addr + ImmOffs;

474}

475

476static std::optional<uint64_t>

478 unsigned MemOpIndex, uint64_t Addr) {

479 if (MemOpIndex + 1 >= Desc.getNumOperands())

480 return std::nullopt;

481

485 return std::nullopt;

486

489

491 return Addr - ImmOffs * 4;

492 return Addr + ImmOffs * 4;

493}

494

495static std::optional<uint64_t>

497 unsigned MemOpIndex, uint64_t Addr) {

498 if (MemOpIndex + 1 >= Desc.getNumOperands())

499 return std::nullopt;

500

504 return std::nullopt;

505

508

510 return Addr - ImmOffs * 2;

511 return Addr + ImmOffs * 2;

512}

513

514static std::optional<uint64_t>

515

517 unsigned MemOpIndex, uint64_t Addr) {

518 if (MemOpIndex + 1 >= Desc.getNumOperands())

519 return std::nullopt;

520

524 return std::nullopt;

525

526 int32_t OffImm = (int32_t)MO2.getImm();

527 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");

528

529

530 if (OffImm == INT32_MIN)

531 OffImm = 0;

532 return Addr + OffImm;

533}

534

535static std::optional<uint64_t>

536

538 unsigned MemOpIndex, uint64_t Addr) {

540 if (!MO1.isImm())

541 return std::nullopt;

542

543 int32_t OffImm = (int32_t)MO1.getImm();

544

545

546 if (OffImm == INT32_MIN)

547 OffImm = 0;

548 return Addr + OffImm;

549}

550

551static std::optional<uint64_t>

552

554 unsigned MemOpIndex, uint64_t Addr) {

556}

557

558std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(

562

563

564 if ( Desc .mayLoad())

565 return std::nullopt;

566

567

568 uint64_t TSFlags = Desc.TSFlags;

572 return std::nullopt;

573

574

576 while (OpIndex < Desc.getNumOperands() &&

580 return std::nullopt;

581

582

583 Addr &= ~0x3;

584

585

586

588 default:

589 Addr += 8;

590 break;

592 Addr += 4;

593 break;

594

595

597 Addr += STI->hasFeature(ARM::ModeThumb) ? 4 : 8;

598 break;

599 }

600

601

604 default:

605 return std::nullopt;

620 }

621}

622

623template <typename T, size_t N>

626 for (size_t I = 0; I < N; ++I) {

628 if (Val != Insns[I])

629 return false;

630 }

631 return true;

632}

633

634std::vector<std::pair<uint64_t, uint64_t>>

635ARMMCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,

636 ArrayRef<uint8_t> PltContents,

637 const MCSubtargetInfo &STI) const {

639 ? endianness::little

640 : endianness::big;

642 STI.checkFeatures("+big-endian-instructions") ? endianness::big

643 : endianness::little;

644

645

646 std::vector<std::pair<uint64_t, uint64_t>> Result;

648 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;

649 Byte += 16) {

650

651

652

653

654

655

656

657

658 uint32_t MovwPart1 =

660 if ((MovwPart1 & 0xffb0) != 0xf200)

661 continue;

662

664 PltContents.data() + Byte + 2, InstrEndianness);

665 if ((MovwPart2 & 0x8f00) != 0xc00)

666 continue;

667

668 uint64_t OffsetLower = (MovwPart2 & 0xff) + ((MovwPart2 & 0x7000) >> 4) +

669 ((MovwPart1 & 0x400) << 1) +

670 ((MovwPart1 & 0xf) << 12);

671

673 PltContents.data() + Byte + 4, InstrEndianness);

674 if ((MovtPart1 & 0xfbf0) != 0xf2c0)

675 continue;

676

678 PltContents.data() + Byte + 6, InstrEndianness);

679 if ((MovtPart2 & 0x8f00) != 0xc00)

680 continue;

681

682 uint64_t OffsetHigher =

683 ((MovtPart2 & 0xff) << 16) + ((MovtPart2 & 0x7000) << 12) +

684 ((MovtPart1 & 0x400) << 17) + ((MovtPart1 & 0xf) << 28);

685

686 const uint16_t Insns[] = {

687 0x44fc,

688 0xf8dc, 0xf000,

689 0xe7fc,

690 };

691

693 InstrEndianness))

694 continue;

695

696

697 uint64_t Offset = (PltSectionVA + Byte + 12) + OffsetLower + OffsetHigher;

698 Result.emplace_back(PltSectionVA + Byte, Offset);

699 }

700 } else {

701 const uint32_t LongEntryInsns[] = {

702 0xe59fc004,

703 0xe08cc00f,

704 0xe59cf000,

705 };

706

707 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 12 < End;

708 Byte += 4) {

709

711 InstrEndianness)) {

712

713

714

715

716

717

718

719 uint64_t Offset = (PltSectionVA + Byte + 12) +

721 PltContents.data() + Byte + 12, DataEndianness);

722 Result.emplace_back(PltSectionVA + Byte, Offset);

724 } else {

725

726

727

728

729

730

731 uint32_t Add1 =

733 if ((Add1 & 0xe28fc600) != 0xe28fc600)

734 continue;

736 InstrEndianness);

737 if ((Add2 & 0xe28cca00) != 0xe28cca00)

738 continue;

740 InstrEndianness);

741 if ((Ldr & 0xe5bcf000) != 0xe5bcf000)

742 continue;

743

744

745 uint64_t Offset = (PltSectionVA + Byte + 8) + ((Add1 & 0xff) << 20) +

746 ((Add2 & 0xff) << 12) + (Ldr & 0xfff);

747 Result.emplace_back(PltSectionVA + Byte, Offset);

749 }

750 }

751 }

753}

754

756 return new ARMMCInstrAnalysis(Info);

757}

758

760

761

762 if (Coproc >= 8)

763 return false;

764 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];

765}

766

767

771

773

774

776

777

779

780

783

787

788

791

792

794

795

797

798

800

801

803 }

804

805

809

813 }

817 }

818}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isUnconditionalBranch(Instruction *Term)

static std::optional< uint64_t > evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:439

static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)

Definition ARMMCTargetDesc.cpp:90

static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)

Definition ARMMCTargetDesc.cpp:106

static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:553

static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)

Definition ARMMCTargetDesc.cpp:365

static std::optional< uint64_t > evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:457

static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)

Definition ARMMCTargetDesc.cpp:755

static std::optional< uint64_t > evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:496

static bool instructionsMatch(const T(&Insns)[N], const uint8_t *Buf, llvm::endianness E)

Definition ARMMCTargetDesc.cpp:624

static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:537

static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)

Definition ARMMCTargetDesc.cpp:39

static std::optional< uint64_t > evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:477

static MCInstrInfo * createARMMCInstrInfo()

Definition ARMMCTargetDesc.cpp:212

static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)

Definition ARMMCTargetDesc.cpp:382

static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition ARMMCTargetDesc.cpp:372

static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)

Definition ARMMCTargetDesc.cpp:328

static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)

Definition ARMMCTargetDesc.cpp:78

static std::optional< uint64_t > evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)

Definition ARMMCTargetDesc.cpp:516

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()

Definition ARMMCTargetDesc.cpp:768

static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)

Definition ARMMCTargetDesc.cpp:335

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

Analysis containing CSE Info

#define LLVM_EXTERNAL_VISIBILITY

dxil DXContainer Global Emitter

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

size_t size() const

size - Get the array size.

This class is intended to be used as a base class for asm properties and features specific to the tar...

void addInitialFrameState(const MCCFIInstruction &Inst)

static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.

Context object for machine code objects.

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

const MCOperand & getOperand(unsigned i) const

virtual bool isUnconditionalBranch(const MCInst &Inst) const

virtual bool isConditionalBranch(const MCInst &Inst) const

Describe properties that are true of each instruction in the target description file.

unsigned getOpcode() const

Return the opcode number for this descriptor.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Create MCExprs from relocations found in an object file.

Streaming machine code generation interface.

Generic base class for all target subtargets.

bool checkFeatures(StringRef FS) const

Check whether the subtarget features are enabled/disabled as per the provided string,...

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

const FeatureBitset & getFeatureBits() const

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

bool isOSBinFormatMachO() const

Tests whether the environment is MachO.

LLVM_ABI bool isLittleEndian() const

Tests whether the target triple is little endian.

bool isOSWindows() const

Tests whether the OS is Windows.

bool isOSDarwin() const

Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, DriverKit, XROS, or bridgeOS).

bool isWindowsMSVCEnvironment() const

Checks if the environment could be MSVC.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

IndexMode

ARM Index Modes.

unsigned char getAM3Offset(unsigned AM3Opc)

unsigned char getAM5FP16Offset(unsigned AM5Opc)

AddrOpc getAM5Op(unsigned AM5Opc)

AddrOpc getAM5FP16Op(unsigned AM5Opc)

unsigned char getAM5Offset(unsigned AM5Opc)

AddrOpc getAM3Op(unsigned AM3Opc)

MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Create a ARM MCSubtargetInfo instance.

Definition ARMMCTargetDesc.cpp:199

std::string ParseARMTriple(const Triple &TT, StringRef CPU)

Definition ARMMCTargetDesc.cpp:142

bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)

Definition ARMMCTargetDesc.cpp:170

void initLLVMToCVRegMapping(MCRegisterInfo *MRI)

Definition ARMMCTargetDesc.cpp:218

bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)

Definition ARMMCTargetDesc.cpp:164

uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)

Definition ARMMCTargetDesc.cpp:181

LLVM_ABI StringRef getArchName(ArchKind AK)

LLVM_ABI ArchKind parseArch(StringRef Arch)

bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)

Definition ARMMCTargetDesc.cpp:759

@ D16

Only 16 D registers.

uint32_t read32(const void *P, endianness E)

value_type read(const void *memory, endianness endian)

Read a value of a particular endianness from memory.

uint16_t read16(const void *P, endianness E)

This is an optimization pass for GlobalISel generic memory operations.

MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool IsThumb, bool IsAndroid)

Target & getTheThumbBETarget()

MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

LLVM_ABI MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE)

MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)

Construct ARM Mach-O relocation info.

LLVM_ABI MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool DWARFMustBeAtTheEnd, bool LabelSections=false)

LLVM_ABI MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

Target & getTheARMLETarget()

MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)

MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)

MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

Target & getTheARMBETarget()

Target & getTheThumbLETarget()

RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)

RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.

static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)

static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)

static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)

RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.