HexagonVLIWPacketizer.cpp Source File (original) (raw)

50#include

51#include

52#include

54using namespace llvm;

56#define DEBUG_TYPE "packets"

60 cl::desc("Disable Hexagon packetizer pass"));

64 cl::desc("Allow slot1 store and slot0 load"));

68 cl::desc("Allow non-solo packetization of volatile memory references"));

72 cl::desc("Generate all instruction with TC"));

76 cl::desc("Disable vector double new-value-stores"));

80namespace {

83 public:

84 static char ID;

86 HexagonPacketizer(bool Min = false)

89 void getAnalysisUsage(AnalysisUsage &AU) const override {

92 AU.addRequired();

93 AU.addRequired();

94 AU.addRequired();

95 AU.addPreserved();

96 AU.addPreserved();

98 }

100 StringRef getPassName() const override { return "Hexagon Packetizer"; }

101 bool runOnMachineFunction(MachineFunction &Fn) override;

102

103 MachineFunctionProperties getRequiredProperties() const override {

104 return MachineFunctionProperties().setNoVRegs();

105 }

106

107 private:

108 const HexagonInstrInfo *HII = nullptr;

109 const HexagonRegisterInfo *HRI = nullptr;

110 const bool Minimal = false;

111 };

112

113}

114

115char HexagonPacketizer::ID = 0;

116

118 "Hexagon Packetizer", false, false)

125

130 Minimal(Minimal) {

133

134 addMutation(std::make_uniqueHexagonSubtarget::UsrOverflowMutation());

135 addMutation(std::make_uniqueHexagonSubtarget::HVXMemLatencyMutation());

136 addMutation(std::make_uniqueHexagonSubtarget::BankConflictMutation());

137}

138

139

143 for (auto &MO : FirstI.operands()) {

144 if (!MO.isReg() || !MO.isDef())

145 continue;

148 return true;

149 }

150 return false;

151}

152

153

157 if (Before)

159 else

160 InsertPt = std::next(BundleIt).getInstrIterator();

161

163

164

165 assert(MI.isBundledWithPred());

166 if (MI.isBundledWithSucc()) {

169 } else {

170

171

172

173 MI.unbundleFromPred();

174 }

175 B.splice(InsertPt, &B, MI.getIterator());

176

177

180 unsigned Size = 0;

181 for (++I; I != E && I->isBundledWithPred(); ++I)

183

184

185

186 if (Size > 1)

187 return BundleIt;

188

189

191 MachineInstr &SingleI = *BundleIt->getNextNode();

194 BundleIt->eraseFromParent();

195 return NextIt;

196}

197

198bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {

199

201

202 auto &HST = MF.getSubtarget();

203 HII = HST.getInstrInfo();

204 HRI = HST.getRegisterInfo();

205 auto &MLI = getAnalysis().getLI();

206 auto *AA = &getAnalysis().getAAResults();

207 auto *MBPI =

208 &getAnalysis().getMBPI();

209

211 HII->genAllInsnTimingClasses(MF);

212

213

214 bool MinOnly = Minimal || DisablePacketizer || !HST.usePackets() ||

216 HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI, MinOnly);

217

218

219 assert(Packetizer.getResourceTracker() && "Empty DFA table!");

220

221

222

223

224

225

226

227

228

229 for (MachineBasicBlock &MB : MF) {

231 if (MI.isKill())

232 MB.erase(&MI);

233 }

234

235

236 if (HST.isTinyCoreWithDuplex())

237 HII->translateInstrsForDup(MF, true);

238

239

240 for (auto &MB : MF) {

241 auto Begin = MB.begin(), End = MB.end();

242 while (Begin != End) {

243

244

246 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))

247 ++RB;

248

249

251 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))

252 ++RE;

253

254 if (RE != End)

255 ++RE;

256

257 if (RB != End)

258 Packetizer.PacketizeMIs(&MB, RB, RE);

259

260 Begin = RE;

261 }

262 }

263

264

265 if (HST.isTinyCoreWithDuplex())

266 HII->translateInstrsForDup(MF, false);

267

268 Packetizer.unpacketizeSoloInstrs(MF);

269 return true;

270}

271

272

273

278

282

283

284

286 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());

287 bool Avail = ResourceTracker->canReserveResources(*ExtMI);

288 if (Reserve && Avail)

290 MF.deleteMachineInstr(ExtMI);

291 return Avail;

292}

293

295 SDep::Kind DepType, unsigned DepReg) {

296

297 if (DepReg == HRI->getRARegister())

298 return true;

299

300 if (HII->isDeallocRet(MI))

301 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())

302 return true;

303

304

305

306

307

308

311 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())

312 return true;

313 }

314

315 return false;

316}

317

322

324 return MI.getOpcode() == Hexagon::J2_jump;

325}

326

328 switch (MI.getOpcode()) {

329 case Hexagon::Y2_barrier:

330 return true;

331 }

332 return false;

333}

334

336 return MI.getDesc().isTerminator() || MI.getDesc().isCall();

337}

338

339

343 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)

344 if (MI.modifiesRegister(*CSR, TRI))

345 return true;

346 return false;

347}

348

349

350

353

354

355 if (NewRC == &Hexagon::PredRegsRegClass) {

356 if (HII->isHVXVec(MI) && MI.mayStore())

357 return false;

358 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;

359 }

360

361 return HII->mayBeNewStore(MI);

362}

363

364

365

366

371 int CurOpcode = HII->getDotCurOp(MI);

372 MI.setDesc(HII->get(CurOpcode));

373 return true;

374}

375

379 LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););

380 if (HII->isDotCurInst(*BI)) {

381 MI = BI;

382 continue;

383 }

384 if (MI) {

385 for (auto &MO : BI->operands())

386 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())

387 return;

388 }

389 }

390 if ()

391 return;

392

393 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));

395}

396

397

401 if (!HII->isHVXVec(MI))

402 return false;

403 if (!HII->isHVXVec(*MII))

404 return false;

405

406

407 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))

408 return false;

409

410 if (!HII->mayBeCurLoad(MI))

411 return false;

412

413

415 return false;

416

417

418 LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();

419 dbgs() << "in packet\n";);

422 dbgs() << "Checking CUR against ";

423 MJ.dump();

424 });

425 Register DestReg = MI.getOperand(0).getReg();

426 bool FoundMatch = false;

427 for (auto &MO : MJ.operands())

428 if (MO.isReg() && MO.getReg() == DestReg)

429 FoundMatch = true;

430 if (!FoundMatch)

431 return false;

432

433

434

437 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))

438 return false;

439 }

440

442

443 return true;

444}

445

446

447

448

453 int NewOpcode;

454 if (RC == &Hexagon::PredRegsRegClass)

455 NewOpcode = HII->getDotNewPredOp(MI, MBPI);

456 else

457 NewOpcode = HII->getDotNewOp(MI);

458 MI.setDesc(HII->get(NewOpcode));

459 return true;

460}

461

463 int NewOpcode = HII->getDotOldOp(MI);

464 MI.setDesc(HII->get(NewOpcode));

465 return true;

466}

467

469 unsigned Opc = MI.getOpcode();

470 switch (Opc) {

471 case Hexagon::S2_storerd_io:

472 case Hexagon::S2_storeri_io:

473 case Hexagon::S2_storerh_io:

474 case Hexagon::S2_storerb_io:

475 break;

476 default:

478 }

479 unsigned FrameSize = MF.getFrameInfo().getStackSize();

482 if (HII->isValidOffset(Opc, NewOff, HRI)) {

483 Off.setImm(NewOff);

484 return true;

485 }

486 return false;

487}

488

490 unsigned Opc = MI.getOpcode();

491 switch (Opc) {

492 case Hexagon::S2_storerd_io:

493 case Hexagon::S2_storeri_io:

494 case Hexagon::S2_storerh_io:

495 case Hexagon::S2_storerb_io:

496 break;

497 default:

499 }

500 unsigned FrameSize = MF.getFrameInfo().getStackSize();

503}

504

505

506

511

512 unsigned BPI, OPI;

513 if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))

514 return false;

515 unsigned BPJ, OPJ;

516 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))

517 return false;

518 Register Reg = MI.getOperand(BPI).getReg();

520 return false;

521

522

523

524 for (const auto &PI : SUI->Preds)

526 (PI.getKind() != SDep::Data || PI.getReg() != Reg))

527 return false;

528 int Incr;

529 if (!HII->getIncrementValue(MJ, Incr))

530 return false;

531

532 int64_t Offset = MI.getOperand(OPI).getImm();

533 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))

534 return false;

535

536 MI.getOperand(OPI).setImm(Offset + Incr);

537 ChangedOffset = Offset;

538 return true;

539}

540

541

542

544 unsigned BP, OP;

545 if (!HII->getBaseAndOffsetPosition(MI, BP, OP))

546 llvm_unreachable("Unable to find base and offset operands.");

547 MI.getOperand(OP).setImm(ChangedOffset);

548}

549

555

556

557

566

570#ifndef NDEBUG

571

572

573

575 for (auto &MO : MI.operands())

576 if (MO.isReg() && MO.isDef())

577 DefRegsSet.insert(MO.getReg());

578

579 for (auto &MO : MI.operands())

580 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))

581 return MO;

582#else

583 if (MI.mayLoad()) {

585

586 assert(Op1.isReg() && "Post increment operand has be to a register.");

587 return Op1;

588 }

589 if (MI.getDesc().mayStore()) {

591

592 assert(Op0.isReg() && "Post increment operand has be to a register.");

593 return Op0;

594 }

595#endif

596

597 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");

598}

599

600

602

603 return MI.getOperand(MI.getNumOperands()-1);

604}

605

607 unsigned Opc = MI.getOpcode();

608 switch (Opc) {

609 case Hexagon::L4_loadrd_ap:

610 case Hexagon::L4_loadrb_ap:

611 case Hexagon::L4_loadrh_ap:

612 case Hexagon::L4_loadrub_ap:

613 case Hexagon::L4_loadruh_ap:

614 case Hexagon::L4_loadri_ap:

615 return true;

616 }

617 return false;

618}

619

622 return MI.getOperand(1);

623}

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

643 const MachineInstr &PacketMI, unsigned DepReg) {

644

645 if (!HII->mayBeNewStore(MI))

646 return false;

647

648

650 if (Val.isReg() && Val.getReg() != DepReg)

651 return false;

652

654

655

657

658 if (PacketRC == &Hexagon::DoubleRegsRegClass)

659 return false;

660

661

662

666 return false;

667 }

668

669

670

671 if (HII->isPostIncrement(MI) &&

673 return false;

674 }

675

676 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&

678

679

680

681

682

683 return false;

684 }

685

687 return false;

688

689

690

691 if (HII->isPredicated(PacketMI)) {

692 if (!HII->isPredicated(MI))

693 return false;

694

695

696

697 unsigned predRegNumSrc = 0;

698 unsigned predRegNumDst = 0;

700

701

702 for (auto &MO : PacketMI.operands()) {

703 if (!MO.isReg())

704 continue;

705 predRegNumSrc = MO.getReg();

706 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);

707 if (predRegClass == &Hexagon::PredRegsRegClass)

708 break;

709 }

710 assert((predRegClass == &Hexagon::PredRegsRegClass) &&

711 "predicate register not found in a predicated PacketMI instruction");

712

713

714 for (auto &MO : MI.operands()) {

715 if (!MO.isReg())

716 continue;

717 predRegNumDst = MO.getReg();

718 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);

719 if (predRegClass == &Hexagon::PredRegsRegClass)

720 break;

721 }

722 assert((predRegClass == &Hexagon::PredRegsRegClass) &&

723 "predicate register not found in a predicated MI instruction");

724

725

726

727

728

729

730

731

732

733 if (predRegNumDst != predRegNumSrc ||

734 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||

736 return false;

737 }

738

739

740

741

742

743

744

745

746

747 unsigned StartCheck = 0;

748

752

753

754

755

756 if (&TempMI != &PacketMI && !StartCheck)

757 continue;

758

759 StartCheck = 1;

760 if (&TempMI == &PacketMI)

761 continue;

762

763 for (auto &MO : MI.operands())

765 return false;

766 }

767

768

769

770

771

772

773

774 if (!HII->isPostIncrement(MI)) {

775 for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {

778 return false;

779 }

780 }

781

782

783

784

785

786 for (auto &MO : PacketMI.operands()) {

787 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))

788 return false;

789 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())

790 continue;

792 if (R == DepReg || HRI->isSuperRegister(DepReg, R))

793 return false;

794 }

795

796

797

798

799

800

801 for (auto &MO : MI.operands()) {

802 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)

803 return false;

804 }

805

806

807 return true;

808}

809

810

812 const SUnit *PacketSU, unsigned DepReg,

814 if (!HII->mayBeNewStore(MI))

815 return false;

816

817

820 return true;

821

822

823

824 return false;

825}

826

828 unsigned DepReg) {

829 for (auto &MO : I.operands()) {

830 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))

831 return true;

832 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())

833 continue;

834 if (CheckDef == MO.isDef())

835 return true;

836 }

837 return false;

838}

839

840

844

845 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))

846 return false;

847

849 return false;

850

852

853

855 return false;

856

857

858

860 return false;

861

862

863

866 return false;

867

871 return false;

872

873

874 if (RC == &Hexagon::PredRegsRegClass)

875 return HII->predCanBeUsedAsDotNew(PI, DepReg);

876

877 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))

878 return false;

879

880

881

882 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) :

883 HII->getDotNewPredOp(MI, MBPI);

886 bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);

887 MF.deleteMachineInstr(NewMI);

888 if (!ResourcesAvailable)

889 return false;

890

891

893 return false;

894

895 return true;

896}

897

898

899

900

901

902

903

904

905

906

907

908

909

910

912 unsigned DepReg) {

914

916

917 if (!HII->isPredicated(*I))

918 continue;

919

920

922

923

924

925

926 if (PacketSU->isSucc(PacketSUDep)) {

927 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {

928 auto &Dep = PacketSU->Succs[i];

929 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&

930 Dep.getReg() == DepReg)

931 return true;

932 }

933 }

934 }

935

936 return false;

937}

938

939

942

943

945

946 for (auto &Op : MI.operands()) {

947 if (Op.isReg() && Op.getReg() && Op.isUse() &&

948 Hexagon::PredRegsRegClass.contains(Op.getReg()))

949 return Op.getReg();

950 }

951

953 return 0;

954}

955

956

957

960

961

964 return false;

965

966

968

969

970

971

972

973

974

975

976

977

978

979

980

981

982

983

984

986

988

989

990 if (PacketSU->isSucc(SU)) {

991 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {

992 auto Dep = PacketSU->Succs[i];

993

994

995

996

997 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&

998 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {

999

1000

1001

1002

1003

1005 return false;

1006 }

1007 }

1008 }

1009 }

1010

1011

1012

1013

1014

1017 return PReg1 == PReg2 &&

1018 Hexagon::PredRegsRegClass.contains(PReg1) &&

1019 Hexagon::PredRegsRegClass.contains(PReg2) &&

1021 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);

1022}

1023

1024

1026 Dependence = false;

1027 PromotedToDotNew = false;

1028 GlueToNewValueJump = false;

1029 GlueAllocframeStore = false;

1030 FoundSequentialDependence = false;

1032}

1033

1034

1037 if (MI.isDebugInstr())

1038 return true;

1039

1040 if (MI.isCFIInstruction())

1041 return false;

1042

1043

1044 if (MI.isInlineAsm())

1045 return false;

1046

1047 if (MI.isImplicitDef())

1048 return false;

1049

1050

1051

1054 return !IS->getUnits();

1055}

1056

1058

1059 if (MI.isBundle())

1060 return true;

1061

1062 if (MI.isEHLabel() || MI.isCFIInstruction())

1063 return true;

1064

1065

1066

1067

1068

1069

1071 return true;

1072

1074 return true;

1075

1076 if (HII->isSolo(MI))

1077 return true;

1078

1079 if (MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER ||

1080 MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT ||

1081 MI.getOpcode() == Hexagon::PATCHABLE_TAIL_CALL)

1082 return true;

1083

1084 if (MI.getOpcode() == Hexagon::A2_nop)

1085 return true;

1086

1087 return false;

1088}

1089

1090

1091

1092

1093

1094

1095

1096

1102 return true;

1103

1104

1105

1107 return true;

1108

1109

1110

1111

1112

1113 if (MI.isInlineAsm())

1116

1117

1119 return true;

1120

1121 switch (MI.getOpcode()) {

1122 case Hexagon::S2_storew_locked:

1123 case Hexagon::S4_stored_locked:

1124 case Hexagon::L2_loadw_locked:

1125 case Hexagon::L4_loadd_locked:

1126 case Hexagon::Y2_dccleana:

1127 case Hexagon::Y2_dccleaninva:

1128 case Hexagon::Y2_dcinva:

1129 case Hexagon::Y2_dczeroa:

1130 case Hexagon::Y4_l2fetch:

1131 case Hexagon::Y5_l2fetch: {

1132

1133

1134

1135 unsigned TJ = HII.getType(MJ);

1139 return true;

1140 break;

1141 }

1142 default:

1143 break;

1144 }

1145

1146

1147

1148 return false;

1149}

1150

1151

1156

1158 for (auto &B : MF) {

1161 if (MI.isBundle())

1162 BundleIt = MI.getIterator();

1163 if (.isInsideBundle())

1164 continue;

1165

1166

1167

1168

1169

1170

1171

1172 bool InsertBeforeBundle;

1173 if (MI.isInlineAsm())

1175 else if (MI.isDebugInstr())

1176 InsertBeforeBundle = true;

1177 else

1178 continue;

1179

1180 BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);

1181 }

1182 }

1183}

1184

1185

1187 unsigned Opc = MI.getOpcode();

1188 switch (Opc) {

1189 case Hexagon::Y2_barrier:

1190 case Hexagon::Y2_dcfetchbo:

1191 case Hexagon::Y4_l2fetch:

1192 case Hexagon::Y5_l2fetch:

1193 return true;

1194 }

1195 return false;

1196}

1197

1200

1201

1202

1203 if (I.isCall() || J.isCall())

1204 return false;

1205 if (HII->isPredicated(I) || HII->isPredicated(J))

1206 return false;

1207

1208 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);

1209 for (auto &MO : I.operands()) {

1210 if (!MO.isReg() || !MO.isDef() || !MO.isDead())

1211 continue;

1212 DeadDefs[MO.getReg()] = true;

1213 }

1214

1215 for (auto &MO : J.operands()) {

1216 if (!MO.isReg() || !MO.isDef() || !MO.isDead())

1217 continue;

1219 if (R != Hexagon::USR_OVF && DeadDefs[R])

1220 return true;

1221 }

1222 return false;

1223}

1224

1227

1228

1229 if ((HII->isSaveCalleeSavedRegsCall(I) &&

1231 (HII->isSaveCalleeSavedRegsCall(J) &&

1233 return true;

1234

1235

1237 return true;

1238

1239

1240

1241

1242 auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {

1243 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))

1244 return true;

1245 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))

1246 return true;

1247 return false;

1248 };

1249

1250 if (HII->isLoopN(I) && isBadForLoopN(J))

1251 return true;

1252 if (HII->isLoopN(J) && isBadForLoopN(I))

1253 return true;

1254

1255

1256

1257 return HII->isDeallocRet(I) &&

1259}

1260

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1275 if (!OpJ.isRegMask())

1276 continue;

1277 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");

1279 if (OpI.isReg()) {

1280 if (OpJ.clobbersPhysReg(OpI.getReg()))

1281 return true;

1282 } else if (OpI.isRegMask()) {

1283

1284 return true;

1285 }

1286 }

1287 }

1288 return false;

1289}

1290

1294 bool StoreI = I.mayStore(), StoreJ = J.mayStore();

1295 if ((SysI && StoreJ) || (SysJ && StoreI))

1296 return true;

1297

1298 if (StoreI && StoreJ) {

1299 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))

1300 return true;

1301 } else {

1302

1303

1304 bool MopStI = HII->isMemOp(I) || StoreI;

1305 bool MopStJ = HII->isMemOp(J) || StoreJ;

1306 if (MopStI && MopStJ)

1307 return true;

1308 }

1309

1310 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));

1311}

1312

1313

1314

1315

1320

1321

1323 IgnoreDepMIs.clear();

1324

1326

1327

1329

1331 return false;

1332

1334 if (Dependence)

1335 return false;

1336

1337

1338

1339

1340

1342 if (Dependence)

1343 return false;

1344

1345

1346

1347

1349 if (Dependence)

1350 return false;

1351

1352

1354 ++NextMII;

1355 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {

1357

1358 bool secondRegMatch = false;

1361

1362 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())

1363 secondRegMatch = true;

1364

1366

1367 if (PI->isCall()) {

1368 Dependence = true;

1369 break;

1370 }

1371

1372

1373

1374

1375

1376

1377

1378

1379 if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||

1380 HII->isLoopN(*PI)) {

1381 Dependence = true;

1382 break;

1383 }

1384

1385 const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;

1386 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {

1387 Dependence = true;

1388 break;

1389 }

1390 }

1391

1392 GlueToNewValueJump = true;

1393 if (Dependence)

1394 return false;

1395 }

1396

1397

1398 if (!SUJ->isSucc(SUI))

1399 return true;

1400

1401 for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {

1402 if (FoundSequentialDependence)

1403 break;

1404

1405 if (SUJ->Succs[i].getSUnit() != SUI)

1406 continue;

1407

1409

1410

1411

1412

1413

1414

1415

1416

1417

1418

1419

1420

1421

1422

1423

1424 unsigned DepReg = 0;

1427 DepReg = SUJ->Succs[i].getReg();

1428 RC = HRI->getMinimalPhysRegClass(DepReg);

1429 }

1430

1431 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {

1433 continue;

1435 continue;

1436 }

1437

1441 continue;

1442 }

1443

1444

1445 if (DepType == SDep::Data && HII->isDotCurInst(J)) {

1446 if (HII->isHVXVec(I))

1447 continue;

1448 }

1449

1450

1454 PromotedToDotNew = true;

1456 FoundSequentialDependence = true;

1457 continue;

1458 }

1459 }

1460 if (HII->isNewValueJump(I))

1461 continue;

1462 }

1463

1464

1465

1466 if (HII->isPredicated(I) && HII->isPredicated(J) &&

1468

1469

1470

1471

1472

1473

1474

1475

1476

1477

1478

1479

1480 auto Itr = find(IgnoreDepMIs, &J);

1481 if (Itr != IgnoreDepMIs.end()) {

1482 Dependence = true;

1483 return false;

1484 }

1485 IgnoreDepMIs.push_back(&I);

1486 continue;

1487 }

1488

1489

1490

1493 continue;

1494

1495

1496

1497 if (I.isConditionalBranch() && DepType != SDep::Data &&

1499 continue;

1500

1502 FoundSequentialDependence = true;

1503 break;

1504 }

1505

1506

1507

1508

1509

1510

1511

1515 if (OrdRefs) {

1516 FoundSequentialDependence = true;

1517 break;

1518 }

1519 }

1520

1522 bool LoadI = I.mayLoad(), StoreI = I.mayStore();

1523 bool NVStoreJ = HII->isNewValueStore(J);

1524 bool NVStoreI = HII->isNewValueStore(I);

1525 bool IsVecJ = HII->isHVXVec(J);

1526 bool IsVecI = HII->isHVXVec(I);

1527

1528

1529

1530 if (LoadJ && LoadI && HII->isPureSlot0(J)) {

1531 FoundSequentialDependence = true;

1532 break;

1533 }

1534

1536 ((LoadJ && StoreI && !NVStoreI) ||

1537 (StoreJ && LoadI && !NVStoreJ)) &&

1538 (J.getOpcode() != Hexagon::S2_allocframe &&

1539 I.getOpcode() != Hexagon::S2_allocframe) &&

1540 (J.getOpcode() != Hexagon::L2_deallocframe &&

1541 I.getOpcode() != Hexagon::L2_deallocframe) &&

1542 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))

1544 else

1545 if (StoreJ && LoadI && alias(J, I)) {

1546 FoundSequentialDependence = true;

1547 break;

1548 }

1549

1550 if (!StoreJ)

1551 if (!LoadJ || (!LoadI && !StoreI)) {

1552

1553

1554 FoundSequentialDependence = true;

1555 break;

1556 }

1557

1558

1559

1560

1561 continue;

1562 }

1563

1564

1565

1566

1567

1569 unsigned Opc = I.getOpcode();

1570 switch (Opc) {

1571 case Hexagon::S2_storerd_io:

1572 case Hexagon::S2_storeri_io:

1573 case Hexagon::S2_storerh_io:

1574 case Hexagon::S2_storerb_io:

1575 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {

1576

1577

1578

1579

1581 if (GlueAllocframeStore)

1582 continue;

1583 }

1584 break;

1585 default:

1586 break;

1587 }

1588 }

1589

1590

1591

1592

1593

1594

1595

1597

1598

1599

1601 if (Op.isReg() && Op.isDef()) {

1604 continue;

1605 } else if (.isRegMask()) {

1606

1607 continue;

1608 }

1609 FoundSequentialDependence = true;

1610 break;

1611 }

1612 }

1613

1614

1615

1616

1617

1618

1619

1621 FoundSequentialDependence = true;

1622 break;

1623 }

1624 }

1625

1626 if (FoundSequentialDependence) {

1627 Dependence = true;

1628 return false;

1629 }

1630

1631 return true;

1632}

1633

1638

1640

1641 if (Coexist && !Dependence)

1642 return true;

1643

1644

1645

1646 if (PromotedToDotNew)

1648

1650

1651

1652

1653 if (GlueAllocframeStore) {

1655 GlueAllocframeStore = false;

1656 }

1657

1660

1661 if (GlueToNewValueJump) {

1662

1663

1664 GlueToNewValueJump = false;

1665 return false;

1666 }

1667

1668 if (!Coexist)

1669 return false;

1670

1672 FoundSequentialDependence = false;

1673 Dependence = false;

1674 return true;

1675 }

1676

1677 return false;

1678}

1679

1680

1682 bool FoundLoad = false;

1683 bool FoundStore = false;

1684

1686 unsigned Opc = MJ->getOpcode();

1687 if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)

1688 continue;

1689 if (HII->isMemOp(*MJ))

1690 continue;

1691 if (MJ->mayLoad())

1692 FoundLoad = true;

1693 if (MJ->mayStore() && !HII->isNewValueStore(*MJ))

1694 FoundStore = true;

1695 }

1696 return FoundLoad && FoundStore;

1697}

1698

1699

1704

1706 PacketStalls = false;

1707 PacketStallCycles = 0;

1708 }

1710 PacketStallCycles = std::max(PacketStallCycles, calcStall(MI));

1711

1712 if (MI.isImplicitDef()) {

1713

1714

1716 return MII;

1717 }

1719

1720 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);

1721 bool Good = true;

1722

1723 if (GlueToNewValueJump) {

1725

1726

1727

1728

1730 if (ExtMI)

1732

1733 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);

1734 if (Good) {

1737 else

1738 Good = false;

1739 }

1740 if (Good && ExtNvjMI)

1742

1743 if (!Good) {

1747 if (ExtMI) {

1750 }

1753 if (ExtNvjMI) {

1756 }

1757 }

1760 return MII;

1761 }

1762

1766 if (PromotedToDotNew)

1768 if (GlueAllocframeStore) {

1770 GlueAllocframeStore = false;

1771 }

1774 }

1775

1777 return MII;

1778}

1779

1782

1785 dbgs() << "Finalizing packet:\n";

1786 unsigned Idx = 0;

1790 }

1791 }

1792 });

1793

1797 LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");

1798 }

1800

1801 OldPacketMIs.clear();

1804 for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))

1805 OldPacketMIs.push_back(&I);

1806 }

1808

1809 if (OldPacketMIs.size() > 1) {

1813 auto BundleMII = std::prev(FirstMI);

1814 if (memShufDisabled)

1815 HII->setBundleNoShuf(BundleMII);

1816

1818 }

1819

1820 PacketHasDuplex = false;

1821 PacketHasSLOT0OnlyInsn = false;

1824}

1825

1827 if (Minimal)

1828 return false;

1829

1831 return false;

1832

1833

1834

1835 auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();

1836

1837

1838

1839

1840

1841

1842

1843 if (HST.isTinyCoreWithDuplex() && CurrentPacketMIs.size() > 0 &&

1844 !PacketHasDuplex) {

1845

1847 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);

1848

1849 int Opcode = HII->getDuplexOpcode(MI, false);

1850 if (Opcode >= 0) {

1851

1853 if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) {

1854 PacketHasDuplex = true;

1855 return true;

1856 }

1857 }

1858

1859

1861 MIRef.setDesc(HII->get(Opcode));

1863 }

1864 }

1865

1866 return true;

1867}

1868

1869

1871

1872

1873

1874

1875

1876

1877

1878 if (!OldPacketMIs.empty()) {

1879 auto *OldBB = OldPacketMIs.front()->getParent();

1880 auto *ThisBB = I.getParent();

1881 if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))

1882 return 0;

1883 }

1884

1886 if (!SUI)

1887 return 0;

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

1904

1905

1906

1907

1908

1909

1912 for (auto &Pred : SUI->Preds)

1913 if (Pred.getSUnit() == SUJ)

1914 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||

1915 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))

1916 return 0;

1917 }

1918

1919

1920

1921 for (auto *J : OldPacketMIs) {

1923 for (auto &Pred : SUI->Preds)

1924 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)

1925 return Pred.getLatency();

1926 }

1927

1928 return 0;

1929}

1930

1934 return false;

1935

1936 if (PacketStalls)

1937 return Latency > PacketStallCycles;

1938 return true;

1939}

1940

1941

1942

1943

1944

1946 return new HexagonPacketizer(Minimal);

1947}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements the BitVector class.

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This file defines the DenseSet and SmallDenseSet classes.

cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/" "packetization boundary."))

#define HEXAGON_LRFP_SIZE

static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)

Definition HexagonVLIWPacketizer.cpp:1097

static bool isDirectJump(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:323

static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)

Definition HexagonVLIWPacketizer.cpp:154

static bool isRegDependence(const SDep::Kind DepType)

Definition HexagonVLIWPacketizer.cpp:318

static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:601

static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::Hidden, cl::desc("Generate all instruction with TC"))

static bool isControlFlow(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:335

static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::Hidden, cl::desc("Disable vector double new-value-stores"))

static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)

Returns true if an instruction is predicated on p0 and false if it's predicated on !...

Definition HexagonVLIWPacketizer.cpp:558

static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)

Gets the predicate register of a predicated instruction.

Definition HexagonVLIWPacketizer.cpp:940

static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::desc("Disable Hexagon packetizer pass"))

static cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))

PredicateKind

Definition HexagonVLIWPacketizer.cpp:550

@ PK_Unknown

Definition HexagonVLIWPacketizer.cpp:553

@ PK_True

Definition HexagonVLIWPacketizer.cpp:552

@ PK_False

Definition HexagonVLIWPacketizer.cpp:551

static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))

static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)

Definition HexagonVLIWPacketizer.cpp:140

static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)

Returns true if the instruction modifies a callee-saved register.

Definition HexagonVLIWPacketizer.cpp:340

static bool isLoadAbsSet(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:606

static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:620

static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)

Definition HexagonVLIWPacketizer.cpp:567

static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, unsigned DepReg)

Definition HexagonVLIWPacketizer.cpp:827

static bool isSchedBarrier(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:327

static bool isSystemInstr(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:1186

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

uint64_t IntrinsicInst * II

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

Implements a dense probed hash-table based set.

FunctionPass class - This class is used to implement most global optimizations.

bool isPredicated(const MachineInstr &MI) const override

Returns true if the instruction is already predicated.

bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const

bool isRestrictNoSlot1Store(const MachineInstr &MI) const

bool isPureSlot0(const MachineInstr &MI) const

bool isPostIncrement(const MachineInstr &MI) const override

Return true for post-incremented instructions.

uint64_t getType(const MachineInstr &MI) const

bool isPredicatedTrue(const MachineInstr &MI) const

bool isNewValueStore(const MachineInstr &MI) const

bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)

Definition HexagonVLIWPacketizer.cpp:958

bool updateOffset(SUnit *SUI, SUnit *SUJ)

Return true if we can update the offset in MI so that MI and MJ can be packetized together.

Definition HexagonVLIWPacketizer.cpp:507

void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override

Definition HexagonVLIWPacketizer.cpp:1780

bool getmemShufDisabled()

HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA, const MachineBranchProbabilityInfo *MBPI, bool Minimal)

Definition HexagonVLIWPacketizer.cpp:126

bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)

Definition HexagonVLIWPacketizer.cpp:294

bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

Definition HexagonVLIWPacketizer.cpp:367

bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

Definition HexagonVLIWPacketizer.cpp:449

bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override

Definition HexagonVLIWPacketizer.cpp:1316

bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

Definition HexagonVLIWPacketizer.cpp:398

void useCalleesSP(MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:489

bool demoteToDotOld(MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:462

bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)

Definition HexagonVLIWPacketizer.cpp:1152

const MachineLoopInfo * MLI

bool isSoloInstruction(const MachineInstr &MI) override

Definition HexagonVLIWPacketizer.cpp:1057

bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override

Definition HexagonVLIWPacketizer.cpp:1634

void initPacketizerState() override

Definition HexagonVLIWPacketizer.cpp:1025

bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)

Definition HexagonVLIWPacketizer.cpp:1225

bool restrictingDepExistInPacket(MachineInstr &, unsigned)

Definition HexagonVLIWPacketizer.cpp:911

bool producesStall(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:1931

void undoChangedOffset(MachineInstr &MI)

Undo the changed offset.

Definition HexagonVLIWPacketizer.cpp:543

bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)

Definition HexagonVLIWPacketizer.cpp:1291

void cleanUpDotCur()

Definition HexagonVLIWPacketizer.cpp:376

unsigned int calcStall(const MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:1870

bool foundLSInPacket()

Definition HexagonVLIWPacketizer.cpp:1681

bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

Definition HexagonVLIWPacketizer.cpp:841

bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)

Definition HexagonVLIWPacketizer.cpp:811

bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override

Definition HexagonVLIWPacketizer.cpp:1035

void unpacketizeSoloInstrs(MachineFunction &MF)

Definition HexagonVLIWPacketizer.cpp:1157

const MachineBranchProbabilityInfo * MBPI

A handle to the branch probability pass.

bool shouldAddToPacket(const MachineInstr &MI) override

Definition HexagonVLIWPacketizer.cpp:1826

bool canReserveResourcesForConstExt()

Definition HexagonVLIWPacketizer.cpp:279

bool useCallersSP(MachineInstr &MI)

Definition HexagonVLIWPacketizer.cpp:468

bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)

Definition HexagonVLIWPacketizer.cpp:642

bool tryAllocateResourcesForConstExt(bool Reserve)

Definition HexagonVLIWPacketizer.cpp:285

void setmemShufDisabled(bool val)

void reserveResourcesForConstExt()

Definition HexagonVLIWPacketizer.cpp:274

MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override

Definition HexagonVLIWPacketizer.cpp:1701

bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)

Definition HexagonVLIWPacketizer.cpp:1198

bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)

Definition HexagonVLIWPacketizer.cpp:351

bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)

Definition HexagonVLIWPacketizer.cpp:1261

const HexagonInstrInfo * getInstrInfo() const override

const HexagonRegisterInfo * getRegisterInfo() const override

bool hasV60OpsOnly() const

Describe properties that are true of each instruction in the target description file.

unsigned getSchedClass() const

Return the scheduling class for this instruction.

Instructions::iterator instr_iterator

Instructions::const_iterator const_instr_iterator

MachineInstrBundleIterator< MachineInstr > iterator

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

instr_iterator getInstrIterator() const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

bool isTerminator(QueryType Type=AnyInBundle) const

Returns true if this instruction part of the terminator for a basic block.

bool isImplicitDef() const

bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr reads the specified register.

bool isBarrier(QueryType Type=AnyInBundle) const

Returns true if the specified instruction stops control flow from executing the instruction immediate...

bool isCall(QueryType Type=AnyInBundle) const

bool isBranch(QueryType Type=AnyInBundle) const

Returns true if this is a conditional, unconditional, or indirect branch.

bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr modifies (fully define or partially define) the specified register.

LLVM_ABI void unbundleFromPred()

Break bundle above this instruction.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

const MCInstrDesc & getDesc() const

Returns the target instruction descriptor of this MachineInstr.

LLVM_ABI void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

LLVM_ABI bool hasOrderedMemoryRef() const

Return true if this instruction may have an ordered or volatile memory reference, or if the informati...

bool mayStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly modify memory.

bool isBundledWithSucc() const

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

Wrapper class representing virtual and physical registers.

Kind

These are the different kinds of scheduling dependencies.

@ Output

A register output-dependence (aka WAW).

@ Order

Any other ordering dependency.

@ Anti

A register anti-dependence (aka WAR).

@ Data

Regular data dependence (aka true-dependence).

Scheduling unit. This is a node in the scheduling DAG.

bool isSucc(const SUnit *N) const

Tests if node N is a successor of this node.

SmallVector< SDep, 4 > Succs

All sunit successors.

SmallVector< SDep, 4 > Preds

All sunit predecessors.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA)

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

bool alias(const MachineInstr &MI1, const MachineInstr &MI2, bool UseTBAA=true) const

std::vector< MachineInstr * > CurrentPacketMIs

std::map< MachineInstr *, SUnit * > MIToSUnit

DFAPacketizer * ResourceTracker

std::pair< iterator, bool > insert(const ValueT &V)

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

std::string utohexstr(uint64_t X, bool LowerCase=false, unsigned Width=0)

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

FunctionPass * createHexagonPacketizer(bool Minimal)

Definition HexagonVLIWPacketizer.cpp:1945

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

DWARFExpression::Operation Op