LLVM: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp File Reference (original) (raw)

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Macros
#define	DEBUG_TYPE "packets"

Enumerations
enum	PredicateKind { PK_False, PK_True, PK_Unknown }

Functions
	INITIALIZE_PASS_BEGIN (HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
static bool	hasWriteToReadDep (const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
static MachineBasicBlock::iterator	moveInstrOut (MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
static bool	isRegDependence (const SDep::Kind DepType)
static bool	isDirectJump (const MachineInstr &MI)
static bool	isSchedBarrier (const MachineInstr &MI)
static bool	isControlFlow (const MachineInstr &MI)
static bool	doesModifyCalleeSavedReg (const MachineInstr &MI, const TargetRegisterInfo *TRI)
	Returns true if the instruction modifies a callee-saved register.
static PredicateKind	getPredicateSense (const MachineInstr &MI, const HexagonInstrInfo *HII)
	Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.
static const MachineOperand &	getPostIncrementOperand (const MachineInstr &MI, const HexagonInstrInfo *HII)
static const MachineOperand &	getStoreValueOperand (const MachineInstr &MI)
static bool	isLoadAbsSet (const MachineInstr &MI)
static const MachineOperand &	getAbsSetOperand (const MachineInstr &MI)
static bool	isImplicitDependency (const MachineInstr &I, bool CheckDef, unsigned DepReg)
static unsigned	getPredicatedRegister (MachineInstr &MI, const HexagonInstrInfo *QII)
	Gets the predicate register of a predicated instruction.
static bool	cannotCoexistAsymm (const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
static bool	isSystemInstr (const MachineInstr &MI)

Variables
static cl::opt< bool >	DisablePacketizer ("disable-packetizer", cl::Hidden, cl::desc("Disable Hexagon packetizer pass"))
static cl::opt< bool >	Slot1Store ("slot1-store-slot0-load", cl::Hidden, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
static cl::opt< bool >	PacketizeVolatiles ("hexagon-packetize-volatiles", cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
static cl::opt< bool >	EnableGenAllInsnClass ("enable-gen-insn", cl::Hidden, cl::desc("Generate all instruction with TC"))
static cl::opt< bool >	DisableVecDblNVStores ("disable-vecdbl-nv-stores", cl::Hidden, cl::desc("Disable vector double new-value-stores"))
cl::opt< bool >	ScheduleInlineAsm
hexagon	packetizer
hexagon Hexagon	Packetizer
hexagon Hexagon	false

◆ DEBUG_TYPE

#define DEBUG_TYPE "packets"

◆ PredicateKind

◆ cannotCoexistAsymm()

Definition at line 1097 of file HexagonVLIWPacketizer.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::HexagonInstrInfo::getType(), llvm::HexagonSubtarget::hasV60OpsOnly(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isCall(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::MachineInstr::isInlineAsm(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isPureSlot0(), llvm::HexagonInstrInfo::isRestrictNoSlot1Store(), llvm::MachineInstr::isTerminator(), llvm::MachineInstr::mayStore(), MI, llvm::HexagonII::TypeALU32_2op, llvm::HexagonII::TypeALU32_3op, and llvm::HexagonII::TypeALU32_ADDI.

Referenced by llvm::HexagonPacketizerList::cannotCoexist().

◆ doesModifyCalleeSavedReg()

◆ getAbsSetOperand()

◆ getPostIncrementOperand()

Definition at line 567 of file HexagonVLIWPacketizer.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::HexagonInstrInfo::isPostIncrement(), llvm::MachineOperand::isReg(), llvm_unreachable, and MI.

Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().

◆ getPredicatedRegister()

◆ getPredicateSense()

◆ getStoreValueOperand()

◆ hasWriteToReadDep()

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	HexagonPacketizer	,
"hexagon-packetizer"	,
"Hexagon Packetizer"	,
false	,
false	)

◆ isControlFlow()

◆ isDirectJump()

◆ isImplicitDependency()

◆ isLoadAbsSet()

◆ isRegDependence()

◆ isSchedBarrier()

◆ isSystemInstr()

◆ moveInstrOut()

Definition at line 154 of file HexagonVLIWPacketizer.cpp.

References assert(), B(), llvm::MachineInstr::BundledPred, llvm::MachineInstr::BundledSucc, E(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), I, llvm::MachineInstr::isBundledWithSucc(), MI, Size, and llvm::MachineInstr::unbundleFromPred().

Referenced by llvm::HexagonPacketizerList::unpacketizeSoloInstrs().

◆ DisablePacketizer

cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::desc("Disable Hexagon packetizer pass")) ( "disable-packetizer" , cl::Hidden , cl::desc("Disable Hexagon packetizer pass") )	static

◆ DisableVecDblNVStores

cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::Hidden, cl::desc("Disable vector double new-value-stores")) ( "disable-vecdbl-nv-stores" , cl::Hidden , cl::desc("Disable vector double new-value-stores") )	static

◆ EnableGenAllInsnClass

cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::Hidden, cl::desc("Generate all instruction with TC")) ( "enable-gen-insn" , cl::Hidden , cl::desc("Generate all instruction with TC") )	static

◆ false

◆ Packetizer

hexagon Hexagon Packetizer

◆ packetizer

◆ PacketizeVolatiles

cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references")) ( "hexagon-packetize-volatiles" , cl::Hidden , cl::init(true) , cl::desc("Allow non-solo packetization of volatile memory references") )	static

◆ ScheduleInlineAsm

◆ Slot1Store

cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::init(true), cl::desc("Allow slot1 store and slot0 load")) ( "slot1-store-slot0-load" , cl::Hidden , cl::init(true) , cl::desc("Allow slot1 store and slot0 load") )	static