MachineInstr.cpp Source File (original) (raw)

57#include

58#include

59#include

60#include

61#include

63using namespace llvm;

68 return MF;

69 return nullptr;

70}

81 TRI = MF->getSubtarget().getRegisterInfo();

82 MRI = &MF->getRegInfo();

83 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();

84 TII = MF->getSubtarget().getInstrInfo();

85 }

86}

93}

100 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),

101 DbgLoc(std::move(DL)), DebugInstrNum(0), Opcode(TID.Opcode) {

103

104

107 CapOperands = OperandCapacity::get(NumOps);

109 }

110

111 if (!NoImp)

113}

114

115

116

117

119 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),

123

124 CapOperands = OperandCapacity::get(MI.getNumOperands());

126

127

130

131

132

136 NewMO.TiedTo = OrigMO.TiedTo;

137 }

138

139

141}

142

146 MCID = &TID;

148}

149

152}

153

154

155

156

160 return nullptr;

161}

162

166 return nullptr;

167}

168

171 if (MO.isReg())

172 MRI.removeRegOperandFromUseList(&MO);

173}

174

177 if (MO.isReg())

178 MRI.addRegOperandToUseList(&MO);

179}

180

183 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");

185 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");

187}

188

189

190

194 return MRI->moveOperands(Dst, Src, NumOps);

195

196 assert(Dst && Src && "Unknown operands");

197 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));

198}

199

200

201

202

203

205 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&

206 "Cannot add more operands.");

207 assert(MCID && "Cannot add operands before providing an instr descriptor");

208

209

210 if (&Op >= Operands && &Op < Operands + NumOperands) {

211

212

213

216 }

217

218

219

220

221

222

223

224

226 bool isImpReg = Op.isReg() && Op.isImplicit();

228 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {

229 --OpNo;

230 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");

231 }

232 }

233

234

235

236

238

239

240

241 OperandCapacity OldCap = CapOperands;

243 if (!OldOperands || OldCap.getSize() == getNumOperands()) {

244 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);

246

247 if (OpNo)

249 }

250

251

252 if (OpNo != NumOperands)

253 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,

255 ++NumOperands;

256

257

258 if (OldOperands != Operands && OldOperands)

260

261

263 NewMO->ParentMI = this;

264

265

266 if (NewMO->isReg()) {

267

268 NewMO->Contents.Reg.Prev = nullptr;

269

270 NewMO->TiedTo = 0;

271

273 MRI->addRegOperandToUseList(NewMO);

274

275

276

277 if (!isImpReg) {

278

279 if (NewMO->isUse()) {

281 if (DefIdx != -1)

283 }

284

287 }

288

291 }

292}

293

297

298#ifndef NDEBUG

299

300 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)

301 if (Operands[i].isReg())

302 assert(!Operands[i].isTied() && "Cannot move tied operands");

303#endif

304

306 if (MRI && Operands[OpNo].isReg())

307 MRI->removeRegOperandFromUseList(Operands + OpNo);

308

309

310

311

312

313 if (unsigned N = NumOperands - 1 - OpNo)

315 --NumOperands;

316}

317

324 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;

325 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;

326 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;

327 bool HasPCSections = PCSections != nullptr;

328 bool HasCFIType = CFIType != 0;

329 bool HasMMRAs = MMRAs != nullptr;

330 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +

331 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs;

332

333

334 if (NumPointers <= 0) {

335 Info.clear();

336 return;

337 }

338

339

340

341

342

343 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||

344 HasCFIType) {

345 Info.set<EIIK_OutOfLine>(

347 HeapAllocMarker, PCSections, CFIType, MMRAs));

348 return;

349 }

350

351

352 if (HasPreInstrSymbol)

353 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);

354 else if (HasPostInstrSymbol)

355 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);

356 else

357 Info.set<EIIK_MMO>(MMOs[0]);

358}

359

362 return;

363

367}

368

371 if (MMOs.empty()) {

373 return;

374 }

375

379}

380

387}

388

390 if (this == &MI)

391

392 return;

393

395 "Invalid machine functions when cloning memory refrences!");

396

397

398

403 MI.getMMRAMetadata()) {

404 Info = MI.Info;

405 return;

406 }

407

408

410}

411

412

413

416 if (LHS.size() != RHS.size())

417 return false;

418

421 return std::equal(LHSPointees.begin(), LHSPointees.end(),

422 RHSPointees.begin());

423}

424

427

428 if (MIs.empty()) {

430 return;

431 }

432 if (MIs.size() == 1) {

434 return;

435 }

436

437

438

441 return;

442 }

443

444

446

448 "Invalid machine functions when cloning memory references!");

450

453 "Invalid machine functions when cloning memory references!");

454

455

456

457

459 continue;

460

461

462

463

464 if (MI.memoperands_empty()) {

466 return;

467 }

468

469

470 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());

471 }

472

474}

475

477

479 return;

480

481

482 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {

483 Info.clear();

484 return;

485 }

486

490}

491

493

495 return;

496

497

498 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {

499 Info.clear();

500 return;

501 }

502

506}

507

509

511 return;

512

515}

516

518

520 return;

521

525}

526

528

530 return;

531

534}

535

537

539 return;

540

543}

544

547 if (this == &MI)

548

549 return;

550

552 "Invalid machine functions when cloning instruction symbols!");

553

559}

560

562

563

565}

566

569

571 dyn_cast(&I)) {

572 if (OB->hasNoSignedWrap())

574 if (OB->hasNoUnsignedWrap())

576 } else if (const TruncInst *TI = dyn_cast(&I)) {

577 if (TI->hasNoSignedWrap())

579 if (TI->hasNoUnsignedWrap())

582 if (GEP->hasNoUnsignedSignedWrap())

584 if (GEP->hasNoUnsignedWrap())

586 }

587

588

590 if (PNI->hasNonNeg())

592

594 dyn_cast(&I)) {

595 if (PD->isDisjoint())

597 }

598

599

600 if (const ICmpInst *ICmp = dyn_cast(&I))

601 if (ICmp->hasSameSign())

603

604

606 if (PE->isExact())

608

609

612 if (Flags.noNaNs())

614 if (Flags.noInfs())

616 if (Flags.noSignedZeros())

618 if (Flags.allowReciprocal())

620 if (Flags.allowContract())

622 if (Flags.approxFunc())

624 if (Flags.allowReassoc())

626 }

627

628 if (I.getMetadata(LLVMContext::MD_unpredictable))

630

631 return MIFlags;

632}

633

636}

637

638bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {

641 if (MII->getDesc().getFlags() & Mask) {

643 return true;

644 } else {

646 return false;

647 }

648

649 if (!MII->isBundledWithSucc())

651 }

652}

653

656

657

660 return false;

661

663

664

665

666 assert(Other.isBundle() && "Expected that both instructions are bundles.");

669

670

671 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {

672 ++I1;

673 ++I2;

674 if (!I1->isIdenticalTo(*I2, Check))

675 return false;

676 }

677

678

679 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())

680 return false;

681 }

682

683

684 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

687 if (!MO.isReg()) {

689 return false;

690 continue;

691 }

692

693

694

695

696 if (MO.isDef()) {

698 continue;

702 return false;

703 } else {

705 return false;

707 return false;

708 }

709 } else {

711 return false;

713 return false;

714 }

715 }

716

720 return false;

721

722

725 return false;

726

728 return false;

729

730 return true;

731}

732

735 return false;

737 return false;

739 return false;

741 return false;

744 return false;

747 Other.getDebugExpression(), Other.isIndirectDebugValue()))

748 return false;

749 return true;

750}

751

754}

755

759}

760

764}

765

769}

770

774}

775

778 return false;

780 case TargetOpcode::PATCHPOINT:

781 case TargetOpcode::STACKMAP:

782 case TargetOpcode::STATEPOINT:

783 case TargetOpcode::FENTRY_CALL:

784 return false;

785 }

786 return true;

787}

788

793}

794

798 return NumOperands;

799

800 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {

802

803

804

805

806

808 break;

809 ++NumOperands;

810 }

811 return NumOperands;

812}

813

815 unsigned NumDefs = MCID->getNumDefs();

817 return NumDefs;

818

822 break;

823 ++NumDefs;

824 }

825 return NumDefs;

826}

827

832 --Pred;

833 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");

835}

836

841 ++Succ;

842 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");

844}

845

850 --Pred;

851 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");

853}

854

859 ++Succ;

860 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");

862}

863

868 return true;

869 }

870 return false;

871}

872

874 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");

877}

878

880 unsigned *GroupNo) const {

883

884

886 return -1;

887

888 unsigned Group = 0;

889 unsigned NumOps;

891 i += NumOps) {

893

894 if (!FlagMO.isImm())

895 return -1;

897 NumOps = 1 + F.getNumOperandRegisters();

898 if (i + NumOps > OpIdx) {

899 if (GroupNo)

900 *GroupNo = Group;

901 return i;

902 }

903 ++Group;

904 }

905 return -1;

906}

907

910 return cast(getOperand(0).getMetadata());

911}

912

917}

918

923}

924

927}

928

933}

934

939}

940

943}

944

947}

948

953 assert(getParent() && "Can't have an MBB reference here!");

954 assert(getMF() && "Can't have an MF reference here!");

956

957

959 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);

960

962 return nullptr;

963

964

965 unsigned DefIdx;

967 OpIdx = DefIdx;

968

969

971 if (FlagIdx < 0)

972 return nullptr;

973

975 unsigned RCID;

976 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&

977 F.hasRegClassConstraint(RCID))

978 return TRI->getRegClass(RCID);

979

980

981 if (F.isMemKind())

982 return TRI->getPointerRegClass(MF);

983

984 return nullptr;

985}

986

990

991

992 if (ExploreBundle)

994 ++OpndIt)

995 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(

996 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);

997 else

998

999 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)

1000 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);

1001 return CurRC;

1002}

1003

1004const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(

1007 assert(CurRC && "Invalid initial register class");

1008

1011 return CurRC;

1012

1014}

1015

1022 "Cannot get register constraints for non-register operand");

1023 assert(CurRC && "Invalid initial register class");

1024 if (unsigned SubIdx = MO.getSubReg()) {

1025 if (OpRC)

1026 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);

1027 else

1028 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);

1029 } else if (OpRC)

1030 CurRC = TRI->getCommonSubClass(CurRC, OpRC);

1031 return CurRC;

1032}

1033

1034

1035

1038 unsigned Size = 0;

1039 while (I->isBundledWithSucc()) {

1041 ++I;

1042 }

1043 return Size;

1044}

1045

1046

1047

1051 return true;

1052 }

1053 return false;

1054}

1055

1056

1057

1058

1061 bool isKill) const {

1062 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1065 continue;

1067 if (!MOReg)

1068 continue;

1069 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))

1071 return i;

1072 }

1073 return -1;

1074}

1075

1076

1077

1078

1079std::pair<bool,bool>

1082 bool PartDef = false;

1083 bool FullDef = false;

1084 bool Use = false;

1085

1086 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1089 continue;

1090 if (Ops)

1095

1096 PartDef = true;

1097 else

1098 FullDef = true;

1099 }

1100

1101 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);

1102}

1103

1104

1105

1106

1107

1110 bool isDead, bool Overlap) const {

1111 bool isPhys = Reg.isPhysical();

1112 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1114

1115

1117 return i;

1119 continue;

1121 bool Found = (MOReg == Reg);

1122 if (!Found && TRI && isPhys && MOReg.isPhysical()) {

1123 if (Overlap)

1124 Found = TRI->regsOverlap(MOReg, Reg);

1125 else

1126 Found = TRI->isSubRegister(MOReg, Reg);

1127 }

1129 return i;

1130 }

1131 return -1;

1132}

1133

1134

1135

1136

1138

1139

1140

1141

1144 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)

1145 if (MCID.operands()[i].isPredicate())

1146 return i;

1147 }

1148

1149 return -1;

1150}

1151

1152

1154

1155

1156

1157

1158

1159

1160

1161

1162

1163

1164

1165

1166

1170 assert(DefMO.isDef() && "DefIdx must be a def operand");

1171 assert(UseMO.isUse() && "UseIdx must be a use operand");

1172 assert(!DefMO.isTied() && "Def is already tied to another use");

1173 assert(!UseMO.isTied() && "Use is already tied to another def");

1174

1176 UseMO.TiedTo = DefIdx + 1;

1177 else {

1178

1179

1180

1181

1183 "DefIdx out of range");

1185 }

1186

1187

1188 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);

1189}

1190

1191

1192

1193

1196 assert(MO.isTied() && "Operand isn't tied");

1197

1198

1199 if (MO.TiedTo < TiedMax)

1200 return MO.TiedTo - 1;

1201

1202

1204

1207

1210 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)

1211 return i;

1212 }

1214 }

1215

1216 if (getOpcode() == TargetOpcode::STATEPOINT) {

1217

1218

1221 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");

1223 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {

1226 if (OpIdx == CurDefIdx)

1227 return CurUseIdx;

1228 if (OpIdx == CurUseIdx)

1229 return CurDefIdx;

1231 }

1233 }

1234

1235

1236

1238 unsigned OpIdxGroup = ~0u;

1239 unsigned NumOps;

1241 i += NumOps) {

1243 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");

1244 unsigned CurGroup = GroupIdx.size();

1247 NumOps = 1 + F.getNumOperandRegisters();

1248

1249 if (OpIdx > i && OpIdx < i + NumOps)

1250 OpIdxGroup = CurGroup;

1251 unsigned TiedGroup;

1252 if (.isUseOperandTiedToDef(TiedGroup))

1253 continue;

1254

1255

1256 unsigned Delta = i - GroupIdx[TiedGroup];

1257

1258

1259 if (OpIdxGroup == CurGroup)

1260 return OpIdx - Delta;

1261

1262

1263 if (OpIdxGroup == TiedGroup)

1264 return OpIdx + Delta;

1265 }

1267}

1268

1269

1270

1275 }

1276}

1277

1279 unsigned SubIdx,

1282 if (SubIdx)

1283 ToReg = RegInfo.getSubReg(ToReg, SubIdx);

1285 if (!MO.isReg() || MO.getReg() != FromReg)

1286 continue;

1288 }

1289 } else {

1291 if (!MO.isReg() || MO.getReg() != FromReg)

1292 continue;

1294 }

1295 }

1296}

1297

1298

1299

1300

1302

1303

1304

1305

1306

1309 SawStore = true;

1310 return false;

1311 }

1312

1316 return false;

1317

1318

1319

1320

1321

1322

1324

1325

1326 return !SawStore;

1327

1328 return true;

1329}

1330

1332

1333

1334 if (getOpcode() == TargetOpcode::LOCAL_ESCAPE)

1335 return false;

1336

1337

1338

1340 return false;

1341

1342

1343

1345 return false;

1346

1347

1348

1349 bool SawStore = false;

1351}

1352

1357

1358

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1369

1370 int64_t OffsetA = MMOa->getOffset();

1371 int64_t OffsetB = MMOb->getOffset();

1372 int64_t MinOffset = std::min(OffsetA, OffsetB);

1373

1376 bool KnownWidthA = WidthA.hasValue();

1377 bool KnownWidthB = WidthB.hasValue();

1379

1382 bool SameVal = (ValA && ValB && (ValA == ValB));

1383 if (!SameVal) {

1386 if (PSVa && ValB && !PSVa->mayAlias(&MFI))

1387 return false;

1388 if (PSVb && ValA && !PSVb->mayAlias(&MFI))

1389 return false;

1390 if (PSVa && PSVb && (PSVa == PSVb))

1391 SameVal = true;

1392 }

1393

1394 if (SameVal && BothMMONonScalable) {

1395 if (!KnownWidthA || !KnownWidthB)

1396 return true;

1397 int64_t MaxOffset = std::max(OffsetA, OffsetB);

1398 int64_t LowWidth = (MinOffset == OffsetA)

1401 return (MinOffset + LowWidth > MaxOffset);

1402 }

1403

1404 if (!AA)

1405 return true;

1406

1407 if (!ValA || !ValB)

1408 return true;

1409

1410 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");

1411 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");

1412

1413

1414

1415 if ((WidthA.isScalable() && OffsetA > 0) ||

1416 (WidthB.isScalable() && OffsetB > 0))

1417 return true;

1418

1419 int64_t OverlapA =

1422 int64_t OverlapB =

1425

1427 ? WidthA

1430 ? WidthB

1432

1436}

1437

1443

1444

1445

1447 return true;

1448

1449

1450

1452 return false;

1453

1454

1456 return false;

1457

1458

1460 return false;

1461

1462

1463

1465 return true;

1466

1467

1469 if (NumChecks > TII->getMemOperandAACheckLimit())

1470 return true;

1471

1472

1473

1475 for (auto *MMOb : Other.memoperands())

1477 return true;

1478

1479 return false;

1480}

1481

1484 if (AA) {

1487 }

1489}

1490

1491

1492

1493

1494

1496

1501 return false;

1502

1503

1504

1506 return true;

1507

1508

1511 });

1512}

1513

1514

1515

1516

1518

1520 return false;

1521

1522

1523

1525 return false;

1526

1528

1530 if (!MMO->isUnordered())

1531

1532

1533

1534 return false;

1535 if (MMO->isStore()) return false;

1536 if (MMO->isInvariant() && MMO->isDereferenceable())

1537 continue;

1538

1539

1541 if (PSV->isConstant(&MFI))

1542 continue;

1543 }

1544

1545

1546 return false;

1547 }

1548

1549

1550 return true;

1551}

1552

1555 return {};

1557 "It's illegal to have a PHI without source operands");

1558

1560 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)

1562 return {};

1563 return Reg;

1564}

1565

1568 return true;

1572 return true;

1573 }

1574

1575 return false;

1576}

1577

1581}

1582

1583

1584

1588 continue;

1590 return false;

1591 }

1592 return true;

1593}

1594

1598 continue;

1600 return false;

1601 }

1602 return true;

1603}

1604

1605

1606

1613}

1614

1617 if (MCID.Opcode == TargetOpcode::STATEPOINT)

1618 return true;

1621 if (!Operand.isReg() || Operand.isDef())

1622

1623 continue;

1626 if (ExpectedTiedIdx != TiedIdx)

1627 return true;

1628 }

1629 return false;

1630}

1631

1635 if (.isReg())

1636 return LLT{};

1637

1639 return MRI.getType(Op.getReg());

1640

1642 if (!OpInfo.isGenericType())

1643 return MRI.getType(Op.getReg());

1644

1645 if (PrintedTypes[OpInfo.getGenericTypeIndex()])

1646 return LLT{};

1647

1648 LLT TypeToPrint = MRI.getType(Op.getReg());

1649

1650

1651 if (TypeToPrint.isValid())

1652 PrintedTypes.set(OpInfo.getGenericTypeIndex());

1653 return TypeToPrint;

1654}

1655

1656#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

1658 dbgs() << " ";

1660}

1661

1665 if (Depth >= MaxDepth)

1666 return;

1667 if (!AlreadySeenInstrs.insert(this).second)

1668 return;

1669

1670

1676 continue;

1678 if (Reg.isPhysical())

1679 continue;

1681 if (NewMI == nullptr)

1682 continue;

1683 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);

1684 }

1685}

1686

1688 unsigned MaxDepth) const {

1690 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);

1691}

1692#endif

1693

1695 bool SkipDebugLoc, bool AddNewLine,

1697 const Module *M = nullptr;

1701 M = F->getParent();

1702 if ( TII )

1704 }

1705

1707 if (F)

1709 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);

1710}

1711

1713 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,

1715

1720

1723

1726 auto getTiedOperandIdx = [&](unsigned OpIdx) {

1727 if (!ShouldPrintRegisterTies)

1728 return 0U;

1732 return 0U;

1733 };

1734 unsigned StartOp = 0;

1736

1737

1738 while (StartOp < e) {

1741 break;

1742

1743 if (StartOp != 0)

1744 OS << ", ";

1745

1747 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);

1748 MO.print(OS, MST, TypeToPrint, StartOp, false, IsStandalone,

1749 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);

1750 ++StartOp;

1751 }

1752

1753 if (StartOp != 0)

1754 OS << " = ";

1755

1757 OS << "frame-setup ";

1759 OS << "frame-destroy ";

1761 OS << "nnan ";

1763 OS << "ninf ";

1765 OS << "nsz ";

1767 OS << "arcp ";

1769 OS << "contract ";

1771 OS << "afn ";

1773 OS << "reassoc ";

1775 OS << "nuw ";

1777 OS << "nsw ";

1779 OS << "exact ";

1781 OS << "nofpexcept ";

1783 OS << "nomerge ";

1785 OS << "nneg ";

1787 OS << "disjoint ";

1789 OS << "samesign ";

1790

1791

1792 if (TII)

1794 else

1795 OS << "UNKNOWN";

1796

1797 if (SkipOpers)

1798 return;

1799

1800

1801 bool FirstOp = true;

1802 unsigned AsmDescOp = ~0u;

1803 unsigned AsmOpCount = 0;

1804

1806

1807 OS << " ";

1810 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);

1811 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, true, IsStandalone,

1812 ShouldPrintRegisterTies, TiedOperandIdx, TRI,

1813 IntrinsicInfo);

1814

1815

1818 OS << " [sideeffect]";

1820 OS << " [mayload]";

1822 OS << " [maystore]";

1824 OS << " [isconvergent]";

1826 OS << " [alignstack]";

1828 OS << " [attdialect]";

1830 OS << " [inteldialect]";

1831

1833 FirstOp = false;

1834 }

1835

1836 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {

1838

1839 if (FirstOp) FirstOp = false; else OS << ",";

1840 OS << " ";

1841

1843

1844 auto *DIV = dyn_cast(MO.getMetadata());

1845 if (DIV && !DIV->getName().empty())

1846 OS << "!\"" << DIV->getName() << '\"';

1847 else {

1849 unsigned TiedOperandIdx = getTiedOperandIdx(i);

1850 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

1851 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);

1852 }

1854

1855 auto *DIL = dyn_cast(MO.getMetadata());

1856 if (DIL && !DIL->getName().empty())

1857 OS << "\"" << DIL->getName() << '\"';

1858 else {

1860 unsigned TiedOperandIdx = getTiedOperandIdx(i);

1861 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

1862 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);

1863 }

1864 } else if (i == AsmDescOp && MO.isImm()) {

1865

1866 OS << '$' << AsmOpCount++;

1867 unsigned Flag = MO.getImm();

1869 OS << ":[";

1870 OS << F.getKindName();

1871

1872 unsigned RCID;

1873 if (.isImmKind() && .isMemKind() && F.hasRegClassConstraint(RCID)) {

1874 if (TRI) {

1875 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));

1876 } else

1877 OS << ":RC" << RCID;

1878 }

1879

1880 if (F.isMemKind()) {

1883 }

1884

1885 unsigned TiedTo;

1886 if (F.isUseOperandTiedToDef(TiedTo))

1887 OS << " tiedto:$" << TiedTo;

1888

1889 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||

1890 F.isRegUseKind()) &&

1891 F.getRegMayBeFolded()) {

1892 OS << " foldable";

1893 }

1894

1895 OS << ']';

1896

1897

1898 AsmDescOp += 1 + F.getNumOperandRegisters();

1899 } else {

1901 unsigned TiedOperandIdx = getTiedOperandIdx(i);

1904 else

1905 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

1906 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);

1907 }

1908 }

1909

1910

1911

1913 if (!FirstOp) {

1914 FirstOp = false;

1915 OS << ',';

1916 }

1917 OS << " pre-instr-symbol ";

1919 }

1921 if (!FirstOp) {

1922 FirstOp = false;

1923 OS << ',';

1924 }

1925 OS << " post-instr-symbol ";

1927 }

1929 if (!FirstOp) {

1930 FirstOp = false;

1931 OS << ',';

1932 }

1933 OS << " heap-alloc-marker ";

1935 }

1937 if (!FirstOp) {

1938 FirstOp = false;

1939 OS << ',';

1940 }

1941 OS << " pcsections ";

1943 }

1945 if (!FirstOp) {

1946 FirstOp = false;

1947 OS << ',';

1948 }

1949 OS << " mmra ";

1950 MMRA->printAsOperand(OS, MST);

1951 }

1953 if (!FirstOp)

1954 OS << ',';

1955 OS << " cfi-type " << CFIType;

1956 }

1957

1958 if (DebugInstrNum) {

1959 if (!FirstOp)

1960 OS << ",";

1961 OS << " debug-instr-number " << DebugInstrNum;

1962 }

1963

1964 if (!SkipDebugLoc) {

1966 if (!FirstOp)

1967 OS << ',';

1968 OS << " debug-location ";

1970 }

1971 }

1972

1976 std::unique_ptr CtxPtr;

1981 } else {

1982 CtxPtr = std::make_unique();

1983 Context = CtxPtr.get();

1984 }

1985

1986 OS << " :: ";

1987 bool NeedComma = false;

1989 if (NeedComma)

1990 OS << ", ";

1991 Op->print(OS, MST, SSNs, *Context, MFI, TII);

1992 NeedComma = true;

1993 }

1994 }

1995

1996 if (SkipDebugLoc)

1997 return;

1998

1999 bool HaveSemi = false;

2000

2001

2003 if (!HaveSemi) {

2004 OS << ';';

2005 HaveSemi = true;

2006 }

2007 OS << ' ';

2009 }

2010

2011

2016 if (!HaveSemi) {

2017 OS << ";";

2018 HaveSemi = true;

2019 }

2021 OS << " line no:" << DV->getLine();

2023 OS << " indirect";

2024 }

2025 }

2026

2027

2028 if (AddNewLine)

2029 OS << '\n';

2030}

2031

2034 bool AddIfNotFound) {

2035 bool isPhysReg = IncomingReg.isPhysical();

2036 bool hasAliases = isPhysReg &&

2038 bool Found = false;

2040 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

2043 continue;

2044

2045

2046

2047

2049 continue;

2050

2052 if (!Reg)

2053 continue;

2054

2055 if (Reg == IncomingReg) {

2056 if (!Found) {

2058

2059 return true;

2061

2062 return true;

2064 Found = true;

2065 }

2066 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {

2067

2069 return true;

2072 }

2073 }

2074

2075

2076 while (!DeadOps.empty()) {

2077 unsigned OpIdx = DeadOps.back();

2078 if (getOperand(OpIdx).isImplicit() &&

2081 else

2084 }

2085

2086

2087

2088 if (!Found && AddIfNotFound) {

2090 false ,

2091 true ,

2092 true ));

2093 return true;

2094 }

2095 return Found;

2096}

2097

2100 if (!Reg.isPhysical())

2101 RegInfo = nullptr;

2104 continue;

2106 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)

2108 }

2109}

2110

2113 bool AddIfNotFound) {

2114 bool isPhysReg = Reg.isPhysical();

2115 bool hasAliases = isPhysReg &&

2117 bool Found = false;

2119 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

2122 continue;

2124 if (!MOReg)

2125 continue;

2126

2127 if (MOReg == Reg) {

2129 Found = true;

2130 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {

2131

2133 return true;

2136 }

2137 }

2138

2139

2140 while (!DeadOps.empty()) {

2141 unsigned OpIdx = DeadOps.back();

2142 if (getOperand(OpIdx).isImplicit() &&

2145 else

2148 }

2149

2150

2151

2152 if (Found || !AddIfNotFound)

2153 return Found;

2154

2156 true ,

2157 true ,

2158 false ,

2159 true ));

2160 return true;

2161}

2162

2165 if (MO.getReg() == Reg)

2167}

2168

2173}

2174

2177 if (Reg.isPhysical()) {

2179 if (MO)

2180 return;

2181 } else {

2184 return;

2185 }

2186 }

2188 true ,

2189 true ));

2190}

2191

2194 bool HasRegMask = false;

2197 HasRegMask = true;

2198 continue;

2199 }

2200 if (!MO.isReg() || !MO.isDef()) continue;

2202 if (!Reg.isPhysical())

2203 continue;

2204

2208 }

2209

2210

2211

2212 if (HasRegMask)

2213 for (const Register &UsedReg : UsedRegs)

2215}

2216

2217unsigned

2219

2221 HashComponents.reserve(MI->getNumOperands() + 1);

2222 HashComponents.push_back(MI->getOpcode());

2225 continue;

2226

2228 }

2230}

2231

2233

2234 const MDNode *LocMD = nullptr;

2237 (LocMD = getOperand(i-1).getMetadata()) &&

2239 if (mdconst::hasa(LocMD->getOperand(0)))

2240 return LocMD;

2241 }

2242 }

2243

2244 return nullptr;

2245}

2246

2251 LocMD

2252 ? mdconst::extract(LocMD->getOperand(0))->getZExtValue()

2253 : 0;

2256}

2257

2262}

2263

2265 const MCInstrDesc &MCID, bool IsIndirect,

2267 const MDNode *Expr) {

2268 assert(isa(Variable) && "not a variable");

2269 assert(cast(Expr)->isValid() && "not an expression");

2270 assert(cast(Variable)->isValidLocationForIntrinsic(DL) &&

2271 "Expected inlined-at fields to agree");

2273 if (IsIndirect)

2275 else

2278}

2279

2281 const MCInstrDesc &MCID, bool IsIndirect,

2283 const MDNode *Variable, const MDNode *Expr) {

2284 assert(isa(Variable) && "not a variable");

2285 assert(cast(Expr)->isValid() && "not an expression");

2286 assert(cast(Variable)->isValidLocationForIntrinsic(DL) &&

2287 "Expected inlined-at fields to agree");

2288 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {

2290 "DBG_VALUE must contain exactly one debug operand");

2292 if (DebugOp.isReg())

2293 return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,

2294 Expr);

2295

2296 auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);

2297 if (IsIndirect)

2299 else

2302 }

2303

2304 auto MIB = BuildMI(MF, DL, MCID);

2305 MIB.addMetadata(Variable).addMetadata(Expr);

2307 if (DebugOp.isReg())

2308 MIB.addReg(DebugOp.getReg());

2309 else

2310 MIB.add(DebugOp);

2311 return MIB;

2312}

2313

2317 bool IsIndirect, Register Reg,

2318 const MDNode *Variable, const MDNode *Expr) {

2323}

2324

2328 bool IsIndirect,

2330 const MDNode *Variable, const MDNode *Expr) {

2333 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);

2336}

2337

2338

2339

2343 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&

2344 "Expected inlined-at fields to agree");

2345

2347 if (MI.isIndirectDebugValue()) {

2348 assert(MI.getDebugOffset().getImm() == 0 &&

2349 "DBG_VALUE with nonzero offset");

2351 } else if (MI.isDebugValueList()) {

2352

2353

2354 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};

2356 unsigned OpIdx = MI.getDebugOperandIndex(Op);

2358 }

2359 }

2360 return Expr;

2361}

2364 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");

2366 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))

2369}

2370

2374 int FrameIndex, Register SpillReg) {

2376 "DBG_INSTR_REF should not reference a virtual register.");

2380

2381

2387 if (Op.isReg() && Op.getReg() == SpillReg)

2389 else

2391 }

2392 return NewMI;

2393}

2401

2402

2410 else

2412 }

2413 return NewMI;

2414}

2415

2422 Op.ChangeToFrameIndex(FrameIndex);

2424}

2425

2429 if (.getOperand(0).isReg())

2430 return;

2431

2434 DI != DE; ++DI) {

2435 if (!DI->isDebugValue())

2436 return;

2437 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))

2439 }

2440}

2441

2443

2445

2447 return;

2448

2450 auto *MRI = getRegInfo();

2451 for (auto &MO : MRI->use_operands(DefReg)) {

2453 if (!DI->isDebugValue())

2454 continue;

2455 if (DI->hasDebugOperandForReg(DefReg)) {

2457 }

2458 }

2459

2460

2461 for (auto *DBI : DbgValues)

2462 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))

2463 Op.setReg(Reg);

2464}

2465

2467

2471 for (const auto *A : Accesses) {

2473 cast(A->getPseudoValue())

2474 ->getFrameIndex())) {

2479 }

2480 }

2481 return Size;

2482}

2483

2484std::optional

2486 int FI;

2487 if (TII->isStoreToStackSlotPostFE(*this, FI)) {

2491 }

2492 return std::nullopt;

2493}

2494

2495std::optional

2500 return std::nullopt;

2501}

2502

2503std::optional

2505 int FI;

2506 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {

2510 }

2511 return std::nullopt;

2512}

2513

2514std::optional

2519 return std::nullopt;

2520}

2521

2523 if (DebugInstrNum == 0)

2525 return DebugInstrNum;

2526}

2527

2529 if (DebugInstrNum == 0)

2531 return DebugInstrNum;

2532}

2533

2537}

2538

2543}

2544

2550}

2551

2558}

2559

2560std::tuple<Register, LLT, Register, LLT>

2564 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,

2565 getRegInfo()->getType(Reg1));

2566}

2567

2568std::tuple<Register, LLT, Register, LLT, Register, LLT>

2573 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,

2574 getRegInfo()->getType(Reg1), Reg2,

2575 getRegInfo()->getType(Reg2));

2576}

2577

2578std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>

2584 return std::tuple(

2585 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),

2586 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));

2587}

2588

2597 return std::tuple(

2598 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),

2599 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),

2600 Reg4, getRegInfo()->getType(Reg4));

2601}

2602

2605 assert(InsertBefore != nullptr && "invalid iterator");

2607 "iterator points to operand of other inst");

2608 if (Ops.empty())

2609 return;

2610

2611

2617 TiedOpIndices[OpNo] = TiedTo;

2619 }

2620 }

2621

2622 unsigned OpIdx = getOperandNo(InsertBefore);

2624 unsigned OpsToMove = NumOperands - OpIdx;

2625

2627 MovingOps.reserve(OpsToMove);

2628

2629 for (unsigned I = 0; I < OpsToMove; ++I) {

2632 }

2637

2638

2639 for (auto [Tie1, Tie2] : TiedOpIndices) {

2640 if (Tie1 >= OpIdx)

2641 Tie1 += Ops.size();

2642 if (Tie2 >= OpIdx)

2643 Tie2 += Ops.size();

2645 }

2646}

2647

2649 assert(OpId && "expected non-zero operand id");

2651

2653 return false;

2654

2656 if (!MD.isImm())

2657 return false;

2658

2660 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())

2661 return F.getRegMayBeFolded();

2662 return false;

2663}

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

Analysis containing CSE Info

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file contains the declarations for the subclasses of Constant, which represent the different fla...

const HexagonInstrInfo * TII

Module.h This file contains the declarations for the Module class.

Implement a low-level type suitable for MachineInstr level instruction selection.

static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

Return the first found DebugLoc that has a DILocation, given a range of instructions.

static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)

Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.

static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)

static const DIExpression * computeExprForSpill(const MachineInstr &MI, const SmallVectorImpl< const MachineOperand * > &SpilledOperands)

Compute the new DIExpression to use with a DBG_VALUE for a spill slot.

static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, BatchAAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)

static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)

static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)

static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)

Check to see if the MMOs pointed to by the two MemRefs arrays are identical.

unsigned const TargetRegisterInfo * TRI

This file provides utility analysis objects describing memory locations.

static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))

This file implements the SmallBitVector class.

This file defines the SmallVector class.

static SymbolRef::Type getType(const Symbol *Sym)

static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)

Returns the opcode of Values or ~0 if they do not all agree.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

ArrayRef< T > slice(size_t N, size_t M) const

slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.

This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...

bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)

ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.

bool isEntryValue() const

Check if the expression consists of exactly one entry value operand.

static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)

Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...

static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)

Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...

static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)

Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...

This class represents an Operation in the Expression.

bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const

bool hasTrivialDestructor() const

Check whether this has a trivial destructor.

Diagnostic information for inline asm reporting.

Utility class for floating point operations which can have information about relaxed accuracy require...

Convenience struct for specifying and reasoning about fast-math flags.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

an instruction for type-safe pointer arithmetic to access elements of arrays and structs

bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override

Check if the instruction or the bundle of instructions has store to stack slots.

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override

Check if the instruction or the bundle of instructions has load from stack slots.

This instruction compares its operands according to the predicate given to the constructor.

static StringRef getMemConstraintName(ConstraintCode C)

constexpr bool isValid() const

This is an important class for using LLVM in a threaded context.

void diagnose(const DiagnosticInfo &DI)

Report a message to the currently installed diagnostic handler.

static LocationSize precise(uint64_t Value)

static constexpr LocationSize beforeOrAfterPointer()

Any location before or after the base pointer (but still within the underlying object).

TypeSize getValue() const

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

unsigned getNumDefs() const

Return the number of MachineOperands that are register definitions.

int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const

Returns the value of the specified operand constraint if it is present.

ArrayRef< MCPhysReg > implicit_defs() const

Return a list of registers that are potentially written by any instance of this machine instruction.

bool isPredicable() const

Return true if this instruction has a predicate operand that controls execution.

bool isVariadic() const

Return true if this instruction can have a variable number of operands.

ArrayRef< MCPhysReg > implicit_uses() const

Return a list of registers that are potentially read by any instance of this machine instruction.

MCRegAliasIterator enumerates all registers aliasing Reg.

bool isSubRegister(MCRegister RegA, MCRegister RegB) const

Returns true if RegB is a sub-register of RegA.

bool isSuperRegister(MCRegister RegA, MCRegister RegB) const

Returns true if RegB is a super-register of RegA.

Wrapper class representing physical registers. Should be passed by value.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

const MDOperand & getOperand(unsigned I) const

unsigned getNumOperands() const

Return number of MDNode operands.

bool isValid() const

isValid - Returns true until all the operands have been visited.

MachineInstr * remove_instr(MachineInstr *I)

Remove the possibly bundled instruction from the instruction list without deleting it.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

instr_iterator erase_instr(MachineInstr *I)

Remove an instruction from the instruction list and delete it.

void printAsOperand(raw_ostream &OS, bool PrintType=true) const

MachineInstr * remove(MachineInstr *I)

Remove the unbundled instruction from the instruction list without deleting it.

void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const

Instructions::iterator instr_iterator

Instructions::const_iterator const_instr_iterator

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isSpillSlotObjectIndex(int ObjectIdx) const

Returns true if the specified index corresponds to a spill slot.

MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0, MDNode *MMRAs=nullptr)

Allocate and construct an extra info structure for a MachineInstr.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

unsigned getNewDebugInstrNum()

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)

Dellocate an array of MachineOperands and recycle the memory.

MachineOperand * allocateOperandArray(OperandCapacity Cap)

Allocate an array of MachineOperands.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addMetadata(const MDNode *MD) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

bool mayRaiseFPException() const

Return true if this instruction could possibly raise a floating-point exception.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)

Mark all subregister defs of register Reg with the undef flag.

static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)

Returns a range of all of the operands that correspond to a debug use of Reg.

bool isDebugValueList() const

void bundleWithPred()

Bundle this instruction with its predecessor.

bool isTerminator(QueryType Type=AnyInBundle) const

Returns true if this instruction part of the terminator for a basic block.

std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const

bool mayLoadOrStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read or modify memory.

void setCFIType(MachineFunction &MF, uint32_t Type)

Set the CFI type for the instruction.

MachineInstr * removeFromParent()

Unlink 'this' from the containing basic block, and return it without deleting it.

iterator_range< mop_iterator > debug_operands()

Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...

const MachineBasicBlock * getParent() const

MDNode * getMMRAMetadata() const

Helper to extract mmra.op metadata.

void bundleWithSucc()

Bundle this instruction with its successor.

uint32_t getCFIType() const

Helper to extract a CFI type hash if one has been added.

bool isDebugLabel() const

void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)

Set a symbol that will be emitted just prior to the instruction itself.

bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...

bool isDereferenceableInvariantLoad() const

Return true if this load instruction never traps and points to a memory location whose value doesn't ...

void setFlags(unsigned flags)

QueryType

API for querying MachineInstr properties.

void addImplicitDefUseOperands(MachineFunction &MF)

Add all implicit def and use operands to this instruction.

std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const

bool isCall(QueryType Type=AnyInBundle) const

std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const

bool getFlag(MIFlag Flag) const

Return whether an MI flag is set.

uint32_t mergeFlagsWith(const MachineInstr &Other) const

Return the MIFlags which represent both MachineInstrs.

const MachineOperand & getDebugExpressionOp() const

Return the operand for the complex address expression referenced by this DBG_VALUE instruction.

std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

If the specified instruction is a PHI that always merges together the same virtual register,...

bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const

Return true if the use operand of the specified index is tied to a def operand.

bool allImplicitDefsAreDead() const

Return true if all the implicit defs of this instruction are dead.

void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)

Clone another MachineInstr's memory reference descriptor list and replace ours with it.

const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const

Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.

bool isSafeToMove(bool &SawStore) const

Return true if it is safe to move this instruction.

bool mayAlias(BatchAAResults *AA, const MachineInstr &Other, bool UseTBAA) const

Returns true if this instruction's memory access aliases the memory access of Other.

bool isDebugInstr() const

unsigned getNumDebugOperands() const

Returns the total number of operands which are debug locations.

unsigned getNumOperands() const

Retuns the total number of operands.

void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

MachineInstr * removeFromBundle()

Unlink this instruction from its basic block and return it without deleting it.

void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const

Print on dbgs() the current instruction and the instructions defining its operands and so on until we...

void copyIRFlags(const Instruction &I)

Copy all flags to MachineInst MIFlags.

bool isDebugValueLike() const

bool memoperands_empty() const

Return true if we don't have any memory operands which described the memory access done by this instr...

mmo_iterator memoperands_end() const

Access to memory operands of the instruction.

void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)

Scan instructions immediately following MI and collect any matching DBG_VALUEs.

std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a restore instruction.

unsigned getOperandNo(const_mop_iterator I) const

Returns the number of the operand iterator I points to.

unsigned getNumExplicitOperands() const

Returns the number of non-implicit operands.

void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)

Assign this MachineInstr's memory reference descriptor list.

bool wouldBeTriviallyDead() const

Return true if this instruction would be trivially dead if all of its defined registers were dead.

bool isBundledWithPred() const

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...

std::tuple< LLT, LLT > getFirst2LLTs() const

std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a folded spill instruction.

void unbundleFromPred()

Break bundle above this instruction.

void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)

Copy implicit register operands from specified instruction to this instruction.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

bool isStackAligningInlineAsm() const

void dropMemRefs(MachineFunction &MF)

Clear this MachineInstr's memory reference descriptor list.

int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const

Returns the operand index that is a use of the specific register or -1 if it is not found.

MDNode * getPCSections() const

Helper to extract PCSections metadata target sections.

bool isCFIInstruction() const

int findFirstPredOperandIdx() const

Find the index of the first operand in the operand list that is used to represent the predicate.

const MCInstrDesc & getDesc() const

Returns the target instruction descriptor of this MachineInstr.

unsigned getBundleSize() const

Return the number of instructions inside the MI bundle, excluding the bundle header.

void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...

bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const

Return true if this is a call instruction that may have an additional information associated with it.

std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const

std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const

unsigned getNumMemOperands() const

Return the number of memory operands.

void clearFlag(MIFlag Flag)

clearFlag - Clear a MI flag.

std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a folded restore instruction.

const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const

Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.

bool isOperandSubregIdx(unsigned OpIdx) const

Return true if operand OpIdx is a subregister index.

InlineAsm::AsmDialect getInlineAsmDialect() const

bool hasUnmodeledSideEffects() const

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...

bool isEquivalentDbgInstr(const MachineInstr &Other) const

Returns true if this instruction is a debug instruction that represents an identical debug value to O...

const DILabel * getDebugLabel() const

Return the debug label referenced by this DBG_LABEL instruction.

void untieRegOperand(unsigned OpIdx)

Break any tie involving OpIdx.

static uint32_t copyFlagsFromInstruction(const Instruction &I)

void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)

Inserts Ops BEFORE It. Can untie/retie tied operands.

void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

bool isJumpTableDebugInfo() const

unsigned getNumExplicitDefs() const

Returns the number of non-implicit definitions.

void eraseFromBundle()

Unlink 'this' from its basic block and delete it.

iterator_range< mop_iterator > operands()

void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)

Set a marker on instructions that denotes where we should create and emit heap alloc site labels.

const DILocalVariable * getDebugVariable() const

Return the debug variable referenced by this DBG_VALUE instruction.

bool hasComplexRegisterTies() const

Return true when an instruction has tied register that can't be determined by the instruction's descr...

LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const

Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.

bool isLifetimeMarker() const

void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)

Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...

unsigned findTiedOperandIdx(unsigned OpIdx) const

Given the index of a tied register operand, find the operand it is tied to.

void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

mmo_iterator memoperands_begin() const

Access to memory operands of the instruction.

void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)

Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.

void changeDebugValuesDefReg(Register Reg)

Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.

bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const

Return true if this instruction is identical to Other.

bool hasOrderedMemoryRef() const

Return true if this instruction may have an ordered or volatile memory reference, or if the informati...

void emitGenericError(const Twine &ErrMsg) const

const MachineFunction * getMF() const

Return the function that contains the basic block that this instruction belongs to.

const DIExpression * getDebugExpression() const

Return the complex address expression referenced by this DBG_VALUE instruction.

ArrayRef< MachineMemOperand * > memoperands() const

Access to memory operands of the instruction.

void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const

Print this MI to OS.

bool isNonListDebugValue() const

bool isLoadFoldBarrier() const

Returns true if it is illegal to fold a load across this instruction.

bool mayStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly modify memory.

void setFlag(MIFlag Flag)

Set a MI flag.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

std::tuple< LLT, LLT, LLT > getFirst3LLTs() const

const MachineOperand & getDebugVariableOp() const

Return the operand for the debug variable referenced by this DBG_VALUE instruction.

void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

void removeOperand(unsigned OpNo)

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

MCSymbol * getPreInstrSymbol() const

Helper to extract a pre-instruction symbol if one has been added.

bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)

Set a symbol that will be emitted just after the instruction itself.

bool isDebugValue() const

const MachineOperand & getDebugOffset() const

Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...

MachineOperand & getDebugOperand(unsigned Index)

std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a spill instruction.

iterator_range< mop_iterator > implicit_operands()

bool isBundledWithSucc() const

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...

void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)

We have determined MI defines a register.

MDNode * getHeapAllocMarker() const

Helper to extract a heap alloc marker if one has been added.

unsigned getDebugInstrNum()

Fetch the instruction number of this MachineInstr.

std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const

void clearRegisterDeads(Register Reg)

Clear all dead flags on operands defining register Reg.

void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)

Clear all kill flags affecting Reg.

const MachineOperand & getOperand(unsigned i) const

void emitInlineAsmError(const Twine &ErrMsg) const

Emit an error referring to the source location of this instruction.

uint32_t getFlags() const

Return the MI flags bitvector.

bool isPseudoProbe() const

bool hasRegisterImplicitUseOperand(Register Reg) const

Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...

bool shouldUpdateAdditionalCallInfo() const

Return true if copying, moving, or erasing this instruction requires updating additional call info (s...

MCSymbol * getPostInstrSymbol() const

Helper to extract a post-instruction symbol if one has been added.

void unbundleFromSucc()

Break bundle below this instruction.

iterator_range< filtered_mop_iterator > all_defs()

Returns an iterator range over all operands that are (explicit or implicit) register defs.

void clearKillInfo()

Clears kill flags on all operands.

bool isDebugEntryValue() const

A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.

bool isIndirectDebugValue() const

A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...

unsigned getNumDefs() const

Returns the total number of definitions.

void setPCSections(MachineFunction &MF, MDNode *MD)

const MDNode * getLocCookieMD() const

For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.

int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const

Returns the operand index that is a def of the specified register or -1 if it is not found.

bool isVariadic(QueryType Type=IgnoreBundle) const

Return true if this instruction can have a variable number of operands.

int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...

bool allDefsAreDead() const

Return true if all the defs of this instruction are dead.

void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)

const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const

Compute the static register class constraint for operand OpIdx.

void moveBefore(MachineInstr *MovePos)

Move the instruction before MovePos.

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

bool mayFoldInlineAsmRegOp(unsigned OpId) const

Returns true if the register operand can be folded with a load or store into a frame index.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

const PseudoSourceValue * getPseudoValue() const

bool isUnordered() const

Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...

AAMDNodes getAAInfo() const

Return the AA tags for the memory reference.

const Value * getValue() const

Return the base address of the memory access.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)

Print a subreg index operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

const MDNode * getMetadata() const

void setIsDead(bool Val=true)

void setMetadata(const MDNode *MD)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

bool isMetadata() const

isMetadata - Tests if this is a MO_Metadata operand.

void setIsKill(bool Val=true)

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...

void setIsEarlyClobber(bool Val=true)

void setIsUndef(bool Val=true)

void setIsDebug(bool Val=true)

getReg - Returns the register number.

bool isIdenticalTo(const MachineOperand &Other) const

Returns true if this operand is identical to the specified operand except for liveness related flags ...

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const

Print the MachineOperand to os.

static void printSymbol(raw_ostream &OS, MCSymbol &Sym)

Print a MCSymbol as an operand.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Representation for a specific memory location.

Manage lifetime of a slot tracker for printing IR.

void incorporateFunction(const Function &F)

Incorporate the given function.

A Module instance is used to store all the information related to an LLVM module.

Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.

An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...

A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.

Instruction that can have a nneg flag (zext/uitofp).

Special value supplied for machine level alias analysis.

virtual bool mayAlias(const MachineFrameInfo *) const

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

void reserve(size_type N)

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)

Get index of next meta operand.

MI-level Statepoint operands.

int getFirstGCPtrIdx()

Get index of first GC pointer operand of -1 if there are none.

TargetInstrInfo - Interface to description of machine instruction set.

TargetIntrinsicInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

MCRegister getSubReg(MCRegister Reg, unsigned Idx) const

Returns the physical register number of sub-register "Index" for physical register RegNo.

bool regsOverlap(Register RegA, Register RegB) const

Returns true if the two registers are equal or alias each other.

virtual const TargetInstrInfo * getInstrInfo() const

This class represents a truncation of integer types.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

A Use represents the edge between a Value definition and its users.

LLVM Value Representation.

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

formatted_raw_ostream & PadToColumn(unsigned NewCol)

PadToColumn - Align the output to some column number.

self_iterator getIterator()

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

hash_code hash_value(const FixedPointSemantics &Val)

formatted_raw_ostream & fdbgs()

fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)

Update a DBG_VALUE whose value has been spilled to FrameIndex.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

OutputIt move(R &&Range, OutputIt Out)

Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.

MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)

Clone a DBG_VALUE whose value has been spilled to FrameIndex.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)

Compute a hash_code for a sequence of values.

Implement std::hash so that hash_code can be used in STL containers.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

static unsigned getHashValue(const MachineInstr *const &MI)