MachineInstr.cpp Source File (original) (raw)

58#include

59#include

60#include

61#include

62#include

64using namespace llvm;

68 cl::desc("Print addresses of MachineInstrs when dumping"));

73 return MF;

74 return nullptr;

75}

84 TRI = MF->getSubtarget().getRegisterInfo();

85 MRI = &MF->getRegInfo();

86 TII = MF->getSubtarget().getInstrInfo();

87 }

88}

91 for (MCPhysReg ImpDef : MCID->implicit_defs())

93 for (MCPhysReg ImpUse : MCID->implicit_uses())

95}

102 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),

103 DbgLoc(std::move(DL)), DebugInstrNum(0), Opcode(TID.Opcode) {

105

106

107 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +

108 MCID->implicit_uses().size()) {

111 }

112

113 if (!NoImp)

115}

116

117

118

119

124 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");

125

128

129

130 for (const MachineOperand &MO : MI.operands())

132

133

134

136 MachineOperand &NewMO = getOperand(i);

137 const MachineOperand &OrigMO = MI.getOperand(i);

138 NewMO.TiedTo = OrigMO.TiedTo;

139 }

140

141

143}

144

151

155

156

157

158

161 return &MBB->getParent()->getRegInfo();

162 return nullptr;

163}

164

167 return &MBB->getParent()->getRegInfo();

168 return nullptr;

169}

170

172 for (MachineOperand &MO : operands())

173 if (MO.isReg())

174 MRI.removeRegOperandFromUseList(&MO);

175}

176

178 for (MachineOperand &MO : operands())

179 if (MO.isReg())

180 MRI.addRegOperandToUseList(&MO);

181}

182

185 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");

187 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");

189}

190

191

192

196 return MRI->moveOperands(Dst, Src, NumOps);

197

198 assert(Dst && Src && "Unknown operands");

200}

201

202

203

204

205

208 "Cannot add more operands.");

209 assert(MCID && "Cannot add operands before providing an instr descriptor");

210

211

212 if (&Op >= Operands && &Op < Operands + NumOperands) {

213

214

215

218 }

219

220

221

222

223

224

225

226

228 bool isImpReg = Op.isReg() && Op.isImplicit();

230 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {

231 --OpNo;

232 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");

233 }

234 }

235

236

237

238

240

241

242

243 OperandCapacity OldCap = CapOperands;

246 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);

248

249 if (OpNo)

251 }

252

253

254 if (OpNo != NumOperands)

255 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,

257 ++NumOperands;

258

259

260 if (OldOperands != Operands && OldOperands)

262

263

265 NewMO->ParentMI = this;

266

267

268 if (NewMO->isReg()) {

269

270 NewMO->Contents.Reg.Prev = nullptr;

271

272 NewMO->TiedTo = 0;

273

275 MRI->addRegOperandToUseList(NewMO);

276

277

278

279 if (!isImpReg) {

280

281 if (NewMO->isUse()) {

282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);

283 if (DefIdx != -1)

285 }

286

289 }

290

293 }

294}

295

299

300#ifndef NDEBUG

301

302 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)

303 if (Operands[i].isReg())

304 assert(!Operands[i].isTied() && "Cannot move tied operands");

305#endif

306

308 if (MRI && Operands[OpNo].isReg())

309 MRI->removeRegOperandFromUseList(Operands + OpNo);

310

311

312

313

314

315 if (unsigned N = NumOperands - 1 - OpNo)

317 --NumOperands;

318}

319

326 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;

327 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;

328 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;

329 bool HasPCSections = PCSections != nullptr;

330 bool HasCFIType = CFIType != 0;

331 bool HasMMRAs = MMRAs != nullptr;

332 bool HasDS = DS != nullptr;

333 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +

334 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs +

335 HasDS;

336

337

338 if (NumPointers <= 0) {

339 Info.clear();

340 return;

341 }

342

343

344

345

346

347 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||

348 HasCFIType || HasDS) {

349 Info.set<EIIK_OutOfLine>(

351 HeapAllocMarker, PCSections, CFIType, MMRAs, DS));

352 return;

353 }

354

355

356 if (HasPreInstrSymbol)

357 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);

358 else if (HasPostInstrSymbol)

359 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);

360 else

361 Info.set<EIIK_MMO>(MMOs[0]);

362}

363

372

375 if (MMOs.empty()) {

377 return;

378 }

379

383}

384

392

394 if (this == &MI)

395

396 return;

397

399 "Invalid machine functions when cloning memory refrences!");

400

401

402

407 MI.getMMRAMetadata()) {

408 Info = MI.Info;

409 return;

410 }

411

412

414}

415

416

417

420 if (LHS.size() != RHS.size())

421 return false;

422

425 return std::equal(LHSPointees.begin(), LHSPointees.end(),

426 RHSPointees.begin());

427}

428

431

432 if (MIs.empty()) {

434 return;

435 }

436 if (MIs.size() == 1) {

438 return;

439 }

440

441

442

445 return;

446 }

447

448

450

452 "Invalid machine functions when cloning memory references!");

454

457 "Invalid machine functions when cloning memory references!");

458

459

460

461

463 continue;

464

465

466

467

468 if (MI.memoperands_empty()) {

470 return;

471 }

472

473

474 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());

475 }

476

478}

479

481

483 return;

484

485

486 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {

487 Info.clear();

488 return;

489 }

490

494}

495

497

499 return;

500

501

502 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {

503 Info.clear();

504 return;

505 }

506

510}

511

521

531

541

551

561

563 const MachineInstr &MI) {

564 if (this == &MI)

565

566 return;

567

569 "Invalid machine functions when cloning instruction symbols!");

570

576}

577

583

586

589 if (OB->hasNoSignedWrap())

591 if (OB->hasNoUnsignedWrap())

594 if (TI->hasNoSignedWrap())

596 if (TI->hasNoUnsignedWrap())

599 if (GEP->hasNoUnsignedSignedWrap())

601 if (GEP->hasNoUnsignedWrap())

603 if (GEP->isInBounds())

605 }

606

607

609 if (PNI->hasNonNeg())

611

614 if (PD->isDisjoint())

616 }

617

618

620 if (ICmp->hasSameSign())

622

623

625 if (PE->isExact())

627

628

631 if (Flags.noNaNs())

633 if (Flags.noInfs())

635 if (Flags.noSignedZeros())

637 if (Flags.allowReciprocal())

639 if (Flags.allowContract())

641 if (Flags.approxFunc())

643 if (Flags.allowReassoc())

645 }

646

647 if (I.getMetadata(LLVMContext::MD_unpredictable))

649

650 return MIFlags;

651}

652

656

657bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {

660 if (MII->getDesc().getFlags() & Mask) {

662 return true;

663 } else {

665 return false;

666 }

667

668 if (!MII->isBundledWithSucc())

670 }

671}

672

675

676

679 return false;

680

682

683

684

685 assert(Other.isBundle() && "Expected that both instructions are bundles.");

688

689

690 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {

691 ++I1;

692 ++I2;

693 if (!I1->isIdenticalTo(*I2, Check))

694 return false;

695 }

696

697

698 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())

699 return false;

700 }

701

702

703 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

706 if (!MO.isReg()) {

708 return false;

709 continue;

710 }

711

712

713

714

715 if (MO.isDef()) {

717 continue;

721 return false;

722 } else {

724 return false;

726 return false;

727 }

728 } else {

730 return false;

732 return false;

733 }

734 }

735

739 return false;

740

741

744 return false;

745

747 return false;

749 return false;

750

751 return true;

752}

753

756 return false;

758 return false;

760 return false;

762 return false;

765 return false;

768 Other.getDebugExpression(), Other.isIndirectDebugValue()))

769 return false;

770 return true;

771}

772

776

781

786

791

796

799 return false;

801 case TargetOpcode::PATCHPOINT:

802 case TargetOpcode::STACKMAP:

803 case TargetOpcode::STATEPOINT:

804 case TargetOpcode::FENTRY_CALL:

805 return false;

806 }

807 return true;

808}

809

815

816template <typename Operand, typename Instruction>

820 std::function<bool(Operand & Op)> OpUsesReg(

821 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });

823}

824

831

837

839 unsigned NumOperands = MCID->getNumOperands();

840 if (!MCID->isVariadic())

841 return NumOperands;

842

843 for (const MachineOperand &MO : operands_impl().drop_front(NumOperands)) {

844

845

846

847

848

849 if (MO.isReg() && MO.isImplicit())

850 break;

851 ++NumOperands;

852 }

853 return NumOperands;

854}

855

857 unsigned NumDefs = MCID->getNumDefs();

858 if (!MCID->isVariadic())

859 return NumDefs;

860

861 for (const MachineOperand &MO : operands_impl().drop_front(NumDefs)) {

862 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())

863 break;

864 ++NumDefs;

865 }

866 return NumDefs;

867}

868

873 --Pred;

874 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");

876}

877

882 ++Succ;

883 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");

885}

886

891 --Pred;

892 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");

894}

895

900 ++Succ;

901 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");

903}

904

909 return true;

910 }

911 return false;

912}

913

915 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");

918}

919

921 unsigned *GroupNo) const {

924

925

927 return -1;

928

929 unsigned Group = 0;

934

935 if (!FlagMO.isImm())

936 return -1;

938 NumOps = 1 + F.getNumOperandRegisters();

940 if (GroupNo)

941 *GroupNo = Group;

942 return i;

943 }

944 ++Group;

945 }

946 return -1;

947}

948

953

959

965

969

975

981

985

989

994 assert(getParent() && "Can't have an MBB reference here!");

995 assert(getMF() && "Can't have an MF reference here!");

996

999

1001 return nullptr;

1002

1003

1004 unsigned DefIdx;

1007

1008

1010 if (FlagIdx < 0)

1011 return nullptr;

1012

1014 unsigned RCID;

1015 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&

1016 F.hasRegClassConstraint(RCID))

1017 return TRI->getRegClass(RCID);

1018

1019

1020 if (F.isMemKind())

1021 return TRI->getPointerRegClass();

1022

1023 return nullptr;

1024}

1025

1029

1030

1031 if (ExploreBundle)

1033 ++OpndIt)

1034 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(

1035 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);

1036 else

1037

1038 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)

1039 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);

1040 return CurRC;

1041}

1042

1043const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(

1046 assert(CurRC && "Invalid initial register class");

1047

1050 return CurRC;

1051

1053}

1054

1061 "Cannot get register constraints for non-register operand");

1062 assert(CurRC && "Invalid initial register class");

1063 if (unsigned SubIdx = MO.getSubReg()) {

1064 if (OpRC)

1065 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);

1066 else

1067 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);

1068 } else if (OpRC)

1069 CurRC = TRI->getCommonSubClass(CurRC, OpRC);

1070 return CurRC;

1071}

1072

1073

1074

1077 unsigned Size = 0;

1078 while (I->isBundledWithSucc()) {

1080 ++I;

1081 }

1082 return Size;

1083}

1084

1085

1086

1090 return true;

1091 }

1092 return false;

1093}

1094

1095

1096

1097

1100 bool isKill) const {

1101 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1104 continue;

1106 if (!MOReg)

1107 continue;

1108 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))

1110 return i;

1111 }

1112 return -1;

1113}

1114

1115

1116

1117

1118std::pair<bool,bool>

1121 bool PartDef = false;

1122 bool FullDef = false;

1123 bool Use = false;

1124

1125 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1128 continue;

1129 if (Ops)

1130 Ops->push_back(i);

1134

1135 PartDef = true;

1136 else

1137 FullDef = true;

1138 }

1139

1140 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);

1141}

1142

1143

1144

1145

1146

1149 bool isDead, bool Overlap) const {

1150 bool isPhys = Reg.isPhysical();

1151 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

1153

1154

1156 return i;

1158 continue;

1160 bool Found = (MOReg == Reg);

1161 if (!Found && TRI && isPhys && MOReg.isPhysical()) {

1162 if (Overlap)

1163 Found = TRI->regsOverlap(MOReg, Reg);

1164 else

1165 Found = TRI->isSubRegister(MOReg, Reg);

1166 }

1168 return i;

1169 }

1170 return -1;

1171}

1172

1173

1174

1175

1177

1178

1179

1180

1182 if (MCID.isPredicable()) {

1183 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)

1184 if (MCID.operands()[i].isPredicate())

1185 return i;

1186 }

1187

1188 return -1;

1189}

1190

1191

1193

1194

1195

1196

1197

1198

1199

1200

1201

1202

1203

1204

1205

1209 assert(DefMO.isDef() && "DefIdx must be a def operand");

1210 assert(UseMO.isUse() && "UseIdx must be a use operand");

1211 assert(!DefMO.isTied() && "Def is already tied to another use");

1212 assert(!UseMO.isTied() && "Use is already tied to another def");

1213

1215 UseMO.TiedTo = DefIdx + 1;

1216 } else {

1217

1218

1219

1220

1222 "DefIdx out of range");

1224 }

1225

1226

1227 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);

1228}

1229

1230

1231

1232

1235 assert(MO.isTied() && "Operand isn't tied");

1236

1237

1238 if (MO.TiedTo < TiedMax)

1239 return MO.TiedTo - 1;

1240

1241

1243

1246

1249 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)

1250 return i;

1251 }

1253 }

1254

1255 if (getOpcode() == TargetOpcode::STATEPOINT) {

1256

1257

1260 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");

1262 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {

1265 if (OpIdx == CurDefIdx)

1266 return CurUseIdx;

1267 if (OpIdx == CurUseIdx)

1268 return CurDefIdx;

1270 }

1272 }

1273

1274

1275

1277 unsigned OpIdxGroup = ~0u;

1282 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");

1283 unsigned CurGroup = GroupIdx.size();

1286 NumOps = 1 + F.getNumOperandRegisters();

1287

1289 OpIdxGroup = CurGroup;

1290 unsigned TiedGroup;

1291 if (.isUseOperandTiedToDef(TiedGroup))

1292 continue;

1293

1294

1295 unsigned Delta = i - GroupIdx[TiedGroup];

1296

1297

1298 if (OpIdxGroup == CurGroup)

1299 return OpIdx - Delta;

1300

1301

1302 if (OpIdxGroup == TiedGroup)

1303 return OpIdx + Delta;

1304 }

1306}

1307

1308

1309

1316

1318 unsigned SubIdx,

1321 if (SubIdx)

1322 ToReg = RegInfo.getSubReg(ToReg, SubIdx);

1324 if (!MO.isReg() || MO.getReg() != FromReg)

1325 continue;

1327 }

1328 } else {

1330 if (!MO.isReg() || MO.getReg() != FromReg)

1331 continue;

1333 }

1334 }

1335}

1336

1337

1338

1339

1341

1342

1343

1344

1345

1348 SawStore = true;

1349 return false;

1350 }

1351

1352

1353

1356 return false;

1357

1358

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1369

1372 return false;

1373

1374

1375

1376

1377

1378

1380

1381

1382 return !SawStore;

1383

1384 return true;

1385}

1386

1388

1389

1390 if (getOpcode() == TargetOpcode::LOCAL_ESCAPE)

1391 return false;

1392

1393

1394

1396 return false;

1397

1398

1399

1401 return false;

1402

1403

1404

1405 bool SawStore = false;

1407}

1408

1411

1412

1413

1416 if (Reg.isPhysical()) {

1417

1419 return false;

1420 } else {

1422 continue;

1423 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Reg)) {

1424 if (&Use != this)

1425

1426 return false;

1427 }

1428 }

1429 }

1430

1431

1432

1433

1435 return false;

1436

1437

1439 return true;

1440

1441

1442

1444}

1445

1450

1451

1452

1453

1454

1455

1456

1457

1458

1459

1460

1461

1462

1463 int64_t OffsetA = MMOa->getOffset();

1464 int64_t OffsetB = MMOb->getOffset();

1465 int64_t MinOffset = std::min(OffsetA, OffsetB);

1466

1469 bool KnownWidthA = WidthA.hasValue();

1470 bool KnownWidthB = WidthB.hasValue();

1472

1475 bool SameVal = (ValA && ValB && (ValA == ValB));

1476 if (!SameVal) {

1479 if (PSVa && ValB && !PSVa->mayAlias(&MFI))

1480 return false;

1481 if (PSVb && ValA && !PSVb->mayAlias(&MFI))

1482 return false;

1483 if (PSVa && PSVb && (PSVa == PSVb))

1484 SameVal = true;

1485 }

1486

1487 if (SameVal && BothMMONonScalable) {

1488 if (!KnownWidthA || !KnownWidthB)

1489 return true;

1490 int64_t MaxOffset = std::max(OffsetA, OffsetB);

1491 int64_t LowWidth = (MinOffset == OffsetA)

1494 return (MinOffset + LowWidth > MaxOffset);

1495 }

1496

1497 if ()

1498 return true;

1499

1500 if (!ValA || !ValB)

1501 return true;

1502

1503 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");

1504 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");

1505

1506

1507

1508 if ((WidthA.isScalable() && OffsetA > 0) ||

1509 (WidthB.isScalable() && OffsetB > 0))

1510 return true;

1511

1512 int64_t OverlapA =

1515 int64_t OverlapB =

1518

1520 ? WidthA

1523 ? WidthB

1525

1526 return ->isNoAlias(

1529}

1530

1536

1537

1538

1540 return true;

1541

1542

1543

1545 return false;

1546

1547

1549 return false;

1550

1551

1552 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))

1553 return false;

1554

1555

1556

1558 return true;

1559

1560

1562 if (NumChecks > TII->getMemOperandAACheckLimit())

1563 return true;

1564

1565

1566

1568 for (auto *MMOb : Other.memoperands()) {

1569 if (!MMOa->isStore() && !MMOb->isStore())

1570 continue;

1572 return true;

1573 }

1574 }

1575

1576 return false;

1577}

1578

1581 if (AA) {

1584 }

1586}

1587

1588

1589

1590

1591

1593

1598 return false;

1599

1600

1601

1603 return true;

1604

1605

1608 });

1609}

1610

1611

1612

1613

1615

1617 return false;

1618

1619

1620

1622 return false;

1623

1625

1627 if (!MMO->isUnordered())

1628

1629

1630

1631 return false;

1632 if (MMO->isStore()) return false;

1633 if (MMO->isInvariant() && MMO->isDereferenceable())

1634 continue;

1635

1636

1638 if (PSV->isConstant(&MFI))

1639 continue;

1640 }

1641

1642

1643 return false;

1644 }

1645

1646

1647 return true;

1648}

1649

1652 return {};

1654 "It's illegal to have a PHI without source operands");

1655

1657 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)

1659 return {};

1660 return Reg;

1661}

1662

1665 return true;

1669 return true;

1670 }

1671

1672 return false;

1673}

1674

1679

1680

1681

1685 continue;

1687 return false;

1688 }

1689 return true;

1690}

1691

1695 continue;

1697 return false;

1698 }

1699 return true;

1700}

1701

1702

1703

1705 const MachineInstr &MI) {

1710}

1711

1714 if (MCID.Opcode == TargetOpcode::STATEPOINT)

1715 return true;

1718 if (!Operand.isReg() || Operand.isDef())

1719

1720 continue;

1721 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);

1723 if (ExpectedTiedIdx != TiedIdx)

1724 return true;

1725 }

1726 return false;

1727}

1728

1732 if (.isReg())

1733 return LLT{};

1734

1736 return MRI.getType(Op.getReg());

1737

1739 if (!OpInfo.isGenericType())

1740 return MRI.getType(Op.getReg());

1741

1742 if (PrintedTypes[OpInfo.getGenericTypeIndex()])

1743 return LLT{};

1744

1745 LLT TypeToPrint = MRI.getType(Op.getReg());

1746

1747

1748 if (TypeToPrint.isValid())

1749 PrintedTypes.set(OpInfo.getGenericTypeIndex());

1750 return TypeToPrint;

1751}

1752

1753#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

1755 dbgs() << " ";

1757}

1758

1762 if (Depth >= MaxDepth)

1763 return;

1764 if (!AlreadySeenInstrs.insert(this).second)

1765 return;

1766

1767

1773 continue;

1775 if (Reg.isPhysical())

1776 continue;

1778 if (NewMI == nullptr)

1779 continue;

1780 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);

1781 }

1782}

1783

1785 unsigned MaxDepth) const {

1787 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);

1788}

1789#endif

1790

1792 bool SkipDebugLoc, bool AddNewLine,

1794 const Module *M = nullptr;

1798 M = F->getParent();

1799 if ( TII )

1801 }

1802

1804 if (F)

1806 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);

1807}

1808

1810 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,

1812

1816

1819

1822 auto getTiedOperandIdx = [&](unsigned OpIdx) {

1823 if (!ShouldPrintRegisterTies)

1824 return 0U;

1828 return 0U;

1829 };

1830 unsigned StartOp = 0;

1832

1833

1834 while (StartOp < e) {

1837 break;

1838

1839 if (StartOp != 0)

1840 OS << ", ";

1841

1843 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);

1844 MO.print(OS, MST, TypeToPrint, StartOp, false, IsStandalone,

1845 ShouldPrintRegisterTies, TiedOperandIdx, TRI);

1846 ++StartOp;

1847 }

1848

1849 if (StartOp != 0)

1850 OS << " = ";

1851

1853 OS << "frame-setup ";

1855 OS << "frame-destroy ";

1857 OS << "nnan ";

1859 OS << "ninf ";

1861 OS << "nsz ";

1863 OS << "arcp ";

1865 OS << "contract ";

1867 OS << "afn ";

1869 OS << "reassoc ";

1871 OS << "nuw ";

1873 OS << "nsw ";

1875 OS << "exact ";

1877 OS << "nofpexcept ";

1879 OS << "nomerge ";

1881 OS << "nneg ";

1883 OS << "disjoint ";

1885 OS << "nusw ";

1887 OS << "samesign ";

1889 OS << "inbounds ";

1890

1891

1892 if (TII)

1894 else

1895 OS << "UNKNOWN";

1896

1897 if (SkipOpers)

1898 return;

1899

1900

1901 bool FirstOp = true;

1902 unsigned AsmDescOp = ~0u;

1903 unsigned AsmOpCount = 0;

1904

1906

1907 OS << " ";

1910 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);

1912 IsStandalone, ShouldPrintRegisterTies,

1913 TiedOperandIdx, TRI);

1914

1915

1918 OS << " [sideeffect]";

1920 OS << " [mayload]";

1922 OS << " [maystore]";

1924 OS << " [isconvergent]";

1926 OS << " [alignstack]";

1928 OS << " [attdialect]";

1930 OS << " [inteldialect]";

1931

1933 FirstOp = false;

1934 }

1935

1936 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {

1938

1939 if (FirstOp) FirstOp = false; else OS << ",";

1940 OS << " ";

1941

1943

1945 if (DIV && !DIV->getName().empty())

1946 OS << "!\"" << DIV->getName() << '\"';

1947 else {

1949 unsigned TiedOperandIdx = getTiedOperandIdx(i);

1950 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

1951 ShouldPrintRegisterTies, TiedOperandIdx, TRI);

1952 }

1954

1956 if (DIL && !DIL->getName().empty())

1957 OS << "\"" << DIL->getName() << '\"';

1958 else {

1960 unsigned TiedOperandIdx = getTiedOperandIdx(i);

1961 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

1962 ShouldPrintRegisterTies, TiedOperandIdx, TRI);

1963 }

1964 } else if (i == AsmDescOp && MO.isImm()) {

1965

1966 OS << '$' << AsmOpCount++;

1967 unsigned Flag = MO.getImm();

1969 OS << ":[";

1970 OS << F.getKindName();

1971

1972 unsigned RCID;

1973 if (.isImmKind() && .isMemKind() && F.hasRegClassConstraint(RCID)) {

1974 if (TRI) {

1975 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));

1976 } else

1977 OS << ":RC" << RCID;

1978 }

1979

1980 if (F.isMemKind()) {

1983 }

1984

1985 unsigned TiedTo;

1986 if (F.isUseOperandTiedToDef(TiedTo))

1987 OS << " tiedto:$" << TiedTo;

1988

1989 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||

1990 F.isRegUseKind()) &&

1991 F.getRegMayBeFolded()) {

1992 OS << " foldable";

1993 }

1994

1995 OS << ']';

1996

1997

1998 AsmDescOp += 1 + F.getNumOperandRegisters();

1999 } else {

2001 unsigned TiedOperandIdx = getTiedOperandIdx(i);

2004 else

2005 MO.print(OS, MST, TypeToPrint, i, true, IsStandalone,

2006 ShouldPrintRegisterTies, TiedOperandIdx, TRI);

2007 }

2008 }

2009

2010

2011

2013 if (!FirstOp) {

2014 FirstOp = false;

2015 OS << ',';

2016 }

2017 OS << " pre-instr-symbol ";

2019 }

2021 if (!FirstOp) {

2022 FirstOp = false;

2023 OS << ',';

2024 }

2025 OS << " post-instr-symbol ";

2027 }

2029 if (!FirstOp) {

2030 FirstOp = false;

2031 OS << ',';

2032 }

2033 OS << " heap-alloc-marker ";

2035 }

2037 if (!FirstOp) {

2038 FirstOp = false;

2039 OS << ',';

2040 }

2041 OS << " pcsections ";

2043 }

2045 if (!FirstOp) {

2046 FirstOp = false;

2047 OS << ',';

2048 }

2049 OS << " mmra ";

2050 MMRA->printAsOperand(OS, MST);

2051 }

2053 if (!FirstOp)

2054 OS << ',';

2055 OS << " cfi-type " << CFIType;

2056 }

2059

2060 if (DebugInstrNum) {

2061 if (!FirstOp)

2062 OS << ",";

2063 OS << " debug-instr-number " << DebugInstrNum;

2064 }

2065

2066 if (!SkipDebugLoc) {

2068 if (!FirstOp)

2069 OS << ',';

2070 OS << " debug-location ";

2071 DL->printAsOperand(OS, MST);

2072 }

2073 }

2074

2078 std::unique_ptr CtxPtr;

2083 } else {

2084 CtxPtr = std::make_unique();

2085 Context = CtxPtr.get();

2086 }

2087

2088 OS << " :: ";

2089 bool NeedComma = false;

2091 if (NeedComma)

2092 OS << ", ";

2093 Op->print(OS, MST, SSNs, *Context, MFI, TII);

2094 NeedComma = true;

2095 }

2096 }

2097

2098 if (SkipDebugLoc)

2099 return;

2100

2101 bool HaveSemi = false;

2102

2103

2105 if (!HaveSemi) {

2106 OS << ';';

2107 HaveSemi = true;

2108 }

2109 OS << ' ';

2110 DL.print(OS);

2111 }

2112

2113

2118 if (!HaveSemi) {

2119 OS << ";";

2120 HaveSemi = true;

2121 }

2123 OS << " line no:" << DV->getLine();

2125 OS << " indirect";

2126 }

2127 }

2128

2129

2131 OS << " ; " << this;

2132

2133 if (AddNewLine)

2134 OS << '\n';

2135}

2136

2139 bool AddIfNotFound) {

2140 bool isPhysReg = IncomingReg.isPhysical();

2141 bool hasAliases = isPhysReg &&

2143 bool Found = false;

2145 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

2148 continue;

2149

2150

2151

2152

2154 continue;

2155

2157 if (!Reg)

2158 continue;

2159

2160 if (Reg == IncomingReg) {

2161 if (!Found) {

2163

2164 return true;

2166

2167 return true;

2169 Found = true;

2170 }

2171 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {

2172

2173 if (RegInfo->isSuperRegister(IncomingReg, Reg))

2174 return true;

2175 if (RegInfo->isSubRegister(IncomingReg, Reg))

2177 }

2178 }

2179

2180

2181 while (!DeadOps.empty()) {

2182 unsigned OpIdx = DeadOps.back();

2186 else

2189 }

2190

2191

2192

2193 if (!Found && AddIfNotFound) {

2195 false ,

2196 true ,

2197 true ));

2198 return true;

2199 }

2200 return Found;

2201}

2202

2205 if (!Reg.isPhysical())

2206 RegInfo = nullptr;

2209 continue;

2211 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)

2213 }

2214}

2215

2218 bool AddIfNotFound) {

2219 bool isPhysReg = Reg.isPhysical();

2220 bool hasAliases = isPhysReg &&

2222 bool Found = false;

2224 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {

2227 continue;

2229 if (!MOReg)

2230 continue;

2231

2232 if (MOReg == Reg) {

2234 Found = true;

2235 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {

2236

2237 if (RegInfo->isSuperRegister(Reg, MOReg))

2238 return true;

2239 if (RegInfo->isSubRegister(Reg, MOReg))

2241 }

2242 }

2243

2244

2245 while (!DeadOps.empty()) {

2246 unsigned OpIdx = DeadOps.back();

2250 else

2253 }

2254

2255

2256

2257 if (Found || !AddIfNotFound)

2258 return Found;

2259

2261 true ,

2262 true ,

2263 false ,

2264 true ));

2265 return true;

2266}

2267

2270 if (MO.getReg() == Reg)

2272}

2273

2279

2282 if (Reg.isPhysical()) {

2284 if (MO)

2285 return;

2286 } else {

2289 return;

2290 }

2291 }

2293 true ,

2294 true ));

2295}

2296

2299 bool HasRegMask = false;

2302 HasRegMask = true;

2303 continue;

2304 }

2305 if (!MO.isReg() || !MO.isDef()) continue;

2307 if (!Reg.isPhysical())

2308 continue;

2309

2313 }

2314

2315

2316

2317 if (HasRegMask)

2318 for (const Register &UsedReg : UsedRegs)

2320}

2321

2322unsigned

2324

2326 HashComponents.reserve(MI->getNumOperands() + 1);

2327 HashComponents.push_back(MI->getOpcode());

2330 continue;

2331

2333 }

2335}

2336

2338

2339 const MDNode *LocMD = nullptr;

2342 (LocMD = getOperand(i-1).getMetadata()) &&

2345 return LocMD;

2346 }

2347 }

2348

2349 return nullptr;

2350}

2351

2356 LocMD

2358 : 0;

2361}

2362

2368

2372 const MDNode *Expr) {

2376 "Expected inlined-at fields to agree");

2378 if (IsIndirect)

2380 else

2383}

2384

2388 const MDNode *Variable, const MDNode *Expr) {

2392 "Expected inlined-at fields to agree");

2393 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {

2395 "DBG_VALUE must contain exactly one debug operand");

2397 if (DebugOp.isReg())

2399 Expr);

2400

2402 if (IsIndirect)

2404 else

2407 }

2408

2410 MIB.addMetadata(Variable).addMetadata(Expr);

2412 if (DebugOp.isReg())

2413 MIB.addReg(DebugOp.getReg());

2414 else

2415 MIB.add(DebugOp);

2416 return MIB;

2417}

2418

2429

2433 bool IsIndirect,

2435 const MDNode *Variable, const MDNode *Expr) {

2438 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);

2441}

2442

2443

2444

2448 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&

2449 "Expected inlined-at fields to agree");

2450

2452 if (MI.isIndirectDebugValue()) {

2453 assert(MI.getDebugOffset().getImm() == 0 &&

2454 "DBG_VALUE with nonzero offset");

2456 } else if (MI.isDebugValueList()) {

2457

2458

2459 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};

2461 unsigned OpIdx = MI.getDebugOperandIndex(Op);

2463 }

2464 }

2465 return Expr;

2466}

2469 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");

2473}

2474

2478 int FrameIndex, Register SpillReg) {

2480 "DBG_INSTR_REF should not reference a virtual register.");

2484

2485

2491 if (Op.isReg() && Op.getReg() == SpillReg)

2493 else

2495 }

2496 return NewMI;

2497}

2505

2506

2514 else

2516 }

2517 return NewMI;

2518}

2519

2526 Op.ChangeToFrameIndex(FrameIndex);

2528}

2529

2532 MachineInstr &MI = *this;

2533 if (.getOperand(0).isReg())

2534 return;

2535

2538 DI != DE; ++DI) {

2539 if (!DI->isDebugValue())

2540 return;

2541 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))

2543 }

2544}

2545

2547

2549

2551 return;

2552

2554 auto *MRI = getRegInfo();

2555 for (auto &MO : MRI->use_operands(DefReg)) {

2557 if (!DI->isDebugValue())

2558 continue;

2559 if (DI->hasDebugOperandForReg(DefReg)) {

2561 }

2562 }

2563

2564

2565 for (auto *DBI : DbgValues)

2566 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))

2567 Op.setReg(Reg);

2568}

2569

2571

2574 std::optional Size;

2575 for (const auto *A : Accesses) {

2578 ->getFrameIndex())) {

2584 else

2586 }

2587 }

2591}

2592

2593std::optional

2595 int FI;

2596 if (TII->isStoreToStackSlotPostFE(*this, FI)) {

2600 }

2601 return std::nullopt;

2602}

2603

2604std::optional

2607 if (TII->hasStoreToStackSlot(*this, Accesses))

2609 return std::nullopt;

2610}

2611

2612std::optional

2614 int FI;

2615 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {

2619 }

2620 return std::nullopt;

2621}

2622

2623std::optional

2626 if (TII->hasLoadFromStackSlot(*this, Accesses))

2628 return std::nullopt;

2629}

2630

2632 if (DebugInstrNum == 0)

2634 return DebugInstrNum;

2635}

2636

2638 if (DebugInstrNum == 0)

2640 return DebugInstrNum;

2641}

2642

2647

2653

2660

2668

2669std::tuple<Register, LLT, Register, LLT>

2673 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,

2674 getRegInfo()->getType(Reg1));

2675}

2676

2677std::tuple<Register, LLT, Register, LLT, Register, LLT>

2682 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,

2683 getRegInfo()->getType(Reg1), Reg2,

2684 getRegInfo()->getType(Reg2));

2685}

2686

2687std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>

2693 return std::tuple(

2694 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),

2695 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));

2696}

2697

2706 return std::tuple(

2707 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),

2708 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),

2709 Reg4, getRegInfo()->getType(Reg4));

2710}

2711

2714 assert(InsertBefore != nullptr && "invalid iterator");

2716 "iterator points to operand of other inst");

2717 if (Ops.empty())

2718 return;

2719

2720

2726 TiedOpIndices[OpNo] = TiedTo;

2728 }

2729 }

2730

2733 unsigned OpsToMove = NumOperands - OpIdx;

2734

2736 MovingOps.reserve(OpsToMove);

2737

2738 for (unsigned I = 0; I < OpsToMove; ++I) {

2741 }

2746

2747

2748 for (auto [Tie1, Tie2] : TiedOpIndices) {

2749 if (Tie1 >= OpIdx)

2750 Tie1 += Ops.size();

2751 if (Tie2 >= OpIdx)

2752 Tie2 += Ops.size();

2754 }

2755}

2756

2758 assert(OpId && "expected non-zero operand id");

2760

2762 return false;

2763

2765 if (!MD.isImm())

2766 return false;

2767

2769 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())

2770 return F.getRegMayBeFolded();

2771 return false;

2772}

2773

2776

2777

2778 unsigned RemovedCount = 0;

2783 RemovedCount += 2;

2784 }

2785 }

2786 return RemovedCount;

2787}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

Analysis containing CSE Info

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file contains the declarations for the subclasses of Constant, which represent the different fla...

DXIL Forward Handle Accesses

Module.h This file contains the declarations for the Module class.

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Implement a low-level type suitable for MachineInstr level instruction selection.

static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

Return the first DebugLoc that has line number information, given a range of instructions.

const unsigned TiedMax

Definition MachineInstr.cpp:1192

static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)

Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.

Definition MachineInstr.cpp:193

static cl::opt< bool > PrintMIAddrs("print-mi-addrs", cl::Hidden, cl::desc("Print addresses of MachineInstrs when dumping"))

static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)

Definition MachineInstr.cpp:2572

static const DIExpression * computeExprForSpill(const MachineInstr &MI, const SmallVectorImpl< const MachineOperand * > &SpilledOperands)

Compute the new DIExpression to use with a DBG_VALUE for a spill slot.

Definition MachineInstr.cpp:2445

static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, BatchAAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)

Definition MachineInstr.cpp:1446

static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForRegHelper(Instruction *MI, Register Reg)

Definition MachineInstr.cpp:819

SmallVector< const MachineMemOperand *, 2 > MMOList

Definition MachineInstr.cpp:2570

static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetInstrInfo *&TII)

Definition MachineInstr.cpp:78

static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)

Definition MachineInstr.cpp:70

static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)

Check to see if the MMOs pointed to by the two MemRefs arrays are identical.

Definition MachineInstr.cpp:418

This file provides utility analysis objects describing memory locations.

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

MachineInstr unsigned OpIdx

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))

This file implements the SmallBitVector class.

This file defines the SmallVector class.

static SymbolRef::Type getType(const Symbol *Sym)

static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)

Returns the opcode of Values or ~0 if they do not all agree.

Capacity getNext() const

Get the next larger capacity.

size_t getSize() const

Get the number of elements in an array with this capacity.

static Capacity get(size_t N)

Get the capacity of an array that can hold at least N elements.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

ArrayRef< T > slice(size_t N, size_t M) const

slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.

This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...

ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.

LLVM_ABI bool isEntryValue() const

Check if the expression consists of exactly one entry value operand.

static LLVM_ABI bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)

Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...

static LLVM_ABI DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)

Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...

static LLVM_ABI DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)

Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...

bool hasTrivialDestructor() const

Check whether this has a trivial destructor.

Diagnostic information for inline asm reporting.

Utility class for floating point operations which can have information about relaxed accuracy require...

Convenience struct for specifying and reasoning about fast-math flags.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

an instruction for type-safe pointer arithmetic to access elements of arrays and structs

This instruction compares its operands according to the predicate given to the constructor.

static StringRef getMemConstraintName(ConstraintCode C)

constexpr bool isValid() const

This is an important class for using LLVM in a threaded context.

LLVM_ABI void diagnose(const DiagnosticInfo &DI)

Report a message to the currently installed diagnostic handler.

A set of physical registers with utility functions to track liveness when walking backward/forward th...

bool available(const MachineRegisterInfo &MRI, MCRegister Reg) const

Returns true if register Reg and no aliasing register is in the set.

A set of register units used to track register liveness.

static LocationSize precise(uint64_t Value)

static constexpr LocationSize beforeOrAfterPointer()

Any location before or after the base pointer (but still within the underlying object).

TypeSize getValue() const

Describe properties that are true of each instruction in the target description file.

ArrayRef< MCOperandInfo > operands() const

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

const MDOperand & getOperand(unsigned I) const

unsigned getNumOperands() const

Return number of MDNode operands.

bool isValid() const

isValid - Returns true until all the operands have been visited.

LLVM_ABI MachineInstr * remove_instr(MachineInstr *I)

Remove the possibly bundled instruction from the instruction list without deleting it.

LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

instr_iterator erase_instr(MachineInstr *I)

Remove an instruction from the instruction list and delete it.

MachineInstr * remove(MachineInstr *I)

Remove the unbundled instruction from the instruction list without deleting it.

Instructions::iterator instr_iterator

Instructions::const_iterator const_instr_iterator

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

LLVM_ABI instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isSpillSlotObjectIndex(int ObjectIdx) const

Returns true if the specified index corresponds to a spill slot.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

unsigned getNewDebugInstrNum()

MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0, MDNode *MMRAs=nullptr, Value *DS=nullptr)

Allocate and construct an extra info structure for a MachineInstr.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)

Dellocate an array of MachineOperands and recycle the memory.

MachineOperand * allocateOperandArray(OperandCapacity Cap)

Allocate an array of MachineOperands.

void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addMetadata(const MDNode *MD) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

bool mayRaiseFPException() const

Return true if this instruction could possibly raise a floating-point exception.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)

Mark all subregister defs of register Reg with the undef flag.

Definition MachineInstr.cpp:2274

bool isDebugValueList() const

LLVM_ABI void bundleWithPred()

Bundle this instruction with its predecessor.

Definition MachineInstr.cpp:869

bool isTerminator(QueryType Type=AnyInBundle) const

Returns true if this instruction part of the terminator for a basic block.

LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const

Definition MachineInstr.cpp:2700

LLVM_ABI iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const

Returns a range of all of the operands that correspond to a debug use of Reg.

Definition MachineInstr.cpp:827

mop_range debug_operands()

Returns all operands that are used to determine the variable location for this DBG_VALUE instruction.

bool mayLoadOrStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read or modify memory.

LLVM_ABI void setCFIType(MachineFunction &MF, uint32_t Type)

Set the CFI type for the instruction.

Definition MachineInstr.cpp:532

LLVM_ABI MachineInstr * removeFromParent()

Unlink 'this' from the containing basic block, and return it without deleting it.

Definition MachineInstr.cpp:777

const MachineBasicBlock * getParent() const

MDNode * getMMRAMetadata() const

Helper to extract mmra.op metadata.

LLVM_ABI void bundleWithSucc()

Bundle this instruction with its successor.

Definition MachineInstr.cpp:878

uint32_t getCFIType() const

Helper to extract a CFI type hash if one has been added.

bool isDebugLabel() const

LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)

Set a symbol that will be emitted just prior to the instruction itself.

Definition MachineInstr.cpp:480

bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...

LLVM_ABI bool isDereferenceableInvariantLoad() const

Return true if this load instruction never traps and points to a memory location whose value doesn't ...

Definition MachineInstr.cpp:1614

void setFlags(unsigned flags)

QueryType

API for querying MachineInstr properties.

LLVM_ABI void addImplicitDefUseOperands(MachineFunction &MF)

Add all implicit def and use operands to this instruction.

Definition MachineInstr.cpp:90

filtered_mop_range all_defs()

Returns an iterator range over all operands that are (explicit or implicit) register defs.

LLVM_ABI std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const

Definition MachineInstr.cpp:2661

bool isCall(QueryType Type=AnyInBundle) const

LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const

Definition MachineInstr.cpp:2678

bool getFlag(MIFlag Flag) const

Return whether an MI flag is set.

LLVM_ABI uint32_t mergeFlagsWith(const MachineInstr &Other) const

Return the MIFlags which represent both MachineInstrs.

Definition MachineInstr.cpp:578

LLVM_ABI const MachineOperand & getDebugExpressionOp() const

Return the operand for the complex address expression referenced by this DBG_VALUE instruction.

Definition MachineInstr.cpp:970

LLVM_ABI std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

Definition MachineInstr.cpp:1119

LLVM_ABI Register isConstantValuePHI() const

If the specified instruction is a PHI that always merges together the same virtual register,...

Definition MachineInstr.cpp:1650

bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const

Return true if the use operand of the specified index is tied to a def operand.

LLVM_ABI bool allImplicitDefsAreDead() const

Return true if all the implicit defs of this instruction are dead.

Definition MachineInstr.cpp:1692

LLVM_ABI void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)

Clone another MachineInstr's memory reference descriptor list and replace ours with it.

Definition MachineInstr.cpp:393

LLVM_ABI const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const

Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.

Definition MachineInstr.cpp:1026

LLVM_ABI bool isSafeToMove(bool &SawStore) const

Return true if it is safe to move this instruction.

Definition MachineInstr.cpp:1340

LLVM_ABI bool mayAlias(BatchAAResults *AA, const MachineInstr &Other, bool UseTBAA) const

Returns true if this instruction's memory access aliases the memory access of Other.

Definition MachineInstr.cpp:1531

bool isDebugInstr() const

unsigned getNumDebugOperands() const

Returns the total number of operands which are debug locations.

unsigned getNumOperands() const

Retuns the total number of operands.

LLVM_ABI void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

Definition MachineInstr.cpp:206

LLVM_ABI MachineInstr * removeFromBundle()

Unlink this instruction from its basic block and return it without deleting it.

Definition MachineInstr.cpp:782

LLVM_ABI void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const

Print on dbgs() the current instruction and the instructions defining its operands and so on until we...

Definition MachineInstr.cpp:1784

LLVM_ABI void copyIRFlags(const Instruction &I)

Copy all flags to MachineInst MIFlags.

Definition MachineInstr.cpp:653

bool isDebugValueLike() const

bool memoperands_empty() const

Return true if we don't have any memory operands which described the memory access done by this instr...

mmo_iterator memoperands_end() const

Access to memory operands of the instruction.

LLVM_ABI void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)

Scan instructions immediately following MI and collect any matching DBG_VALUEs.

Definition MachineInstr.cpp:2530

LLVM_ABI std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a restore instruction.

Definition MachineInstr.cpp:2613

unsigned getOperandNo(const_mop_iterator I) const

Returns the number of the operand iterator I points to.

LLVM_ABI unsigned getNumExplicitOperands() const

Returns the number of non-implicit operands.

Definition MachineInstr.cpp:838

mop_range implicit_operands()

LLVM_ABI void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)

Assign this MachineInstr's memory reference descriptor list.

Definition MachineInstr.cpp:373

LLVM_ABI bool wouldBeTriviallyDead() const

Return true if this instruction would be trivially dead if all of its defined registers were dead.

Definition MachineInstr.cpp:1387

bool isBundledWithPred() const

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...

LLVM_ABI std::tuple< LLT, LLT > getFirst2LLTs() const

Definition MachineInstr.cpp:2643

LLVM_ABI std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a folded spill instruction.

Definition MachineInstr.cpp:2605

LLVM_ABI void unbundleFromPred()

Break bundle above this instruction.

Definition MachineInstr.cpp:887

LLVM_ABI void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)

Copy implicit register operands from specified instruction to this instruction.

Definition MachineInstr.cpp:1704

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

LLVM_ABI bool isStackAligningInlineAsm() const

Definition MachineInstr.cpp:905

LLVM_ABI void dropMemRefs(MachineFunction &MF)

Clear this MachineInstr's memory reference descriptor list.

Definition MachineInstr.cpp:364

LLVM_ABI int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const

Returns the operand index that is a use of the specific register or -1 if it is not found.

Definition MachineInstr.cpp:1098

MDNode * getPCSections() const

Helper to extract PCSections metadata target sections.

bool isCFIInstruction() const

LLVM_ABI int findFirstPredOperandIdx() const

Find the index of the first operand in the operand list that is used to represent the predicate.

Definition MachineInstr.cpp:1176

const MCInstrDesc & getDesc() const

Returns the target instruction descriptor of this MachineInstr.

LLVM_ABI unsigned getBundleSize() const

Return the number of instructions inside the MI bundle, excluding the bundle header.

Definition MachineInstr.cpp:1075

LLVM_ABI void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...

Definition MachineInstr.cpp:429

LLVM_ABI bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const

Return true if this is a call instruction that may have an additional information associated with it.

Definition MachineInstr.cpp:797

LLVM_ABI std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const

Definition MachineInstr.cpp:2688

LLVM_ABI std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const

Definition MachineInstr.cpp:2670

unsigned getNumMemOperands() const

Return the number of memory operands.

void clearFlag(MIFlag Flag)

clearFlag - Clear a MI flag.

LLVM_ABI std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a folded restore instruction.

Definition MachineInstr.cpp:2624

LLVM_ABI const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const

Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.

Definition MachineInstr.cpp:1055

bool isOperandSubregIdx(unsigned OpIdx) const

Return true if operand OpIdx is a subregister index.

LLVM_ABI InlineAsm::AsmDialect getInlineAsmDialect() const

Definition MachineInstr.cpp:914

LLVM_ABI bool hasUnmodeledSideEffects() const

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...

Definition MachineInstr.cpp:1663

LLVM_ABI bool isEquivalentDbgInstr(const MachineInstr &Other) const

Returns true if this instruction is a debug instruction that represents an identical debug value to O...

Definition MachineInstr.cpp:754

LLVM_ABI const DILabel * getDebugLabel() const

Return the debug label referenced by this DBG_LABEL instruction.

Definition MachineInstr.cpp:949

void untieRegOperand(unsigned OpIdx)

Break any tie involving OpIdx.

static LLVM_ABI uint32_t copyFlagsFromInstruction(const Instruction &I)

Definition MachineInstr.cpp:584

LLVM_ABI unsigned removePHIIncomingValueFor(const MachineBasicBlock &MBB)

Remove all incoming values of Phi instruction for the given block.

Definition MachineInstr.cpp:2774

LLVM_ABI void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)

Inserts Ops BEFORE It. Can untie/retie tied operands.

Definition MachineInstr.cpp:2712

LLVM_ABI void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

Definition MachineInstr.cpp:145

bool isJumpTableDebugInfo() const

LLVM_ABI unsigned getNumExplicitDefs() const

Returns the number of non-implicit definitions.

Definition MachineInstr.cpp:856

LLVM_ABI void eraseFromBundle()

Unlink 'this' from its basic block and delete it.

Definition MachineInstr.cpp:792

LLVM_ABI void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)

Set a marker on instructions that denotes where we should create and emit heap alloc site labels.

Definition MachineInstr.cpp:512

LLVM_ABI const DILocalVariable * getDebugVariable() const

Return the debug variable referenced by this DBG_VALUE instruction.

Definition MachineInstr.cpp:966

LLVM_ABI bool hasComplexRegisterTies() const

Return true when an instruction has tied register that can't be determined by the instruction's descr...

Definition MachineInstr.cpp:1712

LLVM_ABI LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const

Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.

Definition MachineInstr.cpp:1729

bool isLifetimeMarker() const

LLVM_ABI void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)

Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...

Definition MachineInstr.cpp:1317

LLVM_ABI unsigned findTiedOperandIdx(unsigned OpIdx) const

Given the index of a tied register operand, find the operand it is tied to.

Definition MachineInstr.cpp:1233

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

Definition MachineInstr.cpp:1206

mmo_iterator memoperands_begin() const

Access to memory operands of the instruction.

LLVM_ABI void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)

Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.

Definition MachineInstr.cpp:562

LLVM_ABI void changeDebugValuesDefReg(Register Reg)

Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.

Definition MachineInstr.cpp:2546

LLVM_ABI bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const

Return true if this instruction is identical to Other.

Definition MachineInstr.cpp:673

LLVM_ABI bool hasOrderedMemoryRef() const

Return true if this instruction may have an ordered or volatile memory reference, or if the informati...

Definition MachineInstr.cpp:1592

LLVM_ABI void emitGenericError(const Twine &ErrMsg) const

Definition MachineInstr.cpp:2363

LLVM_ABI const MachineFunction * getMF() const

Return the function that contains the basic block that this instruction belongs to.

Definition MachineInstr.cpp:773

LLVM_ABI const DIExpression * getDebugExpression() const

Return the complex address expression referenced by this DBG_VALUE instruction.

Definition MachineInstr.cpp:982

ArrayRef< MachineMemOperand * > memoperands() const

Access to memory operands of the instruction.

LLVM_ABI void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const

Print this MI to OS.

Definition MachineInstr.cpp:1791

bool isNonListDebugValue() const

MachineOperand * mop_iterator

iterator/begin/end - Iterate over all operands of a machine instruction.

LLVM_ABI bool isLoadFoldBarrier() const

Returns true if it is illegal to fold a load across this instruction.

Definition MachineInstr.cpp:1675

bool mayStore(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly modify memory.

void setFlag(MIFlag Flag)

Set a MI flag.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI bool isDead(const MachineRegisterInfo &MRI, LiveRegUnits *LivePhysRegs=nullptr) const

Check whether an MI is dead.

Definition MachineInstr.cpp:1409

LLVM_ABI std::tuple< LLT, LLT, LLT > getFirst3LLTs() const

Definition MachineInstr.cpp:2648

LLVM_ABI const MachineOperand & getDebugVariableOp() const

Return the operand for the debug variable referenced by this DBG_VALUE instruction.

Definition MachineInstr.cpp:954

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

Definition MachineInstr.cpp:787

LLVM_ABI void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

Definition MachineInstr.cpp:2297

LLVM_ABI void removeOperand(unsigned OpNo)

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

Definition MachineInstr.cpp:296

friend class MachineFunction

MCSymbol * getPreInstrSymbol() const

Helper to extract a pre-instruction symbol if one has been added.

LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

Definition MachineInstr.cpp:2137

LLVM_ABI void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)

Set a symbol that will be emitted just after the instruction itself.

Definition MachineInstr.cpp:496

bool isDebugValue() const

LLVM_ABI void dump() const

Definition MachineInstr.cpp:1754

const MachineOperand & getDebugOffset() const

Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...

MachineOperand & getDebugOperand(unsigned Index)

LLVM_ABI std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const

Return a valid size if the instruction is a spill instruction.

Definition MachineInstr.cpp:2594

bool isBundledWithSucc() const

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...

LLVM_ABI void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)

We have determined MI defines a register.

Definition MachineInstr.cpp:2280

MDNode * getHeapAllocMarker() const

Helper to extract a heap alloc marker if one has been added.

LLVM_ABI unsigned getDebugInstrNum()

Fetch the instruction number of this MachineInstr.

Definition MachineInstr.cpp:2631

LLVM_ABI std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const

Definition MachineInstr.cpp:2654

LLVM_ABI void clearRegisterDeads(Register Reg)

Clear all dead flags on operands defining register Reg.

Definition MachineInstr.cpp:2268

LLVM_ABI void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)

Clear all kill flags affecting Reg.

Definition MachineInstr.cpp:2203

const MachineOperand & getOperand(unsigned i) const

LLVM_ABI void emitInlineAsmError(const Twine &ErrMsg) const

Emit an error referring to the source location of this instruction.

Definition MachineInstr.cpp:2352

uint32_t getFlags() const

Return the MI flags bitvector.

bool isPseudoProbe() const

LLVM_ABI bool hasRegisterImplicitUseOperand(Register Reg) const

Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...

Definition MachineInstr.cpp:1087

LLVM_ABI bool shouldUpdateAdditionalCallInfo() const

Return true if copying, moving, or erasing this instruction requires updating additional call info (s...

Definition MachineInstr.cpp:810

LLVM_ABI void setDeactivationSymbol(MachineFunction &MF, Value *DS)

Definition MachineInstr.cpp:552

Value * getDeactivationSymbol() const

MCSymbol * getPostInstrSymbol() const

Helper to extract a post-instruction symbol if one has been added.

LLVM_ABI void unbundleFromSucc()

Break bundle below this instruction.

Definition MachineInstr.cpp:896

LLVM_ABI void clearKillInfo()

Clears kill flags on all operands.

Definition MachineInstr.cpp:1310

LLVM_ABI bool isDebugEntryValue() const

A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.

Definition MachineInstr.cpp:986

bool isIndirectDebugValue() const

A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...

unsigned getNumDefs() const

Returns the total number of definitions.

LLVM_ABI void setPCSections(MachineFunction &MF, MDNode *MD)

Definition MachineInstr.cpp:522

LLVM_ABI const MDNode * getLocCookieMD() const

For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.

Definition MachineInstr.cpp:2337

LLVM_ABI int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const

Returns the operand index that is a def of the specified register or -1 if it is not found.

Definition MachineInstr.cpp:1147

bool isVariadic(QueryType Type=IgnoreBundle) const

Return true if this instruction can have a variable number of operands.

LLVM_ABI int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...

Definition MachineInstr.cpp:920

LLVM_ABI bool allDefsAreDead() const

Return true if all the defs of this instruction are dead.

Definition MachineInstr.cpp:1682

LLVM_ABI void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)

Definition MachineInstr.cpp:542

LLVM_ABI const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const

Compute the static register class constraint for operand OpIdx.

Definition MachineInstr.cpp:991

LLVM_ABI void moveBefore(MachineInstr *MovePos)

Move the instruction before MovePos.

Definition MachineInstr.cpp:152

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

Definition MachineInstr.cpp:385

LLVM_ABI bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

Definition MachineInstr.cpp:2216

LLVM_ABI bool mayFoldInlineAsmRegOp(unsigned OpId) const

Returns true if the register operand can be folded with a load or store into a frame index.

Definition MachineInstr.cpp:2757

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

const PseudoSourceValue * getPseudoValue() const

bool isUnordered() const

Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...

AAMDNodes getAAInfo() const

Return the AA tags for the memory reference.

const Value * getValue() const

Return the base address of the memory access.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

LLVM_ABI void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

static LLVM_ABI void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)

Print a subreg index operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

const MDNode * getMetadata() const

void setIsDead(bool Val=true)

void setMetadata(const MDNode *MD)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

LLVM_ABI void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

bool isMetadata() const

isMetadata - Tests if this is a MO_Metadata operand.

LLVM_ABI void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const

Print the MachineOperand to os.

void setIsKill(bool Val=true)

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

LLVM_ABI void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...

void setIsEarlyClobber(bool Val=true)

void setIsUndef(bool Val=true)

void setIsDebug(bool Val=true)

getReg - Returns the register number.

LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const

Returns true if this operand is identical to the specified operand except for liveness related flags ...

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

static LLVM_ABI void printSymbol(raw_ostream &OS, MCSymbol &Sym)

Print a MCSymbol as an operand.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Representation for a specific memory location.

Manage lifetime of a slot tracker for printing IR.

void incorporateFunction(const Function &F)

Incorporate the given function.

A Module instance is used to store all the information related to an LLVM module.

Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.

An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...

A udiv, sdiv, lshr, or ashr instruction, which can be marked as "exact", indicating that no bits are ...

Instruction that can have a nneg flag (zext/uitofp).

Special value supplied for machine level alias analysis.

virtual bool mayAlias(const MachineFrameInfo *) const

Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

void reserve(size_type N)

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

static LLVM_ABI unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)

Get index of next meta operand.

MI-level Statepoint operands.

LLVM_ABI int getFirstGCPtrIdx()

Get index of first GC pointer operand of -1 if there are none.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

This class represents a truncation of integer types.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

A Use represents the edge between a Value definition and its users.

LLVM Value Representation.

LLVM_ABI StringRef getName() const

Return a constant reference to the value's name.

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

formatted_raw_ostream & PadToColumn(unsigned NewCol)

PadToColumn - Align the output to some column number.

self_iterator getIterator()

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Abstract Attribute helper functions.

MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)

std::enable_if_t< detail::IsValidPointer< X, Y >::value, bool > hasa(Y &&MD)

Check whether Metadata has a Value.

std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > extract(Y &&MD)

Extract a Value from Metadata.

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

hash_code hash_value(const FixedPointSemantics &Val)

LLVM_ABI formatted_raw_ostream & fdbgs()

fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)

Update a DBG_VALUE whose value has been spilled to FrameIndex.

Definition MachineInstr.cpp:2520

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)

Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

OutputIt move(R &&Range, OutputIt Out)

Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)

Clone a DBG_VALUE whose value has been spilled to FrameIndex.

Definition MachineInstr.cpp:2475

iterator_range< pointer_iterator< WrappedIteratorT > > make_pointer_range(RangeT &&Range)

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

filter_iterator_impl< WrappedIteratorT, PredicateT, detail::fwd_or_bidi_tag< WrappedIteratorT > > filter_iterator

Defines filter_iterator to a suitable specialization of filter_iterator_impl, based on the underlying...

hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)

Compute a hash_code for a sequence of values.

Implement std::hash so that hash_code can be used in STL containers.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

static LLVM_ABI unsigned getHashValue(const MachineInstr *const &MI)

Definition MachineInstr.cpp:2323