LLVM: lib/CodeGen/MachineVerifier.cpp Source File (original) (raw)
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86#include
87#include
88#include
89#include
90#include
91#include
92#include
93
94using namespace llvm;
95
96namespace {
97
98
99
101
102struct MachineVerifier {
104 raw_ostream *OS, bool AbortOnError = true)
105 : MFAM(&MFAM), OS(OS ? *OS : nulls()), Banner(b),
106 ReportedErrs(AbortOnError) {}
107
108 MachineVerifier(Pass *pass, const char *b, raw_ostream *OS,
109 bool AbortOnError = true)
110 : PASS(pass), OS(OS ? *OS : nulls()), Banner(b),
111 ReportedErrs(AbortOnError) {}
112
113 MachineVerifier(const char *b, LiveVariables *LiveVars,
114 LiveIntervals *LiveInts, LiveStacks *LiveStks,
115 SlotIndexes *Indexes, raw_ostream *OS,
116 bool AbortOnError = true)
117 : OS(OS ? *OS : nulls()), Banner(b), LiveVars(LiveVars),
118 LiveInts(LiveInts), LiveStks(LiveStks), Indexes(Indexes),
119 ReportedErrs(AbortOnError) {}
120
121
122 bool verify(const MachineFunction &MF);
123
125 Pass *const PASS = nullptr;
126 raw_ostream &OS;
127 const char *Banner;
128 const MachineFunction *MF = nullptr;
129 const TargetMachine *TM = nullptr;
130 const TargetInstrInfo *TII = nullptr;
131 const TargetRegisterInfo *TRI = nullptr;
132 const MachineRegisterInfo *MRI = nullptr;
133 const RegisterBankInfo *RBI = nullptr;
134
135
136 bool isFunctionRegBankSelected = false;
137 bool isFunctionSelected = false;
138 bool isFunctionTracksDebugUserValues = false;
139
140 using RegVector = SmallVector<Register, 16>;
141 using RegMaskVector = SmallVector<const uint32_t *, 4>;
142 using RegSet = DenseSet;
143 using RegMap = DenseMap<Register, const MachineInstr *>;
144 using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
145
146 const MachineInstr *FirstNonPHI = nullptr;
147 const MachineInstr *FirstTerminator = nullptr;
148 BlockSet FunctionBlocks;
149
150 BitVector regsReserved;
151 RegSet regsLive;
152 RegVector regsDefined, regsDead, regsKilled;
153 RegMaskVector regMasks;
154
155 SlotIndex lastIndex;
156
157
158 void addRegWithSubRegs(RegVector &RV, Register Reg) {
159 RV.push_back(Reg);
162 }
163
164 struct BBInfo {
165
166 bool reachable = false;
167
168
169
170
171 RegMap vregsLiveIn;
172
173
174
175 RegSet regsKilled;
176
177
178
179 RegSet regsLiveOut;
180
181
182
183 RegSet vregsPassed;
184
185
186
187 RegSet vregsRequired;
188
189
191
192 BBInfo() = default;
193
194
195
198 return false;
199 if (regsLiveOut.count(Reg))
200 return false;
201 return vregsRequired.insert(Reg).second;
202 }
203
204
205 bool addRequired(const RegSet &RS) {
210 }
211
212
213 bool addRequired(const RegMap &RM) {
215 for (const auto &I : RM)
216 Changed |= addRequired(I.first);
218 }
219
220
222 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
223 }
224 };
225
226
227 DenseMap<const MachineBasicBlock *, BBInfo> MBBInfoMap;
228
230 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
231 }
232
234 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
235 !regsReserved.test(Reg.id());
236 }
237
238
239 LiveVariables *LiveVars = nullptr;
240 LiveIntervals *LiveInts = nullptr;
241 LiveStacks *LiveStks = nullptr;
242 SlotIndexes *Indexes = nullptr;
243
244
245
246 class ReportedErrors {
247 unsigned NumReported = 0;
248 bool AbortOnError;
249
250 public:
251
252 ReportedErrors(bool AbortOnError) : AbortOnError(AbortOnError) {}
253
254 ~ReportedErrors() {
255 if (!hasError())
256 return;
257 if (AbortOnError)
259 " machine code errors.");
260
261
262 ReportedErrorsLock->unlock();
263 }
264
265
266
267 bool increment() {
268
269
270
271 if (!hasError())
272 ReportedErrorsLock->lock();
273 ++NumReported;
274 return NumReported == 1;
275 }
276
277
278 bool hasError() { return NumReported; }
279 };
280 ReportedErrors ReportedErrs;
281
282
283
284
285 MachineDominatorTree DT;
286
287 void visitMachineFunctionBefore();
288 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
289 void visitMachineBundleBefore(const MachineInstr *MI);
290
291
292
293
294 bool verifyAllRegOpsScalar(const MachineInstr &MI,
295 const MachineRegisterInfo &MRI);
296 bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
297
298 bool verifyGIntrinsicSideEffects(const MachineInstr *MI);
299 bool verifyGIntrinsicConvergence(const MachineInstr *MI);
300 void verifyPreISelGenericInstruction(const MachineInstr *MI);
301
302 void visitMachineInstrBefore(const MachineInstr *MI);
303 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
304 void visitMachineBundleAfter(const MachineInstr *MI);
305 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
306 void visitMachineFunctionAfter();
307
308 void report(const char *msg, const MachineFunction *MF);
309 void report(const char *msg, const MachineBasicBlock *MBB);
310 void report(const char *msg, const MachineInstr *MI);
311 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
312 LLT MOVRegType = LLT{});
313 void report(const Twine &Msg, const MachineInstr *MI);
314
315 void report_context(const LiveInterval &LI) const;
316 void report_context(const LiveRange &LR, VirtRegOrUnit VRegOrUnit,
317 LaneBitmask LaneMask) const;
318 void report_context(const LiveRange::Segment &S) const;
319 void report_context(const VNInfo &VNI) const;
320 void report_context(SlotIndex Pos) const;
321 void report_context(MCPhysReg PhysReg) const;
322 void report_context_liverange(const LiveRange &LR) const;
323 void report_context_lanemask(LaneBitmask LaneMask) const;
324 void report_context_vreg(Register VReg) const;
325 void report_context_vreg_regunit(VirtRegOrUnit VRegOrUnit) const;
326
327 void verifyInlineAsm(const MachineInstr *MI);
328
329 void checkLiveness(const MachineOperand *MO, unsigned MONum);
330 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
331 SlotIndex UseIdx, const LiveRange &LR,
332 VirtRegOrUnit VRegOrUnit,
334 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
335 SlotIndex DefIdx, const LiveRange &LR,
336 VirtRegOrUnit VRegOrUnit, bool SubRangeCheck = false,
338
339 void markReachable(const MachineBasicBlock *MBB);
340 void calcRegsPassed();
341 void checkPHIOps(const MachineBasicBlock &MBB);
342
343 void calcRegsRequired();
344 void verifyLiveVariables();
345 void verifyLiveIntervals();
346 void verifyLiveInterval(const LiveInterval &);
347 void verifyLiveRangeValue(const LiveRange &, const VNInfo *, VirtRegOrUnit,
348 LaneBitmask);
349 void verifyLiveRangeSegment(const LiveRange &,
350 const LiveRange::const_iterator I, VirtRegOrUnit,
351 LaneBitmask);
352 void verifyLiveRange(const LiveRange &, VirtRegOrUnit,
354
355 void verifyStackFrame();
356
357 void verifyStackProtector();
358
359 void verifySlotIndexes() const;
360 void verifyProperties(const MachineFunction &MF);
361};
362
364 static char ID;
365
366 const std::string Banner;
367
368 MachineVerifierLegacyPass(std::string banner = std::string())
369 : MachineFunctionPass(ID), Banner(std::move(banner)) {
371 }
372
373 void getAnalysisUsage(AnalysisUsage &AU) const override {
380 }
381
382 bool runOnMachineFunction(MachineFunction &MF) override {
383
384
385
387 return false;
388
389 MachineVerifier(this, Banner.c_str(), &errs()).verify(MF);
390 return false;
391 }
392};
393
394}
395
399
400
401
404 MachineVerifier(MFAM, Banner.c_str(), &errs()).verify(MF);
406}
407
408char MachineVerifierLegacyPass::ID = 0;
409
411 "Verify generated machine code", false, false)
412
414 return new MachineVerifierLegacyPass(Banner);
415}
416
419
420
421
422
423
424 MachineVerifier(nullptr, Banner.c_str(), &errs()).verify(MF);
425}
426
428 bool AbortOnError) const {
429 return MachineVerifier(p, Banner, OS, AbortOnError).verify(*this);
430}
431
434 bool AbortOnError) const {
435 return MachineVerifier(MFAM, Banner, OS, AbortOnError).verify(*this);
436}
437
440 bool AbortOnError) const {
441 return MachineVerifier(Banner, nullptr, LiveInts,
442 nullptr, Indexes, OS, AbortOnError)
443 .verify(*this);
444}
445
446void MachineVerifier::verifySlotIndexes() const {
447 if (Indexes == nullptr)
448 return;
449
450
456 }
457}
458
459void MachineVerifier::verifyProperties(const MachineFunction &MF) {
460
461
462
463 if (MF.getProperties().hasNoVRegs() && MRI->getNumVirtRegs())
464 report("Function has NoVRegs property but there are VReg operands", &MF);
465}
466
468 this->MF = &MF;
474
476 const bool isFunctionFailedISel = Props.hasFailedISel();
477
478
479
480
481 if (isFunctionFailedISel)
482 return true;
483
484 isFunctionRegBankSelected = Props.hasRegBankSelected();
485 isFunctionSelected = Props.hasSelected();
486 isFunctionTracksDebugUserValues = Props.hasTracksDebugUserValues();
487
488 if (PASS) {
490 LiveInts = LISWrapper ? &LISWrapper->getLIS() : nullptr;
491
493 if (!LiveInts)
494 LiveVars = LVWrapper ? &LVWrapper->getLV() : nullptr;
496 LiveStks = LSWrapper ? &LSWrapper->getLS() : nullptr;
498 Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
499 }
500 if (MFAM) {
503 if (!LiveInts)
505
507 }
508
509 verifySlotIndexes();
510
511 verifyProperties(MF);
512
513 visitMachineFunctionBefore();
515 visitMachineBasicBlockBefore(&MBB);
516
518
519 bool InBundle = false;
520
522 if (MI.getParent() != &MBB) {
523 report("Bad instruction parent pointer", &MBB);
524 OS << "Instruction: " << MI;
525 continue;
526 }
527
528
529 if (InBundle && .isBundledWithPred())
530 report("Missing BundledPred flag, "
531 "BundledSucc was set on predecessor",
532 &MI);
533 if (!InBundle && MI.isBundledWithPred())
534 report("BundledPred flag is set, "
535 "but BundledSucc not set on predecessor",
536 &MI);
537
538
539 if (.isInsideBundle()) {
540 if (CurBundle)
541 visitMachineBundleAfter(CurBundle);
542 CurBundle = &MI;
543 visitMachineBundleBefore(CurBundle);
544 } else if (!CurBundle)
545 report("No bundle header", &MI);
546 visitMachineInstrBefore(&MI);
547 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
549 if (Op.getParent() != &MI) {
550
551
552 report("Instruction has operand with wrong parent set", &MI);
553 }
554
555 visitMachineOperand(&Op, I);
556 }
557
558
559 InBundle = MI.isBundledWithSucc();
560 }
561 if (CurBundle)
562 visitMachineBundleAfter(CurBundle);
563 if (InBundle)
564 report("BundledSucc flag set on last instruction in block", &MBB.back());
565 visitMachineBasicBlockAfter(&MBB);
566 }
567 visitMachineFunctionAfter();
568
569
570 regsLive.clear();
571 regsDefined.clear();
572 regsDead.clear();
573 regsKilled.clear();
574 regMasks.clear();
575 MBBInfoMap.clear();
576
577 return !ReportedErrs.hasError();
578}
579
580void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
582 OS << '\n';
583 if (ReportedErrs.increment()) {
584 if (Banner)
585 OS << "# " << Banner << '\n';
586
587 if (LiveInts != nullptr)
588 LiveInts->print(OS);
589 else
590 MF->print(OS, Indexes);
591 }
592
593 OS << "*** Bad machine code: " << msg << " ***\n"
594 << "- function: " << MF->getName() << '\n';
595}
596
601 << " (" << (const void *)MBB << ')';
602 if (Indexes)
603 OS << " [" << Indexes->getMBBStartIdx(MBB) << ';'
604 << Indexes->getMBBEndIdx(MBB) << ')';
605 OS << '\n';
606}
607
608void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
610 report(msg, MI->getParent());
611 OS << "- instruction: ";
612 if (Indexes && Indexes->hasIndex(*MI))
613 OS << Indexes->getInstructionIndex(*MI) << '\t';
615}
616
617void MachineVerifier::report(const char *msg, const MachineOperand *MO,
618 unsigned MONum, LLT MOVRegType) {
621 OS << "- operand " << MONum << ": ";
622 MO->print(OS, MOVRegType, TRI);
623 OS << '\n';
624}
625
627 report(Msg.str().c_str(), MI);
628}
629
630void MachineVerifier::report_context(SlotIndex Pos) const {
631 OS << "- at: " << Pos << '\n';
632}
633
634void MachineVerifier::report_context(const LiveInterval &LI) const {
635 OS << "- interval: " << LI << '\n';
636}
637
638void MachineVerifier::report_context(const LiveRange &LR,
641 report_context_liverange(LR);
642 report_context_vreg_regunit(VRegOrUnit);
643 if (LaneMask.any())
644 report_context_lanemask(LaneMask);
645}
646
647void MachineVerifier::report_context(const LiveRange::Segment &S) const {
648 OS << "- segment: " << S << '\n';
649}
650
651void MachineVerifier::report_context(const VNInfo &VNI) const {
652 OS << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
653}
654
655void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
656 OS << "- liverange: " << LR << '\n';
657}
658
659void MachineVerifier::report_context(MCPhysReg PReg) const {
660 OS << "- p. register: " << printReg(PReg, TRI) << '\n';
661}
662
663void MachineVerifier::report_context_vreg(Register VReg) const {
664 OS << "- v. register: " << printReg(VReg, TRI) << '\n';
665}
666
667void MachineVerifier::report_context_vreg_regunit(
670 report_context_vreg(VRegOrUnit.asVirtualReg());
671 } else {
673 << '\n';
674 }
675}
676
677void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
678 OS << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
679}
680
682 BBInfo &MInfo = MBBInfoMap[MBB];
683 if (!MInfo.reachable) {
684 MInfo.reachable = true;
686 markReachable(Succ);
687 }
688}
689
690void MachineVerifier::visitMachineFunctionBefore() {
692 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
693 : TRI->getReservedRegs(*MF);
694
695 if (!MF->empty())
696 markReachable(&MF->front());
697
698
699 FunctionBlocks.clear();
700 for (const auto &MBB : *MF) {
701 FunctionBlocks.insert(&MBB);
702 BBInfo &MInfo = MBBInfoMap[&MBB];
703
706 report("MBB has duplicate entries in its predecessor list.", &MBB);
707
710 report("MBB has duplicate entries in its successor list.", &MBB);
711 }
712
713
714 MRI->verifyUseLists();
715
716 if (!MF->empty()) {
717 verifyStackFrame();
718 verifyStackProtector();
719 }
720}
721
722void
724 FirstTerminator = nullptr;
725 FirstNonPHI = nullptr;
726
727 if (!MF->getProperties().hasNoPHIs() && MRI->tracksLiveness()) {
728
729
730 for (const auto &LI : MBB->liveins()) {
731 if (isAllocatable(LI.PhysReg) && ->isEHPad() &&
734 report("MBB has allocatable live-in, but isn't entry, landing-pad, or "
735 "inlineasm-br-indirect-target.",
737 report_context(LI.PhysReg);
738 }
739 }
740 }
741
744 report("ir-block-address-taken is associated with basic block not used by "
745 "a blockaddress.",
747 }
748
749
752 if (succ->isEHPad())
753 LandingPadSuccs.insert(succ);
754 if (!FunctionBlocks.count(succ))
755 report("MBB has successor that isn't part of the function.", MBB);
756 if (!MBBInfoMap[succ].Preds.count(MBB)) {
757 report("Inconsistent CFG", MBB);
758 OS << "MBB is not in the predecessor list of the successor "
760 }
761 }
762
763
765 if (!FunctionBlocks.count(Pred))
766 report("MBB has predecessor that isn't part of the function.", MBB);
767 if (!MBBInfoMap[Pred].Succs.count(MBB)) {
768 report("Inconsistent CFG", MBB);
769 OS << "MBB is not in the successor list of the predecessor "
771 }
772 }
773
777 if (LandingPadSuccs.size() > 1 &&
778 !(AsmInfo &&
782 report("MBB has more than one landing pad successor", MBB);
783
784
789
790
791 if ( && !FBB) {
792
795 report("MBB exits via unconditional fall-through but ends with a "
796 "barrier instruction!", MBB);
797 }
798 if (.empty()) {
799 report("MBB exits via unconditional fall-through but has a condition!",
801 }
803
805 report("MBB exits via unconditional branch but doesn't contain "
806 "any instructions!", MBB);
808 report("MBB exits via unconditional branch but doesn't end with a "
809 "barrier instruction!", MBB);
811 report("MBB exits via unconditional branch but the branch isn't a "
812 "terminator instruction!", MBB);
813 }
815
817 report("MBB exits via conditional branch/fall-through but doesn't "
818 "contain any instructions!", MBB);
820 report("MBB exits via conditional branch/fall-through but ends with a "
821 "barrier instruction!", MBB);
823 report("MBB exits via conditional branch/fall-through but the branch "
824 "isn't a terminator instruction!", MBB);
825 }
826 } else if (TBB && FBB) {
827
828
830 report("MBB exits via conditional branch/branch but doesn't "
831 "contain any instructions!", MBB);
833 report("MBB exits via conditional branch/branch but doesn't end with a "
834 "barrier instruction!", MBB);
836 report("MBB exits via conditional branch/branch but the branch "
837 "isn't a terminator instruction!", MBB);
838 }
839 if (Cond.empty()) {
840 report("MBB exits via conditional branch/branch but there's no "
841 "condition!", MBB);
842 }
843 } else {
844 report("analyzeBranch returned invalid data!", MBB);
845 }
846
847
848
850 report("MBB exits via jump or conditional branch, but its target isn't a "
851 "CFG successor!",
854 report("MBB exits via conditional branch, but its target isn't a CFG "
855 "successor!",
857
858
859
860
861 bool Fallthrough = || (
.empty() && !FBB);
862
863
864
865
866 if (.empty() && !FBB) {
869 report("MBB conditionally falls through out of function!", MBB);
871 report("MBB exits via conditional branch/fall-through but the CFG "
872 "successors don't match the actual successors!",
874 }
875
876
878
879 if (SuccMBB == TBB || SuccMBB == FBB)
880 continue;
881
882
884 continue;
885
886
887 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
888 continue;
889 report("MBB has unexpected successors which are not branch targets, "
890 "fallthrough, EHPads, or inlineasm_br targets.",
892 }
893 }
894
895 regsLive.clear();
896 if (MRI->tracksLiveness()) {
897 for (const auto &LI : MBB->liveins()) {
898 if (!LI.PhysReg.isPhysical()) {
899 report("MBB live-in list contains non-physical register", MBB);
900 continue;
901 }
902 regsLive.insert_range(TRI->subregs_inclusive(LI.PhysReg));
903 }
904 }
905
909 regsLive.insert_range(TRI->subregs_inclusive(I));
910
911 regsKilled.clear();
912 regsDefined.clear();
913
914 if (Indexes)
915 lastIndex = Indexes->getMBBStartIdx(MBB);
916}
917
918
919
920void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
921 if (Indexes && Indexes->hasIndex(*MI)) {
922 SlotIndex idx = Indexes->getInstructionIndex(*MI);
923 if (!(idx > lastIndex)) {
924 report("Instruction index out of order", MI);
925 OS << "Last instruction was at " << lastIndex << '\n';
926 }
927 lastIndex = idx;
928 }
929
930
931 if (MI->isTerminator()) {
932 if (!FirstTerminator)
933 FirstTerminator = MI;
934 } else if (FirstTerminator) {
935
936
937 if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
938 report("Non-terminator instruction after the first terminator", MI);
939 OS << "First terminator was:\t" << *FirstTerminator;
940 }
941 }
942}
943
944
945
946void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
947
948 if (MI->getNumOperands() < 2) {
949 report("Too few operands on inline asm", MI);
950 return;
951 }
952 if (->getOperand(0).isSymbol())
953 report("Asm string must be an external symbol", MI);
954 if (->getOperand(1).isImm())
955 report("Asm flags must be an immediate", MI);
956
957
958
959 if ((MI->getOperand(1).getImm()))
960 report("Unknown asm flags", &MI->getOperand(1), 1);
961
963
966 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
968
970 break;
972 NumOps = 1 + F.getNumOperandRegisters();
973 }
974
975 if (OpNo > MI->getNumOperands())
976 report("Missing operands in last group", MI);
977
978
979 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
980 ++OpNo;
981
982
983 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
986 report("Expected implicit register after groups", &MO, OpNo);
987 }
988
989 if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
991
993 i != e; ++i) {
995
997 continue;
998
999
1000
1002 if (!IndirectTargetMBB) {
1003 report("INLINEASM_BR indirect target does not exist", &MO, i);
1004 break;
1005 }
1006
1008 report("INLINEASM_BR indirect target missing from successor list", &MO,
1009 i);
1010
1012 report("INLINEASM_BR indirect target predecessor list missing parent",
1013 &MO, i);
1014 }
1015 }
1016}
1017
1018bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
1021 if (!Op.isReg())
1022 return false;
1023 const auto Reg = Op.getReg();
1024 if (Reg.isPhysical())
1025 return false;
1026 return !MRI.getType(Reg).isScalar();
1027 }))
1028 return true;
1029 report("All register operands must have scalar types", &MI);
1030 return false;
1031}
1032
1033
1034
1035
1036bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
1039 report("operand types must be all-vector or all-scalar", MI);
1040
1041
1042
1043
1044
1045 return false;
1046 }
1047
1049 report("operand types must preserve number of vector elements", MI);
1050 return false;
1051 }
1052
1053 return true;
1054}
1055
1056bool MachineVerifier::verifyGIntrinsicSideEffects(const MachineInstr *MI) {
1057 auto Opcode = MI->getOpcode();
1058 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
1059 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
1061 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1063 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1064 bool DeclHasSideEffects = .getMemoryEffects().doesNotAccessMemory();
1065 if (NoSideEffects && DeclHasSideEffects) {
1067 " used with intrinsic that accesses memory"),
1068 MI);
1069 return false;
1070 }
1071 if (!NoSideEffects && !DeclHasSideEffects) {
1072 report(Twine(TII->getName(Opcode), " used with readnone intrinsic"), MI);
1073 return false;
1074 }
1075 }
1076
1077 return true;
1078}
1079
1080bool MachineVerifier::verifyGIntrinsicConvergence(const MachineInstr *MI) {
1081 auto Opcode = MI->getOpcode();
1082 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1083 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1085 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1087 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1088 bool DeclIsConvergent = Attrs.hasAttribute(Attribute::Convergent);
1089 if (NotConvergent && DeclIsConvergent) {
1090 report(Twine(TII->getName(Opcode), " used with a convergent intrinsic"),
1091 MI);
1092 return false;
1093 }
1094 if (!NotConvergent && !DeclIsConvergent) {
1095 report(
1096 Twine(TII->getName(Opcode), " used with a non-convergent intrinsic"),
1097 MI);
1098 return false;
1099 }
1100 }
1101
1102 return true;
1103}
1104
1105void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
1106 if (isFunctionSelected)
1107 report("Unexpected generic instruction in a Selected function", MI);
1108
1110 unsigned NumOps = MI->getNumOperands();
1111
1112
1113 if (MI->isBranch() && ->isIndirectBranch()) {
1114 bool HasMBB = false;
1116 if (Op.isMBB()) {
1117 HasMBB = true;
1118 break;
1119 }
1120 }
1121
1122 if (!HasMBB) {
1123 report("Branch instruction is missing a basic block operand or "
1124 "isIndirectBranch property",
1125 MI);
1126 }
1127 }
1128
1129
1131 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
1133 if (.operands()[I].isGenericType())
1134 continue;
1135
1136
1137 size_t TypeIdx = MCID.operands()[I].getGenericTypeIndex();
1138 Types.resize(std::max(TypeIdx + 1, Types.size()));
1139
1141 if (!MO->isReg()) {
1142 report("generic instruction must use register operands", MI);
1143 continue;
1144 }
1145
1147
1148
1150
1151
1152 if (!Types[TypeIdx].isValid())
1153 Types[TypeIdx] = OpTy;
1154 else if (Types[TypeIdx] != OpTy)
1155 report("Type mismatch in generic instruction", MO, I, OpTy);
1156 } else {
1157
1158 report("Generic instruction is missing a virtual register type", MO, I);
1159 }
1160 }
1161
1162
1163 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1166 report("Generic instruction cannot have physical register", MO, I);
1167 }
1168
1169
1170 if (MI->getNumOperands() < MCID.getNumOperands())
1171 return;
1172
1176
1177
1178 unsigned Opc = MI->getOpcode();
1179 switch (Opc) {
1180 case TargetOpcode::G_ASSERT_SEXT:
1181 case TargetOpcode::G_ASSERT_ZEXT: {
1182 std::string OpcName =
1183 Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
1184 if (->getOperand(2).isImm()) {
1185 report(Twine(OpcName, " expects an immediate operand #2"), MI);
1186 break;
1187 }
1188
1189 Register Dst = MI->getOperand(0).getReg();
1190 Register Src = MI->getOperand(1).getReg();
1191 LLT SrcTy = MRI->getType(Src);
1192 int64_t Imm = MI->getOperand(2).getImm();
1193 if (Imm <= 0) {
1194 report(Twine(OpcName, " size must be >= 1"), MI);
1195 break;
1196 }
1197
1199 report(Twine(OpcName, " size must be less than source bit width"), MI);
1200 break;
1201 }
1202
1205
1206
1207 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1208 report(Twine(OpcName, " cannot change register bank"), MI);
1209 break;
1210 }
1211
1212
1214 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1215 report(
1216 Twine(OpcName, " source and destination register classes must match"),
1217 MI);
1218 break;
1219 }
1220
1221 break;
1222 }
1223
1224 case TargetOpcode::G_CONSTANT:
1225 case TargetOpcode::G_FCONSTANT: {
1226 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1228 report("Instruction cannot use a vector result type", MI);
1229
1230 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1231 if (->getOperand(1).isCImm()) {
1232 report("G_CONSTANT operand must be cimm", MI);
1233 break;
1234 }
1235
1236 const ConstantInt *CI = MI->getOperand(1).getCImm();
1238 report("inconsistent constant size", MI);
1239 } else {
1240 if (->getOperand(1).isFPImm()) {
1241 report("G_FCONSTANT operand must be fpimm", MI);
1242 break;
1243 }
1244 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1245
1248 report("inconsistent constant size", MI);
1249 }
1250 }
1251
1252 break;
1253 }
1254 case TargetOpcode::G_LOAD:
1255 case TargetOpcode::G_STORE:
1256 case TargetOpcode::G_ZEXTLOAD:
1257 case TargetOpcode::G_SEXTLOAD: {
1258 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1259 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1261 report("Generic memory instruction must access a pointer", MI);
1262
1263
1264
1265 if (->hasOneMemOperand()) {
1266 report("Generic instruction accessing memory must have one mem operand",
1267 MI);
1268 } else {
1270 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1271 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1274 report("Generic extload must have a narrower memory type", MI);
1275 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1278 report("load memory size cannot exceed result size", MI);
1279
1289 report("range is incompatible with the result type", MI);
1290 }
1291 }
1292 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1295 report("store memory size cannot exceed value size", MI);
1296 }
1297
1299 if (Opc == TargetOpcode::G_STORE) {
1302 report("atomic store cannot use acquire ordering", MI);
1303
1304 } else {
1307 report("atomic load cannot use release ordering", MI);
1308 }
1309 }
1310
1311 break;
1312 }
1313 case TargetOpcode::G_PHI: {
1314 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1317 if (!MO.isReg())
1318 return true;
1319 LLT Ty = MRI->getType(MO.getReg());
1320 if (!Ty.isValid() || (Ty != DstTy))
1321 return false;
1322 return true;
1323 }))
1324 report("Generic Instruction G_PHI has operands with incompatible/missing "
1325 "types",
1326 MI);
1327 break;
1328 }
1329 case TargetOpcode::G_BITCAST: {
1330 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1331 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1333 break;
1334
1336 report("bitcast cannot convert between pointers and other types", MI);
1337
1339 report("bitcast sizes must match", MI);
1340
1341 if (SrcTy == DstTy)
1342 report("bitcast must change the type", MI);
1343
1344 break;
1345 }
1346 case TargetOpcode::G_INTTOPTR:
1347 case TargetOpcode::G_PTRTOINT:
1348 case TargetOpcode::G_ADDRSPACE_CAST: {
1349 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1350 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1352 break;
1353
1354 verifyVectorElementMatch(DstTy, SrcTy, MI);
1355
1358
1359 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1361 report("inttoptr result type must be a pointer", MI);
1363 report("inttoptr source type must not be a pointer", MI);
1364 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1366 report("ptrtoint source type must be a pointer", MI);
1368 report("ptrtoint result type must not be a pointer", MI);
1369 } else {
1370 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1372 report("addrspacecast types must be pointers", MI);
1373 else {
1375 report("addrspacecast must convert different address spaces", MI);
1376 }
1377 }
1378
1379 break;
1380 }
1381 case TargetOpcode::G_PTR_ADD: {
1382 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1383 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1384 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1386 break;
1387
1389 report("gep first operand must be a pointer", MI);
1390
1392 report("gep offset operand must not be a pointer", MI);
1393
1397 unsigned IndexSizeInBits = DL.getIndexSize(AS) * 8;
1399 report("gep offset operand must match index size for address space",
1400 MI);
1401 }
1402 }
1403
1404
1405 break;
1406 }
1407 case TargetOpcode::G_PTRMASK: {
1408 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1409 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1410 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1412 break;
1413
1415 report("ptrmask result type must be a pointer", MI);
1416
1418 report("ptrmask mask type must be an integer", MI);
1419
1420 verifyVectorElementMatch(DstTy, MaskTy, MI);
1421 break;
1422 }
1423 case TargetOpcode::G_SEXT:
1424 case TargetOpcode::G_ZEXT:
1425 case TargetOpcode::G_ANYEXT:
1426 case TargetOpcode::G_TRUNC:
1427 case TargetOpcode::G_TRUNC_SSAT_S:
1428 case TargetOpcode::G_TRUNC_SSAT_U:
1429 case TargetOpcode::G_TRUNC_USAT_U:
1430 case TargetOpcode::G_FPEXT:
1431 case TargetOpcode::G_FPTRUNC: {
1432
1433
1434
1435
1436
1437 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1438 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1439 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1441 break;
1442
1444 report("Generic extend/truncate can not operate on pointers", MI);
1445
1446 verifyVectorElementMatch(DstTy, SrcTy, MI);
1447
1450 switch (MI->getOpcode()) {
1451 default:
1452 if (DstSize <= SrcSize)
1453 report("Generic extend has destination type no larger than source", MI);
1454 break;
1455 case TargetOpcode::G_TRUNC:
1456 case TargetOpcode::G_TRUNC_SSAT_S:
1457 case TargetOpcode::G_TRUNC_SSAT_U:
1458 case TargetOpcode::G_TRUNC_USAT_U:
1459 case TargetOpcode::G_FPTRUNC:
1460 if (DstSize >= SrcSize)
1461 report("Generic truncate has destination type no smaller than source",
1462 MI);
1463 break;
1464 }
1465 break;
1466 }
1467 case TargetOpcode::G_SELECT: {
1468 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1469 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1471 break;
1472
1473
1475 verifyVectorElementMatch(SelTy, CondTy, MI);
1476 break;
1477 }
1478 case TargetOpcode::G_MERGE_VALUES: {
1479
1480
1481
1482
1483 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1484 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1486 report("G_MERGE_VALUES cannot operate on vectors", MI);
1487
1488 const unsigned NumOps = MI->getNumOperands();
1490 report("G_MERGE_VALUES result size is inconsistent", MI);
1491
1492 for (unsigned I = 2; I != NumOps; ++I) {
1493 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1494 report("G_MERGE_VALUES source types do not match", MI);
1495 }
1496
1497 break;
1498 }
1499 case TargetOpcode::G_UNMERGE_VALUES: {
1500 unsigned NumDsts = MI->getNumOperands() - 1;
1501 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1502 for (unsigned i = 1; i < NumDsts; ++i) {
1503 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy) {
1504 report("G_UNMERGE_VALUES destination types do not match", MI);
1505 break;
1506 }
1507 }
1508
1509 LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
1511
1517 report("G_UNMERGE_VALUES source operand does not match vector "
1518 "destination operands",
1519 MI);
1520 } else if (SrcTy.isVector()) {
1521
1522
1523
1525 report("G_UNMERGE_VALUES vector source operand does not match scalar "
1526 "destination operands",
1527 MI);
1528 } else {
1529
1531 report("G_UNMERGE_VALUES scalar source operand does not match scalar "
1532 "destination operands",
1533 MI);
1534 }
1535 }
1536 break;
1537 }
1538 case TargetOpcode::G_BUILD_VECTOR: {
1539
1540
1541 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1542 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1544 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1545 break;
1546 }
1547
1549 report("G_BUILD_VECTOR result element type must match source type", MI);
1550
1552 report("G_BUILD_VECTOR must have an operand for each element", MI);
1553
1555 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1556 report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1557
1558 break;
1559 }
1560 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1561
1562
1563 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1564 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1566 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1567 MI);
1569 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1570 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1571 MI);
1573 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1574 "dest elt type",
1575 MI);
1576 break;
1577 }
1578 case TargetOpcode::G_CONCAT_VECTORS: {
1579
1580
1581 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1582 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1584 report("G_CONCAT_VECTOR requires vector source and destination operands",
1585 MI);
1586
1587 if (MI->getNumOperands() < 3)
1588 report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1589
1591 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1592 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1595 report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1596 break;
1597 }
1598 case TargetOpcode::G_ICMP:
1599 case TargetOpcode::G_FCMP: {
1600 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1601 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1602
1606 report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1607
1608 break;
1609 }
1610 case TargetOpcode::G_SCMP:
1611 case TargetOpcode::G_UCMP: {
1612 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1613 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1614
1616 report("Generic scmp/ucmp does not support pointers as operands", MI);
1617 break;
1618 }
1619
1621 report("Generic scmp/ucmp does not support pointers as a result", MI);
1622 break;
1623 }
1624
1626 report("Result type must be at least 2 bits wide", MI);
1627 break;
1628 }
1629
1633 report("Generic vector scmp/ucmp must preserve number of lanes", MI);
1634 break;
1635 }
1636
1637 break;
1638 }
1639 case TargetOpcode::G_EXTRACT: {
1641 if (.isReg()) {
1642 report("extract source must be a register", MI);
1643 break;
1644 }
1645
1648 report("extract offset must be a constant", MI);
1649 break;
1650 }
1651
1652 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1653 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1654 if (SrcSize == DstSize)
1655 report("extract source must be larger than result", MI);
1656
1657 if (DstSize + OffsetOp.getImm() > SrcSize)
1658 report("extract reads past end of register", MI);
1659 break;
1660 }
1661 case TargetOpcode::G_INSERT: {
1663 if (.isReg()) {
1664 report("insert source must be a register", MI);
1665 break;
1666 }
1667
1670 report("insert offset must be a constant", MI);
1671 break;
1672 }
1673
1674 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1675 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1676
1677 if (DstSize <= SrcSize)
1678 report("inserted size must be smaller than total register", MI);
1679
1680 if (SrcSize + OffsetOp.getImm() > DstSize)
1681 report("insert writes past end of register", MI);
1682
1683 break;
1684 }
1685 case TargetOpcode::G_JUMP_TABLE: {
1686 if (->getOperand(1).isJTI())
1687 report("G_JUMP_TABLE source operand must be a jump table index", MI);
1688 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1690 report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1691 break;
1692 }
1693 case TargetOpcode::G_BRJT: {
1694 if (->getType(MI->getOperand(0).getReg()).isPointer())
1695 report("G_BRJT src operand 0 must be a pointer type", MI);
1696
1697 if (->getOperand(1).isJTI())
1698 report("G_BRJT src operand 1 must be a jump table index", MI);
1699
1700 const auto &IdxOp = MI->getOperand(2);
1701 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1702 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1703 break;
1704 }
1705 case TargetOpcode::G_INTRINSIC:
1706 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1707 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1708 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1709
1710
1711 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1713 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1714 break;
1715 }
1716
1717 if (!verifyGIntrinsicSideEffects(MI))
1718 break;
1719 if (!verifyGIntrinsicConvergence(MI))
1720 break;
1721
1722 break;
1723 }
1724 case TargetOpcode::G_SEXT_INREG: {
1725 if (->getOperand(2).isImm()) {
1726 report("G_SEXT_INREG expects an immediate operand #2", MI);
1727 break;
1728 }
1729
1730 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1731 int64_t Imm = MI->getOperand(2).getImm();
1732 if (Imm <= 0)
1733 report("G_SEXT_INREG size must be >= 1", MI);
1735 report("G_SEXT_INREG size must be less than source bit width", MI);
1736 break;
1737 }
1738 case TargetOpcode::G_BSWAP: {
1739 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1741 report("G_BSWAP size must be a multiple of 16 bits", MI);
1742 break;
1743 }
1744 case TargetOpcode::G_VSCALE: {
1745 if (->getOperand(1).isCImm()) {
1746 report("G_VSCALE operand must be cimm", MI);
1747 break;
1748 }
1749 if (MI->getOperand(1).getCImm()->isZero()) {
1750 report("G_VSCALE immediate cannot be zero", MI);
1751 break;
1752 }
1753 break;
1754 }
1755 case TargetOpcode::G_STEP_VECTOR: {
1756 if (->getOperand(1).isCImm()) {
1757 report("operand must be cimm", MI);
1758 break;
1759 }
1760
1761 if (->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
1762 report("step must be > 0", MI);
1763 break;
1764 }
1765
1766 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1768 report("Destination type must be a scalable vector", MI);
1769 break;
1770 }
1771
1772
1774 report("Destination element type must be scalar", MI);
1775 break;
1776 }
1777
1778 if (MI->getOperand(1).getCImm()->getBitWidth() !=
1780 report("step bitwidth differs from result type element bitwidth", MI);
1781 break;
1782 }
1783 break;
1784 }
1785 case TargetOpcode::G_INSERT_SUBVECTOR: {
1787 if (!Src0Op.isReg()) {
1788 report("G_INSERT_SUBVECTOR first source must be a register", MI);
1789 break;
1790 }
1791
1793 if (!Src1Op.isReg()) {
1794 report("G_INSERT_SUBVECTOR second source must be a register", MI);
1795 break;
1796 }
1797
1799 if (!IndexOp.isImm()) {
1800 report("G_INSERT_SUBVECTOR index must be an immediate", MI);
1801 break;
1802 }
1803
1804 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1806
1808 report("Destination type must be a vector", MI);
1809 break;
1810 }
1811
1813 report("Second source must be a vector", MI);
1814 break;
1815 }
1816
1818 report("Element type of vectors must be the same", MI);
1819 break;
1820 }
1821
1823 report("Vector types must both be fixed or both be scalable", MI);
1824 break;
1825 }
1826
1829 report("Second source must be smaller than destination vector", MI);
1830 break;
1831 }
1832
1833 uint64_t Idx = IndexOp.getImm();
1835 if (IndexOp.getImm() % Src1MinLen != 0) {
1836 report("Index must be a multiple of the second source vector's "
1837 "minimum vector length",
1838 MI);
1839 break;
1840 }
1841
1843 if (Idx >= DstMinLen || Idx + Src1MinLen > DstMinLen) {
1844 report("Subvector type and index must not cause insert to overrun the "
1845 "vector being inserted into",
1846 MI);
1847 break;
1848 }
1849
1850 break;
1851 }
1852 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1854 if (.isReg()) {
1855 report("G_EXTRACT_SUBVECTOR first source must be a register", MI);
1856 break;
1857 }
1858
1860 if (!IndexOp.isImm()) {
1861 report("G_EXTRACT_SUBVECTOR index must be an immediate", MI);
1862 break;
1863 }
1864
1865 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1867
1869 report("Destination type must be a vector", MI);
1870 break;
1871 }
1872
1874 report("Source must be a vector", MI);
1875 break;
1876 }
1877
1879 report("Element type of vectors must be the same", MI);
1880 break;
1881 }
1882
1884 report("Vector types must both be fixed or both be scalable", MI);
1885 break;
1886 }
1887
1890 report("Destination vector must be smaller than source vector", MI);
1891 break;
1892 }
1893
1894 uint64_t Idx = IndexOp.getImm();
1896 if (Idx % DstMinLen != 0) {
1897 report("Index must be a multiple of the destination vector's minimum "
1898 "vector length",
1899 MI);
1900 break;
1901 }
1902
1904 if (Idx >= SrcMinLen || Idx + DstMinLen > SrcMinLen) {
1905 report("Destination type and index must not cause extract to overrun the "
1906 "source vector",
1907 MI);
1908 break;
1909 }
1910
1911 break;
1912 }
1913 case TargetOpcode::G_SHUFFLE_VECTOR: {
1916 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1917 break;
1918 }
1919
1920 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1921 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1922 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1923
1924 if (Src0Ty != Src1Ty)
1925 report("Source operands must be the same type", MI);
1926
1928 report("G_SHUFFLE_VECTOR cannot change element type", MI);
1929 break;
1930 }
1932 report("G_SHUFFLE_VECTOR must have vector src", MI);
1933 break;
1934 }
1936 report("G_SHUFFLE_VECTOR must have vector dst", MI);
1937 break;
1938 }
1939
1940
1941
1944
1946
1947 if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1948 report("Wrong result type for shufflemask", MI);
1949
1950 for (int Idx : MaskIdxes) {
1951 if (Idx < 0)
1952 continue;
1953
1954 if (Idx >= 2 * SrcNumElts)
1955 report("Out of bounds shuffle index", MI);
1956 }
1957
1958 break;
1959 }
1960
1961 case TargetOpcode::G_SPLAT_VECTOR: {
1962 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1963 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1964
1966 report("Destination type must be a scalable vector", MI);
1967 break;
1968 }
1969
1971 report("Source type must be a scalar or pointer", MI);
1972 break;
1973 }
1974
1977 report("Element type of the destination must be the same size or smaller "
1978 "than the source type",
1979 MI);
1980 break;
1981 }
1982
1983 break;
1984 }
1985 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1986 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1987 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1988 LLT IdxTy = MRI->getType(MI->getOperand(2).getReg());
1989
1991 report("Destination type must be a scalar or pointer", MI);
1992 break;
1993 }
1994
1996 report("First source must be a vector", MI);
1997 break;
1998 }
1999
2000 auto TLI = MF->getSubtarget().getTargetLowering();
2001 if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
2002 report("Index type must match VectorIdxTy", MI);
2003 break;
2004 }
2005
2006 break;
2007 }
2008 case TargetOpcode::G_INSERT_VECTOR_ELT: {
2009 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2010 LLT VecTy = MRI->getType(MI->getOperand(1).getReg());
2011 LLT ScaTy = MRI->getType(MI->getOperand(2).getReg());
2012 LLT IdxTy = MRI->getType(MI->getOperand(3).getReg());
2013
2015 report("Destination type must be a vector", MI);
2016 break;
2017 }
2018
2019 if (VecTy != DstTy) {
2020 report("Destination type and vector type must match", MI);
2021 break;
2022 }
2023
2025 report("Inserted element must be a scalar or pointer", MI);
2026 break;
2027 }
2028
2029 auto TLI = MF->getSubtarget().getTargetLowering();
2030 if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
2031 report("Index type must match VectorIdxTy", MI);
2032 break;
2033 }
2034
2035 break;
2036 }
2037 case TargetOpcode::G_DYN_STACKALLOC: {
2041
2043 report("dst operand 0 must be a pointer type", MI);
2044 break;
2045 }
2046
2047 if (!AllocOp.isReg() || ->getType(AllocOp.getReg()).isScalar()) {
2048 report("src operand 1 must be a scalar reg type", MI);
2049 break;
2050 }
2051
2052 if (!AlignOp.isImm()) {
2053 report("src operand 2 must be an immediate type", MI);
2054 break;
2055 }
2056 break;
2057 }
2058 case TargetOpcode::G_MEMCPY_INLINE:
2059 case TargetOpcode::G_MEMCPY:
2060 case TargetOpcode::G_MEMMOVE: {
2062 if (MMOs.size() != 2) {
2063 report("memcpy/memmove must have 2 memory operands", MI);
2064 break;
2065 }
2066
2067 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
2069 report("wrong memory operand types", MI);
2070 break;
2071 }
2072
2074 report("inconsistent memory operand sizes", MI);
2075
2076 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
2077 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
2078
2080 report("memory instruction operand must be a pointer", MI);
2081 break;
2082 }
2083
2084 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
2085 report("inconsistent store address space", MI);
2086 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
2087 report("inconsistent load address space", MI);
2088
2089 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
2090 if (->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
2091 report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
2092
2093 break;
2094 }
2095 case TargetOpcode::G_BZERO:
2096 case TargetOpcode::G_MEMSET: {
2098 std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
2099 if (MMOs.size() != 1) {
2100 report(Twine(Name, " must have 1 memory operand"), MI);
2101 break;
2102 }
2103
2104 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
2105 report(Twine(Name, " memory operand must be a store"), MI);
2106 break;
2107 }
2108
2109 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
2111 report(Twine(Name, " operand must be a pointer"), MI);
2112 break;
2113 }
2114
2115 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
2116 report("inconsistent " + Twine(Name, " address space"), MI);
2117
2118 if (->getOperand(MI->getNumOperands() - 1).isImm() ||
2119 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
2120 report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
2121
2122 break;
2123 }
2124 case TargetOpcode::G_UBSANTRAP: {
2126 if (->getOperand(0).isImm()) {
2127 report("Crash kind must be an immediate", &KindOp, 0);
2128 break;
2129 }
2130 int64_t Kind = MI->getOperand(0).getImm();
2132 report("Crash kind must be 8 bit wide", &KindOp, 0);
2133 break;
2134 }
2135 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
2136 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
2137 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2138 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
2139 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
2141 report("Vector reduction requires a scalar destination type", MI);
2143 report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
2145 report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
2146 break;
2147 }
2148 case TargetOpcode::G_VECREDUCE_FADD:
2149 case TargetOpcode::G_VECREDUCE_FMUL:
2150 case TargetOpcode::G_VECREDUCE_FMAX:
2151 case TargetOpcode::G_VECREDUCE_FMIN:
2152 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
2153 case TargetOpcode::G_VECREDUCE_FMINIMUM:
2154 case TargetOpcode::G_VECREDUCE_ADD:
2155 case TargetOpcode::G_VECREDUCE_MUL:
2156 case TargetOpcode::G_VECREDUCE_AND:
2157 case TargetOpcode::G_VECREDUCE_OR:
2158 case TargetOpcode::G_VECREDUCE_XOR:
2159 case TargetOpcode::G_VECREDUCE_SMAX:
2160 case TargetOpcode::G_VECREDUCE_SMIN:
2161 case TargetOpcode::G_VECREDUCE_UMAX:
2162 case TargetOpcode::G_VECREDUCE_UMIN: {
2163 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2165 report("Vector reduction requires a scalar destination type", MI);
2166 break;
2167 }
2168
2169 case TargetOpcode::G_SBFX:
2170 case TargetOpcode::G_UBFX: {
2171 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2173 report("Bitfield extraction is not supported on vectors", MI);
2174 break;
2175 }
2176 break;
2177 }
2178 case TargetOpcode::G_SHL:
2179 case TargetOpcode::G_LSHR:
2180 case TargetOpcode::G_ASHR:
2181 case TargetOpcode::G_ROTR:
2182 case TargetOpcode::G_ROTL: {
2183 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
2184 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
2186 report("Shifts and rotates require operands to be either all scalars or "
2187 "all vectors",
2188 MI);
2189 break;
2190 }
2191 break;
2192 }
2193 case TargetOpcode::G_LLROUND:
2194 case TargetOpcode::G_LROUND: {
2195 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2196 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
2198 break;
2201 report(Twine(Op, " operand must not be a pointer type"), MI);
2202 } else if (SrcTy.isScalar()) {
2203 verifyAllRegOpsScalar(*MI, *MRI);
2204 break;
2205 } else if (SrcTy.isVector()) {
2206 verifyVectorElementMatch(SrcTy, DstTy, MI);
2207 break;
2208 }
2209 break;
2210 }
2211 case TargetOpcode::G_IS_FPCLASS: {
2212 LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
2214 if (!DestEltTy.isScalar()) {
2215 report("Destination must be a scalar or vector of scalars", MI);
2216 break;
2217 }
2218 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
2221 report("Source must be a scalar or vector of scalars", MI);
2222 break;
2223 }
2224 if (!verifyVectorElementMatch(DestTy, SrcTy, MI))
2225 break;
2227 if (!TestMO.isImm()) {
2228 report("floating-point class set (operand 2) must be an immediate", MI);
2229 break;
2230 }
2233 report("Incorrect floating-point class set (operand 2)", MI);
2234 break;
2235 }
2236 break;
2237 }
2238 case TargetOpcode::G_PREFETCH: {
2240 if (!AddrOp.isReg() || ->getType(AddrOp.getReg()).isPointer()) {
2241 report("addr operand must be a pointer", &AddrOp, 0);
2242 break;
2243 }
2245 if (!RWOp.isImm() || (uint64_t)RWOp.getImm() >= 2) {
2246 report("rw operand must be an immediate 0-1", &RWOp, 1);
2247 break;
2248 }
2250 if (!LocalityOp.isImm() || (uint64_t)LocalityOp.getImm() >= 4) {
2251 report("locality operand must be an immediate 0-3", &LocalityOp, 2);
2252 break;
2253 }
2255 if (!CacheTypeOp.isImm() || (uint64_t)CacheTypeOp.getImm() >= 2) {
2256 report("cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
2257 break;
2258 }
2259 break;
2260 }
2261 case TargetOpcode::G_ASSERT_ALIGN: {
2262 if (MI->getOperand(2).getImm() < 1)
2263 report("alignment immediate must be >= 1", MI);
2264 break;
2265 }
2266 case TargetOpcode::G_CONSTANT_POOL: {
2267 if (->getOperand(1).isCPI())
2268 report("Src operand 1 must be a constant pool index", MI);
2269 if (->getType(MI->getOperand(0).getReg()).isPointer())
2270 report("Dst operand 0 must be a pointer", MI);
2271 break;
2272 }
2273 case TargetOpcode::G_PTRAUTH_GLOBAL_VALUE: {
2275 if (!AddrOp.isReg() || ->getType(AddrOp.getReg()).isPointer())
2276 report("addr operand must be a pointer", &AddrOp, 1);
2277 break;
2278 }
2279 default:
2280 break;
2281 }
2282}
2283
2284void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
2286 if (MI->getNumOperands() < MCID.getNumOperands()) {
2287 report("Too few operands", MI);
2288 OS << MCID.getNumOperands() << " operands expected, but "
2289 << MI->getNumOperands() << " given.\n";
2290 }
2291
2293 report("NoConvergent flag expected only on convergent instructions.", MI);
2294
2295 if (MI->isPHI()) {
2296 if (MF->getProperties().hasNoPHIs())
2297 report("Found PHI instruction with NoPHIs property set", MI);
2298
2299 if (FirstNonPHI)
2300 report("Found PHI instruction after non-PHI", MI);
2301 } else if (FirstNonPHI == nullptr)
2302 FirstNonPHI = MI;
2303
2304
2305 if (MI->isInlineAsm())
2306 verifyInlineAsm(MI);
2307
2308
2310 if (->getOperand(0).isReg() ||
->getOperand(0).isDef())
2311 report("Unspillable Terminator does not define a reg", MI);
2313 if (Def.isVirtual() && !MF->getProperties().hasNoPHIs() &&
2314 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
2315 report("Unspillable Terminator expected to have at most one use!", MI);
2316 }
2317
2318
2319
2320
2321 if (MI->isDebugValue() && MI->getNumOperands() == 4)
2322 if (->getDebugLoc())
2323 report("Missing DebugLoc for debug instruction", MI);
2324
2325
2326
2327 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
2328 report("Metadata instruction should not have a value tracking number", MI);
2329
2330
2332 if (Op->isLoad() && ->mayLoad())
2333 report("Missing mayLoad flag", MI);
2334 if (Op->isStore() && ->mayStore())
2335 report("Missing mayStore flag", MI);
2336 }
2337
2338
2339
2340 if (LiveInts) {
2341 bool mapped = !LiveInts->isNotInMIMap(*MI);
2342 if (MI->isDebugOrPseudoInstr()) {
2343 if (mapped)
2344 report("Debug instruction has a slot index", MI);
2345 } else if (MI->isInsideBundle()) {
2346 if (mapped)
2347 report("Instruction inside bundle has a slot index", MI);
2348 } else {
2349 if (!mapped)
2350 report("Missing slot index", MI);
2351 }
2352 }
2353
2354 unsigned Opc = MCID.getOpcode();
2356 verifyPreISelGenericInstruction(MI);
2357 return;
2358 }
2359
2363
2364
2365 switch (MI->getOpcode()) {
2366 case TargetOpcode::COPY: {
2371
2372 LLT DstTy = MRI->getType(DstReg);
2373 LLT SrcTy = MRI->getType(SrcReg);
2375
2376 if (SrcTy != DstTy) {
2377 report("Copy Instruction is illegal with mismatching types", MI);
2378 OS << "Def = " << DstTy << ", Src = " << SrcTy << '\n';
2379 }
2380
2381 break;
2382 }
2383
2385 break;
2386
2387
2388
2393 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2394 if (!SrcRC)
2395 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
2396 } else {
2397 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
2398 }
2399
2402 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2403 if (!DstRC)
2404 DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
2405 } else {
2406 DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
2407 }
2408
2409
2410
2411
2412
2413
2414
2415
2418 break;
2421 break;
2422
2423 if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
2424 if (.getSubReg() &&
.getSubReg()) {
2425 report("Copy Instruction is illegal with mismatching sizes", MI);
2426 OS << "Def Size = " << DstSize << ", Src Size = " << SrcSize << '\n';
2427 }
2428 }
2429 break;
2430 }
2431 case TargetOpcode::COPY_LANEMASK: {
2438
2439 if (DstOp.getSubReg())
2440 report("COPY_LANEMASK must not use a subregister index", &DstOp, 0);
2441
2442 if (SrcOp.getSubReg())
2443 report("COPY_LANEMASK must not use a subregister index", &SrcOp, 1);
2444
2445 if (LaneMask.none())
2446 report("COPY_LANEMASK must read at least one lane", MI);
2447
2450 if (SrcRC)
2452 } else {
2453 SrcMaxLaneMask = MRI->getMaxLaneMaskForVReg(SrcReg);
2454 }
2455
2456
2457
2458 if (SrcMaxLaneMask == LaneMask)
2459 report("COPY_LANEMASK cannot be used to do full copy", MI);
2460
2461
2462
2463
2464 if (SrcMaxLaneMask < LaneMask)
2465 report("COPY_LANEMASK attempts to read from the lanes that "
2466 "don't exist in the source register",
2467 MI);
2468
2469 break;
2470 }
2471 case TargetOpcode::STATEPOINT: {
2473 if (->getOperand(SO.getIDPos()).isImm() ||
2474 ->getOperand(SO.getNBytesPos()).isImm() ||
2475 ->getOperand(SO.getNCallArgsPos()).isImm()) {
2476 report("meta operands to STATEPOINT not constant!", MI);
2477 break;
2478 }
2479
2480 auto VerifyStackMapConstant = [&](unsigned Offset) {
2481 if (Offset >= MI->getNumOperands()) {
2482 report("stack map constant to STATEPOINT is out of range!", MI);
2483 return;
2484 }
2485 if (->getOperand(Offset - 1).isImm() ||
2486 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
2487 ->getOperand(Offset).isImm())
2488 report("stack map constant to STATEPOINT not well formed!", MI);
2489 };
2490 VerifyStackMapConstant(SO.getCCIdx());
2491 VerifyStackMapConstant(SO.getFlagsIdx());
2492 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2493 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2494 VerifyStackMapConstant(SO.getNumAllocaIdx());
2495 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2496
2497
2498
2499 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2500 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2501 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
2502 unsigned UseOpIdx;
2503 if (->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
2504 report("STATEPOINT defs expected to be tied", MI);
2505 break;
2506 }
2507 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2508 report("STATEPOINT def tied to non-gc operand", MI);
2509 break;
2510 }
2511 }
2512
2513
2514 } break;
2515 case TargetOpcode::INSERT_SUBREG: {
2516 unsigned InsertedSize;
2517 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
2518 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
2519 else
2520 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
2521 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
2522 if (SubRegSize < InsertedSize) {
2523 report("INSERT_SUBREG expected inserted value to have equal or lesser "
2524 "size than the subreg it was inserted into", MI);
2525 break;
2526 }
2527 } break;
2528 case TargetOpcode::REG_SEQUENCE: {
2529 unsigned NumOps = MI->getNumOperands();
2530 if (!(NumOps & 1)) {
2531 report("Invalid number of operands for REG_SEQUENCE", MI);
2532 break;
2533 }
2534
2535 for (unsigned I = 1; I != NumOps; I += 2) {
2538
2539 if (!RegOp.isReg())
2540 report("Invalid register operand for REG_SEQUENCE", &RegOp, I);
2541
2542 if (!SubRegOp.isImm() || SubRegOp.getImm() == 0 ||
2543 SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
2544 report("Invalid subregister index operand for REG_SEQUENCE",
2545 &SubRegOp, I + 1);
2546 }
2547 }
2548
2549 Register DstReg = MI->getOperand(0).getReg();
2551 report("REG_SEQUENCE does not support physical register results", MI);
2552
2553 if (MI->getOperand(0).getSubReg())
2554 report("Invalid subreg result for REG_SEQUENCE", MI);
2555
2556 break;
2557 }
2558 }
2559}
2560
2561void
2562MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
2565 unsigned NumDefs = MCID.getNumDefs();
2566 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
2567 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
2568
2569
2570 if (MONum < NumDefs) {
2572 if (!MO->isReg())
2573 report("Explicit definition must be a register", MO, MONum);
2574 else if (!MO->isDef() && .isOptionalDef())
2575 report("Explicit definition marked as use", MO, MONum);
2577 report("Explicit definition marked as implicit", MO, MONum);
2578 } else if (MONum < MCID.getNumOperands()) {
2580
2581
2582 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
2583 if (!IsOptional) {
2584 if (MO->isReg()) {
2585 if (MO->isDef() && .isOptionalDef() &&
.variadicOpsAreDefs())
2586 report("Explicit operand marked as def", MO, MONum);
2588 report("Explicit operand marked as implicit", MO, MONum);
2589 }
2590
2591
2594 report("Expected a register operand.", MO, MONum);
2595 if (MO->isReg()) {
2599 report("Expected a non-register operand.", MO, MONum);
2600 }
2601 }
2602
2604 if (TiedTo != -1) {
2605 if (!MO->isReg())
2606 report("Tied use must be a register", MO, MONum);
2607 else if (!MO->isTied())
2608 report("Operand should be tied", MO, MONum);
2609 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2610 report("Tied def doesn't match MCInstrDesc", MO, MONum);
2613 if (!MOTied.isReg())
2614 report("Tied counterpart must be a register", &MOTied, TiedTo);
2617 report("Tied physical registers must match.", &MOTied, TiedTo);
2618 }
2620 report("Explicit operand should not be tied", MO, MONum);
2621 } else if (->isVariadic()) {
2622
2624 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2625 }
2626
2627
2629 if (!MO->isReg())
2630 report("Early clobber must be a register", MI);
2632 report("Missing earlyClobber flag", MI);
2633 }
2634
2635 switch (MO->getType()) {
2637
2638
2639 if (MI->isDebugInstr() && MO->isUse()) {
2641 report("Register operand must be marked debug", MO, MONum);
2642 } else if (MO->isDebug()) {
2643 report("Register operand must not be marked debug", MO, MONum);
2644 }
2645
2647 if ()
2648 return;
2649 if (MRI->tracksLiveness() && ->isDebugInstr())
2650 checkLiveness(MO, MONum);
2651
2653 MO->getReg().isVirtual())
2654 report("Undef virtual register def operands require a subregister", MO, MONum);
2655
2656
2658 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2660 if (!OtherMO.isReg())
2661 report("Must be tied to a register", MO, MONum);
2662 if (!OtherMO.isTied())
2663 report("Missing tie flags on tied operand", MO, MONum);
2664 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2665 report("Inconsistent tie links", MO, MONum);
2666 if (MONum < MCID.getNumDefs()) {
2667 if (OtherIdx < MCID.getNumOperands()) {
2669 report("Explicit def tied to explicit use without tie constraint",
2670 MO, MONum);
2671 } else {
2673 report("Explicit def should be tied to implicit use", MO, MONum);
2674 }
2675 }
2676 }
2677
2678
2679
2680
2681
2682
2683
2684
2685 unsigned DefIdx;
2686 if (MF->getProperties().hasTiedOpsRewritten() && MO->isUse() &&
2687 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2688 Reg != MI->getOperand(DefIdx).getReg())
2689 report("Two-address instruction operands must be identical", MO, MONum);
2690
2691
2692 unsigned SubIdx = MO->getSubReg();
2693
2695 if (SubIdx) {
2696 report("Illegal subregister index for physical register", MO, MONum);
2697 return;
2698 }
2699 if (MONum < MCID.getNumOperands()) {
2701 if (!DRC->contains(Reg)) {
2702 report("Illegal physical register for instruction", MO, MONum);
2704 << TRI->getRegClassName(DRC) << " register.\n";
2705 }
2706 }
2707 }
2709 if (MRI->isReserved(Reg)) {
2710 report("isRenamable set on reserved register", MO, MONum);
2711 return;
2712 }
2713 }
2714 } else {
2715
2717 if (!RC) {
2718
2719
2720
2721
2722
2723
2724
2725
2727 report("Generic virtual register use cannot be undef", MO, MONum);
2728
2729
2730
2731
2732
2733
2734 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2735 ->isDebugValue() ||
->def_empty(Reg)) {
2736
2737 if (isFunctionSelected) {
2738 report("Generic virtual register invalid in a Selected function",
2739 MO, MONum);
2740 return;
2741 }
2742
2743
2746 report("Generic virtual register must have a valid type", MO,
2747 MONum);
2748 return;
2749 }
2750
2752 const RegisterBankInfo *RBI = MF->getSubtarget().getRegBankInfo();
2753
2754
2755 if (!RegBank && isFunctionRegBankSelected) {
2756 report("Generic virtual register must have a bank in a "
2757 "RegBankSelected function",
2758 MO, MONum);
2759 return;
2760 }
2761
2762
2765 report("Register bank is too small for virtual register", MO,
2766 MONum);
2767 OS << "Register bank " << RegBank->getName() << " too small("
2770 return;
2771 }
2772 }
2773
2774 if (SubIdx) {
2775 report("Generic virtual register does not allow subregister index", MO,
2776 MONum);
2777 return;
2778 }
2779
2780
2781
2782
2785 report("Virtual register does not match instruction constraint", MO,
2786 MONum);
2787 OS << "Expect register class "
2789 << " but got nothing\n";
2790 return;
2791 }
2792
2793 break;
2794 }
2795 if (SubIdx) {
2797 TRI->getSubClassWithSubReg(RC, SubIdx);
2798 if (!SRC) {
2799 report("Invalid subregister index for virtual register", MO, MONum);
2800 OS << "Register class " << TRI->getRegClassName(RC)
2801 << " does not support subreg index "
2802 << TRI->getSubRegIndexName(SubIdx) << '\n';
2803 return;
2804 }
2805 if (RC != SRC) {
2806 report("Invalid register class for subregister index", MO, MONum);
2807 OS << "Register class " << TRI->getRegClassName(RC)
2808 << " does not fully support subreg index "
2809 << TRI->getSubRegIndexName(SubIdx) << '\n';
2810 return;
2811 }
2812 }
2813 if (MONum < MCID.getNumOperands()) {
2815 if (SubIdx) {
2817 TRI->getLargestLegalSuperClass(RC, *MF);
2818 if (!SuperRC) {
2819 report("No largest legal super class exists.", MO, MONum);
2820 return;
2821 }
2822 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2823 if (!DRC) {
2824 report("No matching super-reg register class.", MO, MONum);
2825 return;
2826 }
2827 }
2829 report("Illegal virtual register for instruction", MO, MONum);
2830 OS << "Expected a " << TRI->getRegClassName(DRC)
2831 << " register, but got a " << TRI->getRegClassName(RC)
2832 << " register\n";
2833 }
2834 }
2835 }
2836 }
2837 break;
2838 }
2839
2841 regMasks.push_back(MO->getRegMask());
2842 break;
2843
2846 report("PHI operand is not in the CFG", MO, MONum);
2847 break;
2848
2850 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2851 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2853 LiveInterval &LI = LiveStks->getInterval(FI);
2854 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2855
2856 bool stores = MI->mayStore();
2857 bool loads = MI->mayLoad();
2858
2859
2860
2862 for (auto *MMO : MI->memoperands()) {
2864 if (PSV == nullptr) continue;
2867 if (Value == nullptr) continue;
2868 if (Value->getFrameIndex() != FI) continue;
2869
2872 else
2874 break;
2875 }
2877 report("Missing fixed stack memoperand.", MI);
2878 }
2880 report("Instruction loads from dead spill slot", MO, MONum);
2881 OS << "Live stack: " << LI << '\n';
2882 }
2884 report("Instruction stores to dead spill slot", MO, MONum);
2885 OS << "Live stack: " << LI << '\n';
2886 }
2887 }
2888 break;
2889
2891 if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2892 report("CFI instruction has invalid index", MO, MONum);
2893 break;
2894
2895 default:
2896 break;
2897 }
2898}
2899
2900void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2901 unsigned MONum, SlotIndex UseIdx,
2906
2908 report("invalid live range", MO, MONum);
2909 report_context_liverange(LR);
2910 report_context_vreg_regunit(VRegOrUnit);
2911 report_context(UseIdx);
2912 return;
2913 }
2914
2917
2918
2920 report("No live segment at use", MO, MONum);
2921 report_context_liverange(LR);
2922 report_context_vreg_regunit(VRegOrUnit);
2923 report_context(UseIdx);
2924 }
2926 report("Live range continues after kill flag", MO, MONum);
2927 report_context_liverange(LR);
2928 report_context_vreg_regunit(VRegOrUnit);
2929 if (LaneMask.any())
2930 report_context_lanemask(LaneMask);
2931 report_context(UseIdx);
2932 }
2933}
2934
2935void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2936 unsigned MONum, SlotIndex DefIdx,
2939 bool SubRangeCheck,
2942 report("invalid live range", MO, MONum);
2943 report_context_liverange(LR);
2944 report_context_vreg_regunit(VRegOrUnit);
2945 if (LaneMask.any())
2946 report_context_lanemask(LaneMask);
2947 report_context(DefIdx);
2948 }
2949
2951
2952
2953
2954
2955
2956
2957
2958
2959 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2961 (VNI->def != DefIdx &&
2962 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2963 report("Inconsistent valno->def", MO, MONum);
2964 report_context_liverange(LR);
2965 report_context_vreg_regunit(VRegOrUnit);
2966 if (LaneMask.any())
2967 report_context_lanemask(LaneMask);
2968 report_context(*VNI);
2969 report_context(DefIdx);
2970 }
2971 } else {
2972 report("No live segment at def", MO, MONum);
2973 report_context_liverange(LR);
2974 report_context_vreg_regunit(VRegOrUnit);
2975 if (LaneMask.any())
2976 report_context_lanemask(LaneMask);
2977 report_context(DefIdx);
2978 }
2979
2983 assert(VRegOrUnit.isVirtualReg() && "Expecting a virtual register.");
2984
2985
2986
2987
2988
2989 if (SubRangeCheck || MO->getSubReg() == 0) {
2990 report("Live range continues after dead def flag", MO, MONum);
2991 report_context_liverange(LR);
2992 report_context_vreg_regunit(VRegOrUnit);
2993 if (LaneMask.any())
2994 report_context_lanemask(LaneMask);
2995 }
2996 }
2997 }
2998}
2999
3000void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
3003 const unsigned SubRegIdx = MO->getSubReg();
3004
3007 if (LiveInts->hasInterval(Reg)) {
3008 LI = &LiveInts->getInterval(Reg);
3009 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
3011 report("Live interval for subreg operand has no subranges", MO, MONum);
3012 } else {
3013 report("Virtual register has no live interval", MO, MONum);
3014 }
3015 }
3016
3017
3020 addRegWithSubRegs(regsKilled, Reg);
3021
3022
3023
3024
3026 ->isBundledWithPred()) {
3029 report("Kill missing from LiveVariables", MO, MONum);
3030 }
3031
3032
3033 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
3035 if (MI->isPHI()) {
3036
3037 UseIdx = LiveInts->getMBBEndIdx(
3038 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
3039 } else {
3040 UseIdx = LiveInts->getInstructionIndex(*MI);
3041 }
3042
3044 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
3045 if (MRI->isReservedRegUnit(Unit))
3046 continue;
3047 if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
3048 checkLivenessAtUse(MO, MONum, UseIdx, *LR, VirtRegOrUnit(Unit));
3049 }
3050 }
3051
3053
3054 checkLivenessAtUse(MO, MONum, UseIdx, *LI, VirtRegOrUnit(Reg));
3055
3058 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
3059 : MRI->getMaxLaneMaskForVReg(Reg);
3062 if ((MOMask & SR.LaneMask).none())
3063 continue;
3064 checkLivenessAtUse(MO, MONum, UseIdx, SR, VirtRegOrUnit(Reg),
3065 SR.LaneMask);
3068 LiveInMask |= SR.LaneMask;
3069 }
3070
3071 if ((LiveInMask & MOMask).none()) {
3072 report("No live subrange at use", MO, MONum);
3073 report_context(*LI);
3074 report_context(UseIdx);
3075 }
3076
3077 if (MI->isPHI() && LiveInMask != MOMask) {
3078 report("Not all lanes of PHI source live at use", MO, MONum);
3079 report_context(*LI);
3080 report_context(UseIdx);
3081 }
3082 }
3083 }
3084 }
3085
3086
3087 if (!regsLive.count(Reg)) {
3089
3090 bool Bad = !isReserved(Reg);
3091
3092 if (Bad) {
3093
3095 if (regsLive.count(SubReg)) {
3096 Bad = false;
3097 break;
3098 }
3099 }
3100 }
3101
3102
3103
3104
3105 if (Bad) {
3107 if (!MOP.isReg() || !MOP.isImplicit())
3108 continue;
3109
3110 if (!MOP.getReg().isPhysical())
3111 continue;
3112
3113 if (MOP.getReg() != Reg &&
3114 all_of(TRI->regunits(Reg), [&](const MCRegUnit RegUnit) {
3115 return llvm::is_contained(TRI->regunits(MOP.getReg()),
3116 RegUnit);
3117 }))
3118 Bad = false;
3119 }
3120 }
3121 if (Bad)
3122 report("Using an undefined physical register", MO, MONum);
3123 } else if (MRI->def_empty(Reg)) {
3124 report("Reading virtual register without a def", MO, MONum);
3125 } else {
3126 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
3127
3128
3129
3130 if (MInfo.regsKilled.count(Reg))
3131 report("Using a killed virtual register", MO, MONum);
3132 else if (->isPHI())
3133 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
3134 }
3135 }
3136 }
3137
3138 if (MO->isDef()) {
3139
3140
3142 addRegWithSubRegs(regsDead, Reg);
3143 else
3144 addRegWithSubRegs(regsDefined, Reg);
3145
3146
3148 std::next(MRI->def_begin(Reg)) != MRI->def_end())
3149 report("Multiple virtual register defs in SSA form", MO, MONum);
3150
3151
3152 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
3153 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
3155
3157 checkLivenessAtDef(MO, MONum, DefIdx, *LI, VirtRegOrUnit(Reg));
3158
3161 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
3162 : MRI->getMaxLaneMaskForVReg(Reg);
3164 if ((SR.LaneMask & MOMask).none())
3165 continue;
3166 checkLivenessAtDef(MO, MONum, DefIdx, SR, VirtRegOrUnit(Reg), true,
3167 SR.LaneMask);
3168 }
3169 }
3170 }
3171 }
3172 }
3173}
3174
3175
3176
3177
3178
3179void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
3180 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
3181 set_union(MInfo.regsKilled, regsKilled);
3182 set_subtract(regsLive, regsKilled); regsKilled.clear();
3183
3184 while (!regMasks.empty()) {
3185 const uint32_t *Mask = regMasks.pop_back_val();
3189 regsDead.push_back(Reg);
3190 }
3191 set_subtract(regsLive, regsDead); regsDead.clear();
3192 set_union(regsLive, regsDefined); regsDefined.clear();
3193}
3194
3195void
3197 MBBInfoMap[MBB].regsLiveOut = regsLive;
3198 regsLive.clear();
3199
3200 if (Indexes) {
3201 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
3202 if (!(stop > lastIndex)) {
3203 report("Block ends before last instruction index", MBB);
3204 OS << "Block ends at " << stop << " last instruction was at " << lastIndex
3205 << '\n';
3206 }
3207 lastIndex = stop;
3208 }
3209}
3210
3211namespace {
3212
3213
3214
3215
3216
3217struct VRegFilter {
3218
3219
3220 template void add(const RegSetT &FromRegSet) {
3222 filterAndAdd(FromRegSet, VRegsBuffer);
3223 }
3224
3225
3226
3227 template
3228 bool filterAndAdd(const RegSetT &FromRegSet,
3229 SmallVectorImpl &ToVRegs) {
3230 unsigned SparseUniverse = Sparse.size();
3231 unsigned NewSparseUniverse = SparseUniverse;
3232 unsigned NewDenseSize = Dense.size();
3233 size_t Begin = ToVRegs.size();
3236 continue;
3238 if (Index < SparseUniverseMax) {
3239 if (Index < SparseUniverse && Sparse.test(Index))
3240 continue;
3241 NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
3242 } else {
3244 continue;
3245 ++NewDenseSize;
3246 }
3248 }
3249 size_t End = ToVRegs.size();
3250 if (Begin == End)
3251 return false;
3252
3253
3254
3255
3256 Sparse.resize(NewSparseUniverse);
3257 Dense.reserve(NewDenseSize);
3258 for (unsigned I = Begin; I < End; ++I) {
3261 if (Index < SparseUniverseMax)
3262 Sparse.set(Index);
3263 else
3265 }
3266 return true;
3267 }
3268
3269private:
3270 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280 BitVector Sparse;
3281 DenseSet Dense;
3282};
3283
3284
3285
3286
3287
3288
3289
3290class FilteringVRegSet {
3293
3294public:
3295
3296
3297 template void addToFilter(const RegSetT &RS) {
3299 }
3300
3301
3302 template bool add(const RegSetT &RS) {
3303
3304
3305 return Filter.filterAndAdd(RS, VRegs);
3306 }
3307 using const_iterator = decltype(VRegs)::const_iterator;
3308 const_iterator begin() const { return VRegs.begin(); }
3309 const_iterator end() const { return VRegs.end(); }
3310 size_t size() const { return VRegs.size(); }
3311};
3312}
3313
3314
3315
3316
3317void MachineVerifier::calcRegsPassed() {
3318 if (MF->empty())
3319
3320 return;
3321
3324 FilteringVRegSet VRegs;
3325 BBInfo &Info = MBBInfoMap[MB];
3327
3328 VRegs.addToFilter(Info.regsKilled);
3329 VRegs.addToFilter(Info.regsLiveOut);
3331 const BBInfo &PredInfo = MBBInfoMap[Pred];
3332 if (!PredInfo.reachable)
3333 continue;
3334
3335 VRegs.add(PredInfo.regsLiveOut);
3336 VRegs.add(PredInfo.vregsPassed);
3337 }
3338 Info.vregsPassed.reserve(VRegs.size());
3339 Info.vregsPassed.insert_range(VRegs);
3340 }
3341}
3342
3343
3344
3345
3346void MachineVerifier::calcRegsRequired() {
3347
3349 for (const auto &MBB : *MF) {
3350 BBInfo &MInfo = MBBInfoMap[&MBB];
3352 BBInfo &PInfo = MBBInfoMap[Pred];
3353 if (PInfo.addRequired(MInfo.vregsLiveIn))
3355 }
3356
3357
3359 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
3360
3361 if (.getOperand(i).isReg() ||
.getOperand(i).readsReg())
3362 continue;
3363
3364
3367
3368 BBInfo &PInfo = MBBInfoMap[Pred];
3369 if (PInfo.addRequired(Reg))
3371 }
3372 }
3373 }
3374
3375
3376
3377 while (!todo.empty()) {
3380 BBInfo &MInfo = MBBInfoMap[MBB];
3382 if (Pred == MBB)
3383 continue;
3384 BBInfo &SInfo = MBBInfoMap[Pred];
3385 if (SInfo.addRequired(MInfo.vregsRequired))
3387 }
3388 }
3389}
3390
3391
3392
3394 BBInfo &MInfo = MBBInfoMap[&MBB];
3395
3398 if (.isPHI())
3399 break;
3401
3403 if (!MODef.isReg() || !MODef.isDef()) {
3404 report("Expected first PHI operand to be a register def", &MODef, 0);
3405 continue;
3406 }
3409 report("Unexpected flag on PHI operand", &MODef, 0);
3412 report("Expected first PHI operand to be a virtual register", &MODef, 0);
3413
3414 for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
3416 if (!MO0.isReg()) {
3417 report("Expected PHI operand to be a register", &MO0, I);
3418 continue;
3419 }
3422 report("Unexpected flag on PHI operand", &MO0, I);
3423
3425 if (!MO1.isMBB()) {
3426 report("Expected PHI operand to be a basic block", &MO1, I + 1);
3427 continue;
3428 }
3429
3432 report("PHI input is not a predecessor block", &MO1, I + 1);
3433 continue;
3434 }
3435
3436 if (MInfo.reachable) {
3438 BBInfo &PrInfo = MBBInfoMap[&Pre];
3439 if (!MO0.isUndef() && PrInfo.reachable &&
3440 !PrInfo.isLiveOut(MO0.getReg()))
3441 report("PHI operand is not live-out from predecessor", &MO0, I);
3442 }
3443 }
3444
3445
3446 if (MInfo.reachable) {
3448 if (!seen.count(Pred)) {
3449 report("Missing PHI operand", &Phi);
3451 << " is a predecessor according to the CFG.\n";
3452 }
3453 }
3454 }
3455 }
3456}
3457
3458static void
3460 std::function<void(const Twine &Message)> FailureCB,
3464
3465 for (const auto &MBB : MF) {
3467 for (const auto &MI : MBB.instrs())
3469 }
3470
3474 }
3475}
3476
3477void MachineVerifier::visitMachineFunctionAfter() {
3478 auto FailureCB = [this](const Twine &Message) {
3479 report(Message.str().c_str(), MF);
3480 };
3482
3483 calcRegsPassed();
3484
3486 checkPHIOps(MBB);
3487
3488
3489 calcRegsRequired();
3490
3491
3492 for (const auto &MBB : *MF) {
3493 BBInfo &MInfo = MBBInfoMap[&MBB];
3494 for (Register VReg : MInfo.vregsRequired)
3495 if (MInfo.regsKilled.count(VReg)) {
3496 report("Virtual register killed in block, but needed live out.", &MBB);
3497 OS << "Virtual register " << printReg(VReg)
3498 << " is used after the block.\n";
3499 }
3500 }
3501
3502 if (!MF->empty()) {
3503 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3504 for (Register VReg : MInfo.vregsRequired) {
3505 report("Virtual register defs don't dominate all uses.", MF);
3506 report_context_vreg(VReg);
3507 }
3508 }
3509
3510 if (LiveVars)
3511 verifyLiveVariables();
3512 if (LiveInts)
3513 verifyLiveIntervals();
3514
3515
3516
3517
3518
3519
3520
3521
3522 if (MRI->tracksLiveness())
3523 for (const auto &MBB : *MF)
3527 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3528 continue;
3530 BBInfo &PInfo = MBBInfoMap[Pred];
3531 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3532 report("Live in register not found to be live out from predecessor.",
3534 OS << TRI->getName(LiveInReg) << " not found to be live out from "
3536 }
3537 }
3538 }
3539
3540 for (auto CSInfo : MF->getCallSitesInfo())
3541 if (!CSInfo.first->isCall())
3542 report("Call site info referencing instruction that is not call", MF);
3543
3544
3545
3546 if (MF->getFunction().getSubprogram()) {
3548 for (const auto &MBB : *MF) {
3549 for (const auto &MI : MBB) {
3550 if (auto Num = MI.peekDebugInstrNum()) {
3551 auto Result = SeenNumbers.insert((unsigned)Num);
3553 report("Instruction has a duplicated value tracking number", &MI);
3554 }
3555 }
3556 }
3557 }
3558}
3559
3560void MachineVerifier::verifyLiveVariables() {
3561 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
3562 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3565 for (const auto &MBB : *MF) {
3566 BBInfo &MInfo = MBBInfoMap[&MBB];
3567
3568
3569 if (MInfo.vregsRequired.count(Reg)) {
3571 report("LiveVariables: Block missing from AliveBlocks", &MBB);
3572 OS << "Virtual register " << printReg(Reg)
3573 << " must be live through the block.\n";
3574 }
3575 } else {
3577 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
3578 OS << "Virtual register " << printReg(Reg)
3579 << " is not needed live through the block.\n";
3580 }
3581 }
3582 }
3583 }
3584}
3585
3586void MachineVerifier::verifyLiveIntervals() {
3587 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
3588 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3590
3591
3592 if (MRI->reg_nodbg_empty(Reg))
3593 continue;
3594
3595 if (!LiveInts->hasInterval(Reg)) {
3596 report("Missing live interval for virtual register", MF);
3597 OS << printReg(Reg, TRI) << " still has defs or uses\n";
3598 continue;
3599 }
3600
3602 assert(Reg == LI.reg() && "Invalid reg to interval mapping");
3603 verifyLiveInterval(LI);
3604 }
3605
3606
3607 for (MCRegUnit Unit : TRI->regunits())
3608 if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
3610}
3611
3612void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
3617 return;
3618
3620
3621 if (!DefVNI) {
3622 report("Value not live at VNInfo def and not marked unused", MF);
3623 report_context(LR, VRegOrUnit, LaneMask);
3624 report_context(*VNI);
3625 return;
3626 }
3627
3628 if (DefVNI != VNI) {
3629 report("Live segment at def has different VNInfo", MF);
3630 report_context(LR, VRegOrUnit, LaneMask);
3631 report_context(*VNI);
3632 return;
3633 }
3634
3636 if () {
3637 report("Invalid VNInfo definition index", MF);
3638 report_context(LR, VRegOrUnit, LaneMask);
3639 report_context(*VNI);
3640 return;
3641 }
3642
3644 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
3645 report("PHIDef VNInfo is not defined at MBB start", MBB);
3646 report_context(LR, VRegOrUnit, LaneMask);
3647 report_context(*VNI);
3648 }
3649 return;
3650 }
3651
3652
3653 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
3654 if () {
3655 report("No instruction at VNInfo def index", MBB);
3656 report_context(LR, VRegOrUnit, LaneMask);
3657 report_context(*VNI);
3658 return;
3659 }
3660
3661 bool hasDef = false;
3662 bool isEarlyClobber = false;
3664 if (!MOI->isReg() || !MOI->isDef())
3665 continue;
3667 if (MOI->getReg() != VRegOrUnit.asVirtualReg())
3668 continue;
3669 } else {
3670 if (!MOI->getReg().isPhysical() ||
3671 ->hasRegUnit(MOI->getReg(), VRegOrUnit.asMCRegUnit()))
3672 continue;
3673 }
3674 if (LaneMask.any() &&
3675 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3676 continue;
3677 hasDef = true;
3678 if (MOI->isEarlyClobber())
3679 isEarlyClobber = true;
3680 }
3681
3682 if (!hasDef) {
3683 report("Defining instruction does not modify register", MI);
3684 report_context(LR, VRegOrUnit, LaneMask);
3685 report_context(*VNI);
3686 }
3687
3688
3689
3690 if (isEarlyClobber) {
3692 report("Early clobber def must be at an early-clobber slot", MBB);
3693 report_context(LR, VRegOrUnit, LaneMask);
3694 report_context(*VNI);
3695 }
3697 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3698 report_context(LR, VRegOrUnit, LaneMask);
3699 report_context(*VNI);
3700 }
3701}
3702
3703void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
3709 assert(VNI && "Live segment has no valno");
3710
3712 report("Foreign valno in live segment", MF);
3713 report_context(LR, VRegOrUnit, LaneMask);
3714 report_context(S);
3715 report_context(*VNI);
3716 }
3717
3719 report("Live segment valno is marked unused", MF);
3720 report_context(LR, VRegOrUnit, LaneMask);
3721 report_context(S);
3722 }
3723
3725 if () {
3726 report("Bad start of live segment, no basic block", MF);
3727 report_context(LR, VRegOrUnit, LaneMask);
3728 report_context(S);
3729 return;
3730 }
3731 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3732 if (S.start != MBBStartIdx && S.start != VNI->def) {
3733 report("Live segment must begin at MBB entry or valno def", MBB);
3734 report_context(LR, VRegOrUnit, LaneMask);
3735 report_context(S);
3736 }
3737
3740 if (!EndMBB) {
3741 report("Bad end of live segment, no basic block", MF);
3742 report_context(LR, VRegOrUnit, LaneMask);
3743 report_context(S);
3744 return;
3745 }
3746
3747
3748 if (S.end != LiveInts->getMBBEndIdx(EndMBB)) {
3749
3752 return;
3753
3754
3756 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
3757 if () {
3758 report("Live segment doesn't end at a valid instruction", EndMBB);
3759 report_context(LR, VRegOrUnit, LaneMask);
3760 report_context(S);
3761 return;
3762 }
3763
3764
3766 report("Live segment ends at B slot of an instruction", EndMBB);
3767 report_context(LR, VRegOrUnit, LaneMask);
3768 report_context(S);
3769 }
3770
3772
3773
3775 report("Live segment ending at dead slot spans instructions", EndMBB);
3776 report_context(LR, VRegOrUnit, LaneMask);
3777 report_context(S);
3778 }
3779 }
3780
3781
3782
3783
3784
3785 if (MF->getProperties().hasTiedOpsRewritten() && S.end.isEarlyClobber()) {
3786 if (I + 1 == LR.end() || (I + 1)->start != S.end) {
3787 report("Live segment ending at early clobber slot must be "
3788 "redefined by an EC def in the same instruction",
3789 EndMBB);
3790 report_context(LR, VRegOrUnit, LaneMask);
3791 report_context(S);
3792 }
3793 }
3794
3795
3796
3798
3799
3800 bool hasRead = false;
3801 bool hasSubRegDef = false;
3802 bool hasDeadDef = false;
3804 if (!MOI->isReg() || MOI->getReg() != VRegOrUnit.asVirtualReg())
3805 continue;
3806 unsigned Sub = MOI->getSubReg();
3809 if (MOI->isDef()) {
3810 if (Sub != 0) {
3811 hasSubRegDef = true;
3812
3813
3814
3815 SLM = ~SLM;
3816 }
3817 if (MOI->isDead())
3818 hasDeadDef = true;
3819 }
3820 if (LaneMask.any() && (LaneMask & SLM).none())
3821 continue;
3822 if (MOI->readsReg())
3823 hasRead = true;
3824 }
3826
3827
3828
3829 if (LaneMask.none() && !hasDeadDef) {
3830 report(
3831 "Instruction ending live segment on dead slot has no dead flag",
3832 MI);
3833 report_context(LR, VRegOrUnit, LaneMask);
3834 report_context(S);
3835 }
3836 } else {
3837 if (!hasRead) {
3838
3839
3840 if (->shouldTrackSubRegLiveness(VRegOrUnit.asVirtualReg()) ||
3841 LaneMask.any() || !hasSubRegDef) {
3842 report("Instruction ending live segment doesn't read the register",
3843 MI);
3844 report_context(LR, VRegOrUnit, LaneMask);
3845 report_context(S);
3846 }
3847 }
3848 }
3849 }
3850 }
3851
3852
3854
3856
3857 if (MBB == EndMBB)
3858 return;
3859
3860 ++MFI;
3861 }
3862
3864 if (LaneMask.any()) {
3867 }
3868
3869 while (true) {
3870 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3871
3872 if (!VRegOrUnit.isVirtualReg() && MFI->isEHPad()) {
3873 if (&*MFI == EndMBB)
3874 break;
3875 ++MFI;
3876 continue;
3877 }
3878
3879
3880 bool IsPHI = VNI->isPHIDef() &&
3881 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3882
3883
3885 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3886
3887 if (MFI->isEHPad()) {
3889 if (MI.isCall()) {
3890 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3891 break;
3892 }
3893 }
3894 }
3896
3897
3898
3899
3900
3901 if (!PVNI && (LaneMask.none() || !IsPHI)) {
3903 continue;
3904 report("Register not marked live out of predecessor", Pred);
3905 report_context(LR, VRegOrUnit, LaneMask);
3906 report_context(*VNI);
3908 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before " << PEnd
3909 << '\n';
3910 continue;
3911 }
3912
3913
3914 if (!IsPHI && PVNI != VNI) {
3915 report("Different value live out of predecessor", Pred);
3916 report_context(LR, VRegOrUnit, LaneMask);
3917 OS << "Valno #" << PVNI->id << " live out of "
3920 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3921 }
3922 }
3923 if (&*MFI == EndMBB)
3924 break;
3925 ++MFI;
3926 }
3927}
3928
3929void MachineVerifier::verifyLiveRange(const LiveRange &LR,
3933 verifyLiveRangeValue(LR, VNI, VRegOrUnit, LaneMask);
3934
3936 verifyLiveRangeSegment(LR, I, VRegOrUnit, LaneMask);
3937}
3938
3939void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3943
3948 if ((Mask & SR.LaneMask).any()) {
3949 report("Lane masks of sub ranges overlap in live interval", MF);
3950 report_context(LI);
3951 }
3952 if ((SR.LaneMask & ~MaxMask).any()) {
3953 report("Subrange lanemask is invalid", MF);
3954 report_context(LI);
3955 }
3956 if (SR.empty()) {
3957 report("Subrange must not be empty", MF);
3959 }
3960 Mask |= SR.LaneMask;
3962 if (!LI.covers(SR)) {
3963 report("A Subrange is not covered by the main range", MF);
3964 report_context(LI);
3965 }
3966 }
3967 }
3968
3969
3971 unsigned NumComp = ConEQ.Classify(LI);
3972 if (NumComp > 1) {
3973 report("Multiple connected components in live interval", MF);
3974 report_context(LI);
3975 for (unsigned comp = 0; comp != NumComp; ++comp) {
3976 OS << comp << ": valnos";
3978 if (comp == ConEQ.getEqClass(I))
3979 OS << ' ' << I->id;
3980 OS << '\n';
3981 }
3982 }
3983}
3984
3985namespace {
3986
3987
3988
3989
3990
3991struct StackStateOfBB {
3992 StackStateOfBB() = default;
3993 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup)
3994 : EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3995 ExitIsSetup(ExitSetup) {}
3996
3997
3998 int EntryValue = 0;
3999 int ExitValue = 0;
4000 bool EntryIsSetup = false;
4001 bool ExitIsSetup = false;
4002};
4003
4004}
4005
4006
4007
4008
4009void MachineVerifier::verifyStackFrame() {
4012 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
4013 return;
4014
4016 SPState.resize(MF->getNumBlockIDs());
4018
4019
4023 DFI != DFE; ++DFI) {
4025
4026 StackStateOfBB BBState;
4027
4028 if (DFI.getPathLength() >= 2) {
4029 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
4031 "DFS stack predecessor is already visited.\n");
4032 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
4033 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
4034 BBState.ExitValue = BBState.EntryValue;
4035 BBState.ExitIsSetup = BBState.EntryIsSetup;
4036 }
4037
4039 report("Call frame size on entry does not match value computed from "
4040 "predecessor",
4043 << " does not match value computed from predecessor "
4044 << -BBState.EntryValue << '\n';
4045 }
4046
4047
4048 for (const auto &I : *MBB) {
4049 if (I.getOpcode() == FrameSetupOpcode) {
4050 if (BBState.ExitIsSetup)
4051 report("FrameSetup is after another FrameSetup", &I);
4052 if (->isSSA() && !MF->getFrameInfo().adjustsStack())
4053 report("AdjustsStack not set in presence of a frame pseudo "
4054 "instruction.", &I);
4056 BBState.ExitIsSetup = true;
4057 }
4058
4059 if (I.getOpcode() == FrameDestroyOpcode) {
4061 if (!BBState.ExitIsSetup)
4062 report("FrameDestroy is not after a FrameSetup", &I);
4063 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
4064 BBState.ExitValue;
4065 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
4066 report("FrameDestroy is after FrameSetup ", &I);
4067 OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
4068 << AbsSPAdj << ">.\n";
4069 }
4070 if (->isSSA() && !MF->getFrameInfo().adjustsStack())
4071 report("AdjustsStack not set in presence of a frame pseudo "
4072 "instruction.", &I);
4073 BBState.ExitValue += Size;
4074 BBState.ExitIsSetup = false;
4075 }
4076 }
4078
4079
4080
4082 if (Reachable.count(Pred) &&
4083 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
4084 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
4085 report("The exit stack state of a predecessor is inconsistent.", MBB);
4086 OS << "Predecessor " << printMBBReference(*Pred) << " has exit state ("
4087 << SPState[Pred->getNumber()].ExitValue << ", "
4088 << SPState[Pred->getNumber()].ExitIsSetup << "), while "
4090 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
4091 }
4092 }
4093
4094
4095
4097 if (Reachable.count(Succ) &&
4098 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
4099 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
4100 report("The entry stack state of a successor is inconsistent.", MBB);
4101 OS << "Successor " << printMBBReference(*Succ) << " has entry state ("
4102 << SPState[Succ->getNumber()].EntryValue << ", "
4103 << SPState[Succ->getNumber()].EntryIsSetup << "), while "
4105 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
4106 }
4107 }
4108
4109
4111 if (BBState.ExitIsSetup)
4112 report("A return block ends with a FrameSetup.", MBB);
4113 if (BBState.ExitValue)
4114 report("A return block ends with a nonzero stack adjustment.", MBB);
4115 }
4116 }
4117}
4118
4119void MachineVerifier::verifyStackProtector() {
4122 return;
4123
4124
4126 return;
4127 const TargetFrameLowering &TFI = *MF->getSubtarget().getFrameLowering();
4128 bool StackGrowsDown =
4132 int64_t SPEnd = SPStart + MFI.getObjectSize(FI);
4134 if (I == FI)
4135 continue;
4137 continue;
4138
4139
4140
4141
4143 continue;
4144
4146 continue;
4147
4148
4149
4150
4152 continue;
4155 if (SPStart < ObjEnd && ObjStart < SPEnd) {
4156 report("Stack protector overlaps with another stack object", MF);
4157 break;
4158 }
4159 if ((StackGrowsDown && SPStart <= ObjStart) ||
4160 (!StackGrowsDown && SPStart >= ObjStart)) {
4161 report("Stack protector is not the top-most object on the stack", MF);
4162 break;
4163 }
4164 }
4165}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
hexagon widen Hexagon Store false hexagon widen loads
std::pair< Instruction::BinaryOps, Value * > OffsetOp
Find all possible pairs (BinOp, RHS) that BinOp V, RHS can be simplified.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
print mir2vec MIR2Vec Vocabulary Printer Pass
This file declares the MIR specialization of the GenericConvergenceVerifier template.
Register const TargetRegisterInfo * TRI
static void verifyConvergenceControl(const MachineFunction &MF, MachineDominatorTree &DT, std::function< void(const Twine &Message)> FailureCB, raw_ostream &OS)
Definition MachineVerifier.cpp:3459
Promote Memory to Register
modulo schedule Modulo Schedule test pass
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
SI Optimize VGPR LiveRange
std::unordered_set< BasicBlock * > BlockSet
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static unsigned getSize(unsigned Kind)
static LLVM_ABI unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
const fltSemantics & getSemantics() const
PassT::Result * getCachedResult(IRUnitT &IR) const
Get the cached result of an analysis pass for a given IR unit.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
This class holds the attributes for a particular argument, parameter, function, or return value.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
IntegerType * getIntegerType() const
Variant of the getType() method to always return an IntegerType, which reduces the amount of casting ...
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
A parsed version of the target data layout string in and methods for querying it.
Implements a dense probed hash-table based set.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
const Function & getFunction() const
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
void verify(const DominatorTreeT &DT)
void visit(const BlockT &BB)
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isPointerVector() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr bool isScalable() const
Returns true if the LLT is a scalable vector.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr bool isPointerOrPointerVector() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
LLVM_ABI void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ABI bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Segments::const_iterator const_iterator
bool liveAt(SlotIndex index) const
LLVM_ABI bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...
bool verify() const
Walk the range and assert if any invariants fail to hold.
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LLVM_ABI VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TypeSize getValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
This holds information about one operand of a machine instruction, indicating the register class for ...
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
const MDOperand & getOperand(unsigned I) const
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
LLVM_ABI bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int getStackProtectorIndex() const
Return the index for the stack protector object.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
LLVM_ABI BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
bool isVariableSizedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a variable sized object.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasStackProtectorIndex() const
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Properties which a MachineFunction may have at a given point in time.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, raw_ostream *OS=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition MachineVerifier.cpp:427
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
LLT getMemoryType() const
Return the memory type of the memory reference.
const MDNode * getRanges() const
Return the range tag for the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
LLVM_ABI void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr) const
Print the MachineOperand to os.
LaneBitmask getLaneMask() const
unsigned getCFIIndex() const
LLVM_ABI bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Definition MachineVerifier.cpp:397
ManagedStatic - This transparently changes the behavior of global statics to be lazily constructed on...
static LLVM_ABI PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable() - Subclasses use this function to get analysis information tha...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
unsigned virtRegIndex() const
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
bool erase(PtrType Ptr)
Remove pointer from the set.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
unsigned getCallFrameDestroyOpcode() const
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
static constexpr TypeSize getZero()
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
Wrapper class representing a virtual register or register unit.
constexpr bool isVirtualReg() const
constexpr MCRegUnit asMCRegUnit() const
constexpr Register asVirtualReg() const
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
This class implements an extremely fast bulk output stream that can only output to a stream.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LLVM_ABI AttributeSet getFnAttributes(LLVMContext &C, ID id)
Return the function attributes for an intrinsic.
std::enable_if_t< detail::IsValidPointer< X, Y >::value, X * > extract(Y &&MD)
Extract a Value from Metadata.
NodeAddr< DefNode * > Def
NodeAddr< PhiNode * > Phi
NodeAddr< FuncNode * > Func
LLVM_ABI iterator begin() const
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
LLVM_ABI FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
LLVM_ABI void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
Definition MachineVerifier.cpp:417
auto reverse(ContainerTy &&C)
LLVM_ABI void initializeMachineVerifierLegacyPassPass(PassRegistry &)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
GenericConvergenceVerifier< MachineSSAContext > MachineConvergenceVerifier
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
LLVM_ABI raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
LLVM_ABI EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
bool isa(const From &Val)
isa - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Sub
Subtraction of integers.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Implement std::hash so that hash_code can be used in STL containers.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.