LLVM: lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Source File (original) (raw)
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30
31using namespace llvm;
32
34
35
36
37
38static int64_t
40 switch (E->getKind()) {
43 return Res < 0 ? -1 : Res;
44 }
45
49
50 if (Name == "lt") return 0;
51 if (Name == "gt") return 1;
52 if (Name == "eq") return 2;
53 if (Name == "so") return 3;
54 if (Name == "un") return 3;
55
56 if (Name == "cr0") return 0;
57 if (Name == "cr1") return 1;
58 if (Name == "cr2") return 2;
59 if (Name == "cr3") return 3;
60 if (Name == "cr4") return 4;
61 if (Name == "cr5") return 5;
62 if (Name == "cr6") return 6;
63 if (Name == "cr7") return 7;
64
65 return -1;
66 }
67
69 return -1;
70
75 int64_t Res;
76
77 if (LHSVal < 0 || RHSVal < 0)
78 return -1;
79
81 default: return -1;
84 }
85
86 return Res < 0 ? -1 : Res;
87 }
89 return -1;
92 }
93
95}
96
97namespace {
98
99struct PPCOperand;
100
102 const bool IsPPC64;
103
104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
105
106 bool isPPC64() const { return IsPPC64; }
107
108 MCRegister matchRegisterName(int64_t &IntVal);
109
110 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
111 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
112 SMLoc &EndLoc) override;
113
114 const MCExpr *extractSpecifier(const MCExpr *E,
116 bool parseExpression(const MCExpr *&EVal);
117
119
120 bool parseDirectiveWord(unsigned Size, AsmToken ID);
121 bool parseDirectiveTC(unsigned Size, AsmToken ID);
122 bool parseDirectiveMachine(SMLoc L);
123 bool parseDirectiveAbiVersion(SMLoc L);
124 bool parseDirectiveLocalEntry(SMLoc L);
125 bool parseGNUAttribute(SMLoc L);
126
127 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
129 uint64_t &ErrorInfo,
130 bool MatchingInlineAsm) override;
131
132 void processInstruction(MCInst &Inst, const OperandVector &Ops);
133
134
135
136
137#define GET_ASSEMBLER_HEADER
138#include "PPCGenAsmMatcher.inc"
139
140
141
142
143public:
147 IsPPC64(STI.getTargetTriple().isPPC64()) {
148
149 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
150 }
151
152 bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
153 SMLoc NameLoc, OperandVector &Operands) override;
154
155 bool ParseDirective(AsmToken DirectiveID) override;
156
157 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
158 unsigned Kind) override;
159
160 const MCExpr *applySpecifier(const MCExpr *E, uint32_t,
161 MCContext &Ctx) override;
162};
163
164
165
167 enum KindTy {
168 Token,
169 Immediate,
170 ContextImmediate,
171 Expression,
172 TLSRegister
173 } Kind;
174
175 SMLoc StartLoc, EndLoc;
176 bool IsPPC64;
177
178 struct TokOp {
179 const char *Data;
180 unsigned Length;
181 };
182
183 struct ImmOp {
184 int64_t Val;
185 bool IsMemOpBase;
186 };
187
188 struct ExprOp {
189 const MCExpr *Val;
190 int64_t CRVal;
191 };
192
193 struct TLSRegOp {
194 const MCSymbolRefExpr *Sym;
195 };
196
197 union {
198 struct TokOp Tok;
199 struct ImmOp Imm;
200 struct ExprOp Expr;
201 struct TLSRegOp TLSReg;
202 };
203
204 PPCOperand(KindTy K) : Kind(K) {}
205
206public:
207 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
208 Kind = o.Kind;
209 StartLoc = o.StartLoc;
210 EndLoc = o.EndLoc;
211 IsPPC64 = o.IsPPC64;
212 switch (Kind) {
213 case Token:
214 Tok = o.Tok;
215 break;
216 case Immediate:
217 case ContextImmediate:
219 break;
220 case Expression:
221 Expr = o.Expr;
222 break;
223 case TLSRegister:
224 TLSReg = o.TLSReg;
225 break;
226 }
227 }
228
229
230
231 void operator delete(void *p) { ::operator delete(p); }
232
233
234 SMLoc getStartLoc() const override { return StartLoc; }
235
236
237 SMLoc getEndLoc() const override { return EndLoc; }
238
239
240
241 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
242
243
244 bool isPPC64() const { return IsPPC64; }
245
246
247 bool isMemOpBase() const { return Kind == Immediate && Imm.IsMemOpBase; }
248
249 int64_t getImm() const {
250 assert(Kind == Immediate && "Invalid access!");
251 return Imm.Val;
252 }
253 int64_t getImmS16Context() const {
254 assert((Kind == Immediate || Kind == ContextImmediate) &&
255 "Invalid access!");
256 if (Kind == Immediate)
257 return Imm.Val;
258 return static_cast<int16_t>(Imm.Val);
259 }
260 int64_t getImmU16Context() const {
261 assert((Kind == Immediate || Kind == ContextImmediate) &&
262 "Invalid access!");
263 return Imm.Val;
264 }
265
266 const MCExpr *getExpr() const {
267 assert(Kind == Expression && "Invalid access!");
268 return Expr.Val;
269 }
270
271 int64_t getExprCRVal() const {
272 assert(Kind == Expression && "Invalid access!");
273 return Expr.CRVal;
274 }
275
276 const MCExpr *getTLSReg() const {
277 assert(Kind == TLSRegister && "Invalid access!");
278 return TLSReg.Sym;
279 }
280
282
284 assert(isRegNumber() && "Invalid access!");
285 return (unsigned)Imm.Val;
286 }
287
288 unsigned getFpReg() const {
289 assert(isEvenRegNumber() && "Invalid access!");
290 return (unsigned)(Imm.Val >> 1);
291 }
292
293 unsigned getVSReg() const {
294 assert(isVSRegNumber() && "Invalid access!");
295 return (unsigned) Imm.Val;
296 }
297
298 unsigned getACCReg() const {
299 assert(isACCRegNumber() && "Invalid access!");
300 return (unsigned) Imm.Val;
301 }
302
303 unsigned getDMRROWReg() const {
304 assert(isDMRROWRegNumber() && "Invalid access!");
305 return (unsigned)Imm.Val;
306 }
307
308 unsigned getDMRROWpReg() const {
309 assert(isDMRROWpRegNumber() && "Invalid access!");
310 return (unsigned)Imm.Val;
311 }
312
313 unsigned getDMRReg() const {
314 assert(isDMRRegNumber() && "Invalid access!");
315 return (unsigned)Imm.Val;
316 }
317
318 unsigned getDMRpReg() const {
319 assert(isDMRpRegNumber() && "Invalid access!");
320 return (unsigned)Imm.Val;
321 }
322
323 unsigned getVSRpEvenReg() const {
324 assert(isVSRpEvenRegNumber() && "Invalid access!");
325 return (unsigned) Imm.Val >> 1;
326 }
327
328 unsigned getG8pReg() const {
329 assert(isEvenRegNumber() && "Invalid access!");
330 return (unsigned)Imm.Val;
331 }
332
333 unsigned getCCReg() const {
334 assert(isCCRegNumber() && "Invalid access!");
335 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
336 }
337
338 unsigned getCRBit() const {
339 assert(isCRBitNumber() && "Invalid access!");
340 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
341 }
342
343 unsigned getCRBitMask() const {
344 assert(isCRBitMask() && "Invalid access!");
346 }
347
348 bool isToken() const override { return Kind == Token; }
349 bool isImm() const override {
350 return Kind == Immediate || Kind == Expression;
351 }
352
353 template <uint64_t N> bool isUImm() const {
355 }
356 template <uint64_t N> bool isSImm() const {
358 }
359 bool isU6ImmX2() const { return isUImm<6>() && (getImm() & 1) == 0; }
360 bool isU7ImmX4() const { return isUImm<7>() && (getImm() & 3) == 0; }
361 bool isU8ImmX8() const { return isUImm<8>() && (getImm() & 7) == 0; }
362
363 bool isU16Imm() const { return isExtImm<16>( false, 1); }
364 bool isS16Imm() const { return isExtImm<16>( true, 1); }
365 bool isS16ImmX4() const { return isExtImm<16>( true, 4); }
366 bool isS16ImmX16() const { return isExtImm<16>( true, 16); }
367 bool isS17Imm() const { return isExtImm<17>( true, 1); }
368 bool isS32Imm() const {
369
370 return Kind == Expression || isSImm<32>();
371 }
372 bool isS34Imm() const {
373
374
375 return Kind == Expression || isSImm<34>();
376 }
377 bool isS34ImmX16() const {
378 return Kind == Expression || (isSImm<34>() && (getImm() & 15) == 0);
379 }
380
381 bool isHashImmX8() const {
382
383
384
385 return (Kind == Immediate && getImm() <= -8 && getImm() >= -512 &&
386 (getImm() & 7) == 0);
387 }
388
389 bool isTLSReg() const { return Kind == TLSRegister; }
390 bool isDirectBr() const {
391 if (Kind == Expression)
392 return true;
393 if (Kind != Immediate)
394 return false;
395
396 if ((getImm() & 3) != 0)
397 return false;
399 return true;
400 if (!IsPPC64) {
401
403 return true;
404 }
405 return false;
406 }
407 bool isCondBr() const { return Kind == Expression ||
409 (getImm() & 3) == 0); }
410 bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
411 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
412 bool isACCRegNumber() const {
414 }
415 bool isDMRROWRegNumber() const {
417 }
418 bool isDMRROWpRegNumber() const {
420 }
421 bool isDMRRegNumber() const {
423 }
424 bool isDMRpRegNumber() const {
426 }
427 bool isVSRpEvenRegNumber() const {
429 }
430 bool isVSRegNumber() const {
432 }
433 bool isCCRegNumber() const { return (Kind == Expression
435 (Kind == Immediate
437 bool isCRBitNumber() const { return (Kind == Expression
439 (Kind == Immediate
441
442 bool isEvenRegNumber() const { return isRegNumber() && (getImm() & 1) == 0; }
443
444 bool isCRBitMask() const {
447 }
448 bool isATBitsAsHint() const { return false; }
449 bool isMem() const override { return false; }
450 bool isReg() const override { return false; }
451
452 void addRegOperands(MCInst &Inst, unsigned N) const {
454 }
455
456 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
457 assert(N == 1 && "Invalid number of operands!");
459 }
460
461 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
462 assert(N == 1 && "Invalid number of operands!");
464 }
465
466 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
467 assert(N == 1 && "Invalid number of operands!");
469 }
470
471 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
472 assert(N == 1 && "Invalid number of operands!");
474 }
475
476 void addRegG8pRCOperands(MCInst &Inst, unsigned N) const {
477 assert(N == 1 && "Invalid number of operands!");
479 }
480
481 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
482 if (isPPC64())
483 addRegG8RCOperands(Inst, N);
484 else
485 addRegGPRCOperands(Inst, N);
486 }
487
488 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
489 if (isPPC64())
490 addRegG8RCNoX0Operands(Inst, N);
491 else
492 addRegGPRCNoR0Operands(Inst, N);
493 }
494
495 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
496 assert(N == 1 && "Invalid number of operands!");
498 }
499
500 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
501 assert(N == 1 && "Invalid number of operands!");
503 }
504
505 void addRegFpRCOperands(MCInst &Inst, unsigned N) const {
506 assert(N == 1 && "Invalid number of operands!");
508 }
509
510 void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
511 assert(N == 1 && "Invalid number of operands!");
513 }
514
515 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
516 assert(N == 1 && "Invalid number of operands!");
518 }
519
520 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
521 assert(N == 1 && "Invalid number of operands!");
523 }
524
525 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
526 assert(N == 1 && "Invalid number of operands!");
528 }
529
530 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 1 && "Invalid number of operands!");
533 }
534
535 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
536 assert(N == 1 && "Invalid number of operands!");
538 }
539
540 void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
541 assert(N == 1 && "Invalid number of operands!");
543 }
544
545 void addRegACCRCOperands(MCInst &Inst, unsigned N) const {
546 assert(N == 1 && "Invalid number of operands!");
548 }
549
550 void addRegDMRROWRCOperands(MCInst &Inst, unsigned N) const {
551 assert(N == 1 && "Invalid number of operands!");
553 }
554
555 void addRegDMRROWpRCOperands(MCInst &Inst, unsigned N) const {
556 assert(N == 1 && "Invalid number of operands!");
558 }
559
560 void addRegDMRRCOperands(MCInst &Inst, unsigned N) const {
561 assert(N == 1 && "Invalid number of operands!");
563 }
564
565 void addRegDMRpRCOperands(MCInst &Inst, unsigned N) const {
566 assert(N == 1 && "Invalid number of operands!");
568 }
569
570 void addRegWACCRCOperands(MCInst &Inst, unsigned N) const {
571 assert(N == 1 && "Invalid number of operands!");
573 }
574
575 void addRegWACC_HIRCOperands(MCInst &Inst, unsigned N) const {
576 assert(N == 1 && "Invalid number of operands!");
578 }
579
580 void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
581 assert(N == 1 && "Invalid number of operands!");
583 }
584
585 void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
586 assert(N == 1 && "Invalid number of operands!");
588 }
589
590 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
591 assert(N == 1 && "Invalid number of operands!");
593 }
594
595 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
596 assert(N == 1 && "Invalid number of operands!");
598 }
599
600 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
601 assert(N == 1 && "Invalid number of operands!");
603 }
604
605 void addImmOperands(MCInst &Inst, unsigned N) const {
606 assert(N == 1 && "Invalid number of operands!");
607 if (Kind == Immediate)
609 else
611 }
612
613 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
614 assert(N == 1 && "Invalid number of operands!");
615 switch (Kind) {
616 case Immediate:
618 break;
619 case ContextImmediate:
621 break;
622 default:
624 break;
625 }
626 }
627
628 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
629 assert(N == 1 && "Invalid number of operands!");
630 switch (Kind) {
631 case Immediate:
633 break;
634 case ContextImmediate:
636 break;
637 default:
639 break;
640 }
641 }
642
643 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
644 assert(N == 1 && "Invalid number of operands!");
645 if (Kind == Immediate)
647 else
649 }
650
651 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
652 assert(N == 1 && "Invalid number of operands!");
654 }
655
657 assert(Kind == Token && "Invalid access!");
658 return StringRef(Tok.Data, Tok.Length);
659 }
660
661 void print(raw_ostream &OS, const MCAsmInfo &MAI) const override;
662
663 static std::unique_ptr CreateToken(StringRef Str, SMLoc S,
664 bool IsPPC64) {
665 auto Op = std::make_unique(Token);
666 Op->Tok.Data = Str.data();
667 Op->Tok.Length = Str.size();
668 Op->StartLoc = S;
669 Op->EndLoc = S;
670 Op->IsPPC64 = IsPPC64;
671 return Op;
672 }
673
674 static std::unique_ptr
675 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
676
677
678
679
680
681 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
682 std::unique_ptr Op(new (Mem) PPCOperand(Token));
683 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
684 Op->Tok.Length = Str.size();
685 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
686 Op->StartLoc = S;
687 Op->EndLoc = S;
688 Op->IsPPC64 = IsPPC64;
689 return Op;
690 }
691
692 static std::unique_ptr CreateImm(int64_t Val, SMLoc S, SMLoc E,
693 bool IsPPC64,
694 bool IsMemOpBase = false) {
695 auto Op = std::make_unique(Immediate);
696 Op->Imm.Val = Val;
697 Op->Imm.IsMemOpBase = IsMemOpBase;
698 Op->StartLoc = S;
700 Op->IsPPC64 = IsPPC64;
701 return Op;
702 }
703
704 static std::unique_ptr CreateExpr(const MCExpr *Val, SMLoc S,
705 SMLoc E, bool IsPPC64) {
706 auto Op = std::make_unique(Expression);
707 Op->Expr.Val = Val;
709 Op->StartLoc = S;
711 Op->IsPPC64 = IsPPC64;
712 return Op;
713 }
714
715 static std::unique_ptr
716 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
717 auto Op = std::make_unique(TLSRegister);
718 Op->TLSReg.Sym = Sym;
719 Op->StartLoc = S;
721 Op->IsPPC64 = IsPPC64;
722 return Op;
723 }
724
725 static std::unique_ptr
726 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
727 auto Op = std::make_unique(ContextImmediate);
728 Op->Imm.Val = Val;
729 Op->StartLoc = S;
731 Op->IsPPC64 = IsPPC64;
732 return Op;
733 }
734
735 static std::unique_ptr
736 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
738 return CreateImm(CE->getValue(), S, E, IsPPC64);
739
743 return CreateTLSReg(SRE, S, E, IsPPC64);
744
746 int64_t Res;
748 return CreateContextImm(Res, S, E, IsPPC64);
749 }
750
751 return CreateExpr(Val, S, E, IsPPC64);
752 }
753
754private:
755 template
756 bool isExtImm(bool Signed, unsigned Multiple) const {
757 switch (Kind) {
758 default:
759 return false;
760 case Expression:
761 return true;
762 case Immediate:
763 case ContextImmediate:
766 (getImmS16Context() & (Multiple - 1)) == 0;
767 else
769 (getImmU16Context() & (Multiple - 1)) == 0;
770 }
771 }
772};
773
774}
775
777 switch (Kind) {
778 case Token:
779 OS << "'" << getToken() << "'";
780 break;
781 case Immediate:
782 case ContextImmediate:
784 break;
785 case Expression:
787 break;
788 case TLSRegister:
790 break;
791 }
792}
793
794static void
796 if (Op.isImm()) {
798 return;
799 }
800 const MCExpr *Expr = Op.getExpr();
804 return;
805 }
809 BinExpr->getLHS(), Ctx);
811 return;
812 }
813 }
815}
816
817void PPCAsmParser::processInstruction(MCInst &Inst,
820 switch (Opcode) {
821 case PPC::DCBTx:
822 case PPC::DCBTT:
823 case PPC::DCBTSTx:
824 case PPC::DCBTSTT: {
825 MCInst TmpInst;
826 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
827 PPC::DCBT : PPC::DCBTST);
829 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
832 Inst = TmpInst;
833 break;
834 }
835 case PPC::DCBTCT:
836 case PPC::DCBTDS: {
837 MCInst TmpInst;
842 Inst = TmpInst;
843 break;
844 }
845 case PPC::DCBTSTCT:
846 case PPC::DCBTSTDS: {
847 MCInst TmpInst;
852 Inst = TmpInst;
853 break;
854 }
855 case PPC::DCBFx:
856 case PPC::DCBFL:
857 case PPC::DCBFLP:
858 case PPC::DCBFPS:
859 case PPC::DCBSTPS: {
860 int L = 0;
861 if (Opcode == PPC::DCBFL)
862 L = 1;
863 else if (Opcode == PPC::DCBFLP)
864 L = 3;
865 else if (Opcode == PPC::DCBFPS)
866 L = 4;
867 else if (Opcode == PPC::DCBSTPS)
868 L = 6;
869
870 MCInst TmpInst;
875 Inst = TmpInst;
876 break;
877 }
878 case PPC::LAx: {
879 MCInst TmpInst;
884 Inst = TmpInst;
885 break;
886 }
887 case PPC::PLA8:
888 case PPC::PLA: {
889 MCInst TmpInst;
890 TmpInst.setOpcode(Opcode == PPC::PLA ? PPC::PADDI : PPC::PADDI8);
894 Inst = TmpInst;
895 break;
896 }
897 case PPC::PLA8pc:
898 case PPC::PLApc: {
899 MCInst TmpInst;
900 TmpInst.setOpcode(Opcode == PPC::PLApc ? PPC::PADDIpc : PPC::PADDI8pc);
904 Inst = TmpInst;
905 break;
906 }
907 case PPC::SUBI: {
908 MCInst TmpInst;
913 Inst = TmpInst;
914 break;
915 }
916 case PPC::PSUBI: {
917 MCInst TmpInst;
922 Inst = TmpInst;
923 break;
924 }
925 case PPC::SUBIS: {
926 MCInst TmpInst;
931 Inst = TmpInst;
932 break;
933 }
934 case PPC::SUBIC: {
935 MCInst TmpInst;
940 Inst = TmpInst;
941 break;
942 }
943 case PPC::SUBIC_rec: {
944 MCInst TmpInst;
945 TmpInst.setOpcode(PPC::ADDIC_rec);
949 Inst = TmpInst;
950 break;
951 }
952 case PPC::EXTLWI:
953 case PPC::EXTLWI_rec: {
954 MCInst TmpInst;
957 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
963 Inst = TmpInst;
964 break;
965 }
966 case PPC::EXTRWI:
967 case PPC::EXTRWI_rec: {
968 MCInst TmpInst;
971 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
977 Inst = TmpInst;
978 break;
979 }
980 case PPC::INSLWI:
981 case PPC::INSLWI_rec: {
982 MCInst TmpInst;
985 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
992 Inst = TmpInst;
993 break;
994 }
995 case PPC::INSRWI:
996 case PPC::INSRWI_rec: {
997 MCInst TmpInst;
1000 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
1007 Inst = TmpInst;
1008 break;
1009 }
1010 case PPC::ROTRWI:
1011 case PPC::ROTRWI_rec: {
1012 MCInst TmpInst;
1014 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1020 Inst = TmpInst;
1021 break;
1022 }
1023 case PPC::SLWI:
1024 case PPC::SLWI_rec: {
1025 MCInst TmpInst;
1027 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1033 Inst = TmpInst;
1034 break;
1035 }
1036 case PPC::SRWI:
1037 case PPC::SRWI_rec: {
1038 MCInst TmpInst;
1040 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1046 Inst = TmpInst;
1047 break;
1048 }
1049 case PPC::CLRRWI:
1050 case PPC::CLRRWI_rec: {
1051 MCInst TmpInst;
1053 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1059 Inst = TmpInst;
1060 break;
1061 }
1062 case PPC::CLRLSLWI:
1063 case PPC::CLRLSLWI_rec: {
1064 MCInst TmpInst;
1067 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1073 Inst = TmpInst;
1074 break;
1075 }
1076 case PPC::EXTLDI:
1077 case PPC::EXTLDI_rec: {
1078 MCInst TmpInst;
1081 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1086 Inst = TmpInst;
1087 break;
1088 }
1089 case PPC::EXTRDI:
1090 case PPC::EXTRDI_rec: {
1091 MCInst TmpInst;
1094 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1099 Inst = TmpInst;
1100 break;
1101 }
1102 case PPC::INSRDI:
1103 case PPC::INSRDI_rec: {
1104 MCInst TmpInst;
1107 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
1113 Inst = TmpInst;
1114 break;
1115 }
1116 case PPC::ROTRDI:
1117 case PPC::ROTRDI_rec: {
1118 MCInst TmpInst;
1120 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1125 Inst = TmpInst;
1126 break;
1127 }
1128 case PPC::SLDI:
1129 case PPC::SLDI_rec: {
1130 MCInst TmpInst;
1132 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1137 Inst = TmpInst;
1138 break;
1139 }
1140 case PPC::SUBPCIS: {
1141 MCInst TmpInst;
1143 TmpInst.setOpcode(PPC::ADDPCIS);
1146 Inst = TmpInst;
1147 break;
1148 }
1149 case PPC::SRDI:
1150 case PPC::SRDI_rec: {
1151 MCInst TmpInst;
1153 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1158 Inst = TmpInst;
1159 break;
1160 }
1161 case PPC::CLRRDI:
1162 case PPC::CLRRDI_rec: {
1163 MCInst TmpInst;
1165 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
1170 Inst = TmpInst;
1171 break;
1172 }
1173 case PPC::CLRLSLDI:
1174 case PPC::CLRLSLDI_rec: {
1175 MCInst TmpInst;
1178 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
1183 Inst = TmpInst;
1184 break;
1185 }
1186 case PPC::RLWINMbm:
1187 case PPC::RLWINMbm_rec: {
1188 unsigned MB, ME;
1191 break;
1192
1193 MCInst TmpInst;
1194 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
1200 Inst = TmpInst;
1201 break;
1202 }
1203 case PPC::RLWIMIbm:
1204 case PPC::RLWIMIbm_rec: {
1205 unsigned MB, ME;
1208 break;
1209
1210 MCInst TmpInst;
1211 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
1218 Inst = TmpInst;
1219 break;
1220 }
1221 case PPC::RLWNMbm:
1222 case PPC::RLWNMbm_rec: {
1223 unsigned MB, ME;
1226 break;
1227
1228 MCInst TmpInst;
1229 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
1235 Inst = TmpInst;
1236 break;
1237 }
1238 case PPC::MFTB: {
1239 if (getSTI().hasFeature(PPC::FeatureMFTB)) {
1242 }
1243 break;
1244 }
1245 }
1246}
1247
1249 unsigned VariantID = 0);
1250
1251
1252
1253
1255 for (size_t idx = 0; idx < Operands.size(); ++idx) {
1256 const PPCOperand &Op = static_cast<const PPCOperand &>(*Operands[idx]);
1257 if (Op.isMemOpBase() != (idx == 3 && isMemriOp))
1258 return false;
1259 }
1260 return true;
1261}
1262
1263bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1265 MCStreamer &Out, uint64_t &ErrorInfo,
1266 bool MatchingInlineAsm) {
1267 MCInst Inst;
1268 const PPCInstrInfo *TII = static_cast<const PPCInstrInfo *>(&MII);
1269
1270 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1271 case Match_Success:
1273 return Error(IDLoc, "invalid operand for instruction");
1274
1275 processInstruction(Inst, Operands);
1278 return false;
1279 case Match_MissingFeature:
1280 return Error(IDLoc, "instruction use requires an option to be enabled");
1281 case Match_MnemonicFail: {
1282 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1284 ((PPCOperand &)*Operands[0]).getToken(), FBS);
1285 return Error(IDLoc, "invalid instruction" + Suggestion,
1286 ((PPCOperand &)*Operands[0]).getLocRange());
1287 }
1288 case Match_InvalidOperand: {
1289 SMLoc ErrorLoc = IDLoc;
1290 if (ErrorInfo != ~0ULL) {
1291 if (ErrorInfo >= Operands.size())
1292 return Error(IDLoc, "too few operands for instruction");
1293
1294 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1295 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1296 }
1297
1298 return Error(ErrorLoc, "invalid operand for instruction");
1299 }
1300 }
1301
1303}
1304
1305#define GET_REGISTER_MATCHER
1306#include "PPCGenAsmMatcher.inc"
1307
1308MCRegister PPCAsmParser::matchRegisterName(int64_t &IntVal) {
1310 getParser().Lex();
1311
1314
1315
1316
1317 std::string NameBuf = getParser().getTok().getString().lower();
1320 if (!RegNo)
1321 return RegNo;
1322
1323 Name.substr(Name.find_first_of("1234567890")).getAsInteger(10, IntVal);
1324
1325
1326
1327 if (Name == "lr") {
1328 RegNo = isPPC64() ? PPC::LR8 : PPC::LR;
1329 IntVal = 8;
1330 } else if (Name == "ctr") {
1331 RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR;
1332 IntVal = 9;
1333 } else if (Name == "vrsave")
1334 IntVal = 256;
1335 else if (Name.starts_with("r"))
1336 RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal];
1337
1338 getParser().Lex();
1339 return RegNo;
1340}
1341
1342bool PPCAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1343 SMLoc &EndLoc) {
1344 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
1345 return TokError("invalid register name");
1346 return false;
1347}
1348
1349ParseStatus PPCAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1350 SMLoc &EndLoc) {
1351 const AsmToken &Tok = getParser().getTok();
1352 StartLoc = Tok.getLoc();
1355 if (!(Reg = matchRegisterName(IntVal)))
1358}
1359
1360
1361
1362
1363const MCExpr *PPCAsmParser::extractSpecifier(const MCExpr *E,
1365 MCContext &Context = getParser().getContext();
1366 switch (E->getKind()) {
1368 break;
1370
1372 Spec = TE->getSpecifier();
1373 (void)extractSpecifier(TE->getSubExpr(), Spec);
1375 } break;
1376
1381 default:
1382 break;
1394 else
1395 Error(E->getLoc(), "cannot contain more than one relocation specifier");
1397 }
1398 break;
1399 }
1400
1403 const MCExpr *Sub = extractSpecifier(UE->getSubExpr(), Spec);
1406 break;
1407 }
1408
1411 const MCExpr *LHS = extractSpecifier(BE->getLHS(), Spec);
1412 const MCExpr *RHS = extractSpecifier(BE->getRHS(), Spec);
1415 break;
1416 }
1419 }
1420
1421 return E;
1422}
1423
1424
1425
1426bool PPCAsmParser::parseExpression(const MCExpr *&EVal) {
1427
1428
1429 if (getParser().parseExpression(EVal))
1430 return true;
1431
1433 const MCExpr *E = extractSpecifier(EVal, Spec);
1436
1437 return false;
1438}
1439
1440
1441
1442bool PPCAsmParser::parseOperand(OperandVector &Operands) {
1443 MCAsmParser &Parser = getParser();
1446 const MCExpr *EVal;
1447
1448
1449 switch (getLexer().getKind()) {
1450
1451
1454 if (!matchRegisterName(IntVal))
1455 return Error(S, "invalid register name");
1456
1457 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1458 return false;
1459 }
1469 if (!parseExpression(EVal))
1470 break;
1471
1472 [[fallthrough]];
1473 default:
1474 return Error(S, "unknown operand");
1475 }
1476
1477
1478 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1479
1480
1481 const char TlsGetAddr[] = "__tls_get_addr";
1482 bool TlsCall = false;
1483 const MCExpr *TlsCallAddend = nullptr;
1485 TlsCall = Ref->getSymbol().getName() == TlsGetAddr;
1489 TlsCall = Ref->getSymbol().getName() == TlsGetAddr;
1490 TlsCallAddend = Bin->getRHS();
1491 }
1492 }
1493
1495 const MCExpr *TLSSym;
1497 if (parseExpression(TLSSym))
1498 return Error(S2, "invalid TLS call expression");
1501 return true;
1502
1503 if (!isPPC64() && parseOptionalToken(AsmToken::At)) {
1504 AsmToken Tok = getTok();
1507 return Error(Tok.getLoc(), "expected 'plt'");
1511 const MCExpr *Addend = nullptr;
1512 SMLoc EndLoc;
1513 if (parsePrimaryExpr(Addend, EndLoc))
1514 return true;
1515 if (TlsCallAddend)
1516 TlsCallAddend =
1518 else
1519 TlsCallAddend = Addend;
1520 }
1521 if (TlsCallAddend)
1523
1524 Operands.back() = PPCOperand::CreateFromMCExpr(
1526 }
1527
1528 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1529 }
1530
1531
1534
1536 switch (getLexer().getKind()) {
1538 if (!matchRegisterName(IntVal))
1539 return Error(S, "invalid register name");
1540 break;
1541 }
1543 if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1544 IntVal > 31)
1545 return Error(S, "invalid register number");
1546 break;
1548 default:
1549 return Error(S, "invalid memory operand");
1550 }
1551
1554 return true;
1556 PPCOperand::CreateImm(IntVal, S, E, isPPC64(), true));
1557 }
1558
1559 return false;
1560}
1561
1562
1563bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
1565
1566
1567
1568 std::string NewOpcode;
1570 NewOpcode = std::string(Name);
1571 NewOpcode += '+';
1572 Name = NewOpcode;
1573 }
1575 NewOpcode = std::string(Name);
1576 NewOpcode += '-';
1577 Name = NewOpcode;
1578 }
1579
1580
1581 size_t Dot = Name.find('.');
1582 StringRef Mnemonic = Name.slice(0, Dot);
1583 if (!NewOpcode.empty())
1585 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1586 else
1587 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1590 StringRef DotStr = Name.substr(Dot);
1591 if (!NewOpcode.empty())
1593 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1594 else
1595 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1596 }
1597
1598
1600 return false;
1601
1602
1603 if (parseOperand(Operands))
1604 return true;
1605
1607 if (parseToken(AsmToken::Comma) || parseOperand(Operands))
1608 return true;
1609 }
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619 if (getSTI().hasFeature(PPC::FeatureBookE) &&
1620 Operands.size() == 4 &&
1621 (Name == "dcbt" || Name == "dcbtst")) {
1622 std::swap(Operands[1], Operands[3]);
1623 std::swap(Operands[2], Operands[1]);
1624 }
1625
1626
1627 if (Name == "lqarx" || Name == "ldarx" || Name == "lwarx" ||
1628 Name == "lharx" || Name == "lbarx") {
1629 if (Operands.size() != 5)
1630 return false;
1631 PPCOperand &EHOp = (PPCOperand &)*Operands[4];
1632 if (EHOp.isUImm<1>() && EHOp.getImm() == 0)
1634 }
1635
1636 return false;
1637}
1638
1639
1640bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1642 if (IDVal == ".word")
1643 parseDirectiveWord(2, DirectiveID);
1644 else if (IDVal == ".llong")
1645 parseDirectiveWord(8, DirectiveID);
1646 else if (IDVal == ".tc")
1647 parseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1648 else if (IDVal == ".machine")
1649 parseDirectiveMachine(DirectiveID.getLoc());
1650 else if (IDVal == ".abiversion")
1651 parseDirectiveAbiVersion(DirectiveID.getLoc());
1652 else if (IDVal == ".localentry")
1653 parseDirectiveLocalEntry(DirectiveID.getLoc());
1654 else if (IDVal.starts_with(".gnu_attribute"))
1655 parseGNUAttribute(DirectiveID.getLoc());
1656 else
1657 return true;
1658 return false;
1659}
1660
1661
1662bool PPCAsmParser::parseDirectiveWord(unsigned Size, AsmToken ID) {
1663 auto parseOp = [&]() -> bool {
1664 const MCExpr *Value;
1665 SMLoc ExprLoc = getParser().getTok().getLoc();
1666 if (getParser().parseExpression(Value))
1667 return true;
1669 assert(Size <= 8 && "Invalid size");
1670 uint64_t IntValue = MCE->getValue();
1672 return Error(ExprLoc, "literal value out of range for '" +
1673 ID.getIdentifier() + "' directive");
1674 getStreamer().emitIntValue(IntValue, Size);
1675 } else
1676 getStreamer().emitValue(Value, Size, ExprLoc);
1677 return false;
1678 };
1679
1680 if (parseMany(parseOp))
1681 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1682 return false;
1683}
1684
1685
1686bool PPCAsmParser::parseDirectiveTC(unsigned Size, AsmToken ID) {
1687 MCAsmParser &Parser = getParser();
1688
1691 Parser.Lex();
1693 return addErrorSuffix(" in '.tc' directive");
1694
1695
1696 getParser().getStreamer().emitValueToAlignment(Align(Size));
1697
1698
1699 return parseDirectiveWord(Size, ID);
1700}
1701
1702
1703
1704bool PPCAsmParser::parseDirectiveMachine(SMLoc L) {
1705 MCAsmParser &Parser = getParser();
1708 return Error(L, "unexpected token in '.machine' directive");
1709
1711
1712
1713
1714
1715
1716 Parser.Lex();
1717
1719 return addErrorSuffix(" in '.machine' directive");
1720
1721 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1722 getParser().getStreamer().getTargetStreamer());
1723 if (TStreamer != nullptr)
1725
1726 return false;
1727}
1728
1729
1730bool PPCAsmParser::parseDirectiveAbiVersion(SMLoc L) {
1731 int64_t AbiVersion;
1732 if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1733 "expected constant expression") ||
1735 return addErrorSuffix(" in '.abiversion' directive");
1736
1737 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1738 getParser().getStreamer().getTargetStreamer());
1739 if (TStreamer != nullptr)
1741
1742 return false;
1743}
1744
1745
1746bool PPCAsmParser::parseDirectiveLocalEntry(SMLoc L) {
1747 StringRef Name;
1748 if (getParser().parseIdentifier(Name))
1749 return Error(L, "expected identifier in '.localentry' directive");
1750
1751 auto *Sym = static_cast<MCSymbolELF *>(getContext().getOrCreateSymbol(Name));
1752 const MCExpr *Expr;
1753
1755 check(getParser().parseExpression(Expr), L, "expected expression") ||
1757 return addErrorSuffix(" in '.localentry' directive");
1758
1759 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1760 getParser().getStreamer().getTargetStreamer());
1761 if (TStreamer != nullptr)
1763
1764 return false;
1765}
1766
1767bool PPCAsmParser::parseGNUAttribute(SMLoc L) {
1768 int64_t Tag;
1769 int64_t IntegerValue;
1770 if (!getParser().parseGNUAttribute(L, Tag, IntegerValue))
1771 return false;
1772
1773 getParser().getStreamer().emitGNUAttribute(Tag, IntegerValue);
1774
1775 return true;
1776}
1777
1778
1786
1787#define GET_MATCHER_IMPLEMENTATION
1788#define GET_MNEMONIC_SPELL_CHECKER
1789#include "PPCGenAsmMatcher.inc"
1790
1791
1792
1793unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1794 unsigned Kind) {
1795
1796
1797
1798 int64_t ImmVal;
1799 switch (Kind) {
1800 case MCK_0: ImmVal = 0; break;
1801 case MCK_1: ImmVal = 1; break;
1802 case MCK_2: ImmVal = 2; break;
1803 case MCK_3: ImmVal = 3; break;
1804 case MCK_4: ImmVal = 4; break;
1805 case MCK_5: ImmVal = 5; break;
1806 case MCK_6: ImmVal = 6; break;
1807 case MCK_7: ImmVal = 7; break;
1808 default: return Match_InvalidOperand;
1809 }
1810
1811 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1812 if (Op.isUImm<3>() && Op.getImm() == ImmVal)
1813 return Match_Success;
1814
1815 return Match_InvalidOperand;
1816}
1817
1818const MCExpr *PPCAsmParser::applySpecifier(const MCExpr *E, uint32_t Spec,
1819 MCContext &Ctx) {
1831 break;
1832 default:
1833 return nullptr;
1834 }
1835 }
1836
1838}
static MCRegister MatchRegisterName(StringRef Name)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
static bool getRegNum(StringRef Str, unsigned &Num)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static AMDGPUMCExpr::Specifier getSpecifier(unsigned MOFlags)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
static bool validateMemOp(const OperandVector &Operands, bool isMemriOp)
Definition PPCAsmParser.cpp:1254
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser()
Force static initialization.
Definition PPCAsmParser.cpp:1780
static DEFINE_PPC_REGCLASSES int64_t EvaluateCRExpr(const MCExpr *E)
Definition PPCAsmParser.cpp:39
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Definition PPCAsmParser.cpp:795
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
#define DEFINE_PPC_REGCLASSES
LLVM_ABI SMLoc getLoc() const
bool isNot(TokenKind K) const
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
LLVM_ABI SMLoc getEndLoc() const
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Container class for subtarget features.
This class is intended to be used as a base class for asm properties and features specific to the tar...
void printExpr(raw_ostream &, const MCExpr &) const
bool Warning(SMLoc L, const Twine &Msg)
Generic assembler parser interface, for use by target specific assembly parsers.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
Binary assembler expressions.
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Opcode getOpcode() const
Get the kind of this binary expression.
static LLVM_ABI const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ Unary
Unary expressions.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Specifier
Expression with a relocation specifier.
@ Binary
Binary expressions.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
static const MCSpecifierExpr * create(const MCExpr *Expr, Spec S, MCContext &Ctx, SMLoc Loc=SMLoc())
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Represent a reference to a symbol from inside an expression.
const MCSymbol & getSymbol() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())
StringRef getName() const
getName - Get the symbol name.
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Unary assembler expressions.
Opcode getOpcode() const
Get the kind of this unary expression.
static LLVM_ABI const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
const MCExpr * getSubExpr() const
Get the child of this unary expression.
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
virtual void emitAbiVersion(int AbiVersion)
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)
virtual void emitMachine(StringRef CPU)
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
static SMLoc getFromPointer(const char *Ptr)
constexpr const char * getPointer() const
void push_back(const T &Elt)
StringRef - Represent a constant reference to a string, i.e.
static constexpr size_t npos
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
LLVM_ABI int compare_insensitive(StringRef RHS) const
Compare two strings, ignoring case.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
MCExpr const & getExpr(MCExpr const &Expr)
bool evaluateAsConstant(const MCSpecifierExpr &Expr, int64_t &Res)
@ CE
Windows NT (Windows on ARM)
Context & getContext() const
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
Target & getThePPC64LETarget()
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
static bool isMem(const MachineInstr &MI, unsigned Op)
LLVM_ABI std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
constexpr bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Target & getThePPC32Target()
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool has_single_bit(T Value) noexcept
SmallVectorImpl< std::unique_ptr< MCParsedAsmOperand > > OperandVector
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa - Return true if the parameter to the template is an instance of one of the template type argu...
@ Ref
The access may reference the value stored in memory.
Target & getThePPC64Target()
@ Sub
Subtraction of integers.
DWARFExpression::Operation Op
Target & getThePPC32LETarget()
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
constexpr bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
static uint16_t getSpecifier(const MCSymbolRefExpr *SRE)
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...