Thumb2InstrInfo.cpp Source File (original) (raw)

34#include

36using namespace llvm;

40 cl::desc("Use old-style Thumb2 if-conversion heuristics"),

45 cl::desc("Prefer predicated Move to CSEL"),

54}

58 return 0;

59}

61void

68 return;

69 }

86 unsigned Count = 4;

87 while (Count && MBBI != E) {

88 if (MBBI->isDebugInstr()) {

90 continue;

91 }

92 if (MBBI->getOpcode() == ARM::t2IT) {

93 unsigned Mask = MBBI->getOperand(1).getImm();

94 if (Count == 4)

96 else {

97 unsigned MaskOn = 1 << Count;

98 unsigned MaskOff = ~(MaskOn - 1);

99 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);

100 }

101 return;

102 }

104 --Count;

105 }

106

107

108

109 }

110}

111

112bool

115 while (MBBI->isDebugInstr()) {

118 return false;

119 }

120

123}

124

128 bool PreferFalse) const {

129

130

131

134 Register DestReg = MI.getOperand(0).getReg();

135

137 return nullptr;

138

140 get(ARM::t2CSEL), DestReg)

141 .add(MI.getOperand(2))

142 .add(MI.getOperand(1))

143 .add(MI.getOperand(3));

144 SeenMIs.insert(NewMI);

145 return NewMI;

146 }

147 return RV;

148}

149

154 bool RenamableDest, bool RenamableSrc) const {

155

156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))

158

162}

163

166 Register SrcReg, bool isKill, int FI,

171 if (I != MBB.end()) DL = I->getDebugLoc();

172

178

179 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

186 return;

187 }

188

189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

190

191

192

195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);

196 }

197

200 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);

202 return;

203 }

204

207}

208

221 if (I != MBB.end()) DL = I->getDebugLoc();

222

223 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

229 return;

230 }

231

232 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

233

234

235

238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);

239 }

240

245

248 return;

249 }

250

253}

254

255void Thumb2InstrInfo::expandLoadStackGuard(

259

260 if (M.getStackProtectorGuard() == "tls") {

262 return;

263 }

264

265 const auto *GV = cast((*MI->memoperands_begin())->getValue());

267 if (Subtarget.isTargetELF() && !GV->isDSOLocal())

269 else if (!Subtarget.useMovt())

273 else

275}

276

278 bool NewMI,

279 unsigned OpIdx1,

280 unsigned OpIdx2) const {

281 switch (MI.getOpcode()) {

282 case ARM::MVE_VMAXNMAf16:

283 case ARM::MVE_VMAXNMAf32:

284 case ARM::MVE_VMINNMAf16:

285 case ARM::MVE_VMINNMAf32:

286

288 return nullptr;

289 }

291}

292

296

297

298

299

300 switch (MI.getOpcode()) {

301 case ARM::t2BTI:

302 case ARM::t2PAC:

303 case ARM::t2PACBTI:

304 case ARM::t2SG:

305 return true;

306 default:

307 break;

308 }

310}

311

315 Register BaseReg, int NumBytes,

318 unsigned MIFlags) {

319 if (NumBytes == 0 && DestReg != BaseReg) {

323 return;

324 }

325

326 bool isSub = NumBytes < 0;

327 if (isSub) NumBytes = -NumBytes;

328

329

330

331 if (DestReg != ARM::SP && DestReg != BaseReg &&

332 NumBytes >= 4096 &&

334 bool Fits = false;

335 if (NumBytes < 65536) {

336

340 Fits = true;

341 } else if ((NumBytes & 0xffff) == 0) {

342

345 .addImm(NumBytes >> 16)

347 Fits = true;

348 }

349

350 if (Fits) {

351 if (isSub) {

358 } else {

359

360

361

362

363

370 }

371 return;

372 }

373 }

374

375 while (NumBytes) {

376 unsigned ThisVal = NumBytes;

377 unsigned Opc = 0;

378 if (DestReg == ARM::SP && BaseReg != ARM::SP) {

379

384 BaseReg = ARM::SP;

385 continue;

386 }

387

388 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&

389 "Writing to SP, from other register.");

390

391

392 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {

393 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");

394 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;

400 break;

401 }

402 bool HasCCOut = true;

404 bool ToSP = DestReg == ARM::SP;

405 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;

406 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;

407 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;

408 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

409 Opc = isSub ? t2SUB : t2ADD;

410

411 if (ImmIsT2SO != -1) {

412 NumBytes = 0;

413 } else if (ThisVal < 4096) {

414

415

416 Opc = isSub ? t2SUBi12 : t2ADDi12;

417 HasCCOut = false;

418 NumBytes = 0;

419 } else {

420

421

423 ThisVal = ThisVal & llvm::rotr<uint32_t>(0xff000000U, RotAmt);

424 NumBytes &= ~ThisVal;

426 "Bit extraction didn't work?");

427 }

428

429

435 if (HasCCOut)

437

438 BaseReg = DestReg;

439 }

440}

441

442static unsigned

444{

445 switch (opcode) {

446 case ARM::t2LDRi12: return ARM::t2LDRi8;

447 case ARM::t2LDRHi12: return ARM::t2LDRHi8;

448 case ARM::t2LDRBi12: return ARM::t2LDRBi8;

449 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;

450 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;

451 case ARM::t2STRi12: return ARM::t2STRi8;

452 case ARM::t2STRBi12: return ARM::t2STRBi8;

453 case ARM::t2STRHi12: return ARM::t2STRHi8;

454 case ARM::t2PLDi12: return ARM::t2PLDi8;

455 case ARM::t2PLDWi12: return ARM::t2PLDWi8;

456 case ARM::t2PLIi12: return ARM::t2PLIi8;

457

458 case ARM::t2LDRi8:

459 case ARM::t2LDRHi8:

460 case ARM::t2LDRBi8:

461 case ARM::t2LDRSHi8:

462 case ARM::t2LDRSBi8:

463 case ARM::t2STRi8:

464 case ARM::t2STRBi8:

465 case ARM::t2STRHi8:

466 case ARM::t2PLDi8:

467 case ARM::t2PLDWi8:

468 case ARM::t2PLIi8:

469 return opcode;

470

471 default:

473 }

474}

475

476static unsigned

478{

479 switch (opcode) {

480 case ARM::t2LDRi8: return ARM::t2LDRi12;

481 case ARM::t2LDRHi8: return ARM::t2LDRHi12;

482 case ARM::t2LDRBi8: return ARM::t2LDRBi12;

483 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;

484 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;

485 case ARM::t2STRi8: return ARM::t2STRi12;

486 case ARM::t2STRBi8: return ARM::t2STRBi12;

487 case ARM::t2STRHi8: return ARM::t2STRHi12;

488 case ARM::t2PLDi8: return ARM::t2PLDi12;

489 case ARM::t2PLDWi8: return ARM::t2PLDWi12;

490 case ARM::t2PLIi8: return ARM::t2PLIi12;

491

492 case ARM::t2LDRi12:

493 case ARM::t2LDRHi12:

494 case ARM::t2LDRBi12:

495 case ARM::t2LDRSHi12:

496 case ARM::t2LDRSBi12:

497 case ARM::t2STRi12:

498 case ARM::t2STRBi12:

499 case ARM::t2STRHi12:

500 case ARM::t2PLDi12:

501 case ARM::t2PLDWi12:

502 case ARM::t2PLIi12:

503 return opcode;

504

505 default:

507 }

508}

509

510static unsigned

512{

513 switch (opcode) {

514 case ARM::t2LDRs: return ARM::t2LDRi12;

515 case ARM::t2LDRHs: return ARM::t2LDRHi12;

516 case ARM::t2LDRBs: return ARM::t2LDRBi12;

517 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;

518 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;

519 case ARM::t2STRs: return ARM::t2STRi12;

520 case ARM::t2STRBs: return ARM::t2STRBi12;

521 case ARM::t2STRHs: return ARM::t2STRHi12;

522 case ARM::t2PLDs: return ARM::t2PLDi12;

523 case ARM::t2PLDWs: return ARM::t2PLDWi12;

524 case ARM::t2PLIs: return ARM::t2PLIi12;

525

526 case ARM::t2LDRi12:

527 case ARM::t2LDRHi12:

528 case ARM::t2LDRBi12:

529 case ARM::t2LDRSHi12:

530 case ARM::t2LDRSBi12:

531 case ARM::t2STRi12:

532 case ARM::t2STRBi12:

533 case ARM::t2STRHi12:

534 case ARM::t2PLDi12:

535 case ARM::t2PLDWi12:

536 case ARM::t2PLIi12:

537 case ARM::t2LDRi8:

538 case ARM::t2LDRHi8:

539 case ARM::t2LDRBi8:

540 case ARM::t2LDRSHi8:

541 case ARM::t2LDRSBi8:

542 case ARM::t2STRi8:

543 case ARM::t2STRBi8:

544 case ARM::t2STRHi8:

545 case ARM::t2PLDi8:

546 case ARM::t2PLDWi8:

547 case ARM::t2PLIi8:

548 return opcode;

549

550 default:

552 }

553}

554

559 unsigned Opcode = MI.getOpcode();

562 bool isSub = false;

563

566 TII.getRegClass(Desc, FrameRegIdx, TRI, MF);

567

568

569 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)

571

572 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;

573 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {

574 Offset += MI.getOperand(FrameRegIdx+1).getImm();

575

578 .definesRegister(ARM::CPSR, nullptr)) {

579

580 MI.setDesc(TII.get(ARM::tMOVr));

581 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

582

583 do MI.removeOperand(FrameRegIdx+1);

584 while (MI.getNumOperands() > FrameRegIdx+1);

587 return true;

588 }

589

590 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);

591

594 isSub = true;

595 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));

596 } else {

597 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));

598 }

599

600

602 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

603 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

604

605 if (!HasCCOut)

608 return true;

609 }

610

612 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {

613 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12

614 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

615 MI.setDesc(TII.get(NewOpc));

616 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

617 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

618

619 if (HasCCOut)

620 MI.removeOperand(MI.getNumOperands()-1);

622 return true;

623 }

624

625

626

627 unsigned RotAmt = llvm::countl_zero(Offset);

628 unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xff000000U, RotAmt);

629

630

631 Offset &= ~ThisImmVal;

632

634 "Bit extraction didn't work?");

635 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);

636

637 if (!HasCCOut)

639 } else {

640

642 return false;

643

644

645

646 unsigned NewOpc = Opcode;

648 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();

649 if (OffsetReg != 0) {

650 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

652 }

653

654 MI.removeOperand(FrameRegIdx+1);

655 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);

658 }

659

660 unsigned NumBits = 0;

661 unsigned Scale = 1;

664

665

666

667 Offset += MI.getOperand(FrameRegIdx+1).getImm();

670 NumBits = 8;

671 isSub = true;

673 } else {

675 NumBits = 12;

676 }

678

682 InstrOffs *= -1;

683 NumBits = 8;

684 Scale = 4;

685 Offset += InstrOffs * 4;

686 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

689 isSub = true;

690 }

692

696 InstrOffs *= -1;

697 NumBits = 8;

698 Scale = 2;

699 Offset += InstrOffs * 2;

700 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

703 isSub = true;

704 }

708 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

709 unsigned OffsetMask;

713 default: NumBits = 7; OffsetMask = 0x0; break;

714 }

715

716 Scale = 1;

717 assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");

718 (void)OffsetMask;

720 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

721 NumBits = 8 + 2;

722

723 Scale = 1;

724 assert((Offset & 3) == 0 && "Can't encode this offset!");

726 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;

727 NumBits = 8;

728 Scale = 4;

729 assert((Offset & 3) == 0 && "Can't encode this offset!");

730 } else {

732 }

733

734 if (NewOpc != Opcode)

735 MI.setDesc(TII.get(NewOpc));

736

738

739

740

741

742

743 int ImmedOffset = Offset / Scale;

744 unsigned Mask = (1 << NumBits) - 1;

745 if ((unsigned)Offset <= Mask * Scale &&

748

750 if ( MRI ->constrainRegClass(FrameReg, RegClass))

751 llvm_unreachable("Unable to constrain virtual register class.");

752 }

753

754

755 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

756 if (isSub) {

758

759 ImmedOffset |= 1 << NumBits;

760 else

761 ImmedOffset = -ImmedOffset;

762 }

765 return true;

766 }

767

768

769 ImmedOffset = ImmedOffset & Mask;

770 if (isSub) {

772

773 ImmedOffset |= 1 << NumBits;

774 else {

775 ImmedOffset = -ImmedOffset;

776 if (ImmedOffset == 0)

777

779 }

780 }

782 Offset &= ~(Mask*Scale);

783 }

784

787}

788

791 unsigned Opc = MI.getOpcode();

792 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)

795}

796

799

800 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)

802 return i;

803

804 return -1;

805}

806

810 if (PIdx == -1) {

811 PredReg = 0;

813 }

814

815 PredReg = MI.getOperand(PIdx+1).getReg();

817}

818

820 assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");

821

823 assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");

824

826 End = Instr.getParent()->end();

827

828 while (Iter != End && Iter->isDebugInstr())

829 ++Iter;

830

831

832

833 assert(Iter != End && "Expected some instructions in any VPT block");

836 "VPT/VPST should be followed by an instruction with a 'then' predicate!");

837 ++Iter;

838

839

841 while (Iter != End) {

842 if (Iter->isDebugInstr()) {

843 ++Iter;

844 continue;

845 }

848 break;

850 ++Iter;

851 }

852

853

854 MaskOp.setImm((int64_t)(BlockMask));

855}

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const HexagonInstrInfo * TII

Module.h This file contains the declarations for the Module class.

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

static unsigned negativeOffsetOpcode(unsigned opcode)

static unsigned positiveOffsetOpcode(unsigned opcode)

static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))

static cl::opt< bool > PreferNoCSEL("prefer-no-csel", cl::Hidden, cl::desc("Prefer predicated Move to CSEL"), cl::init(false))

static unsigned immediateOffsetOpcode(unsigned opcode)

const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

const ARMSubtarget & getSubtarget() const

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...

Module * getParent()

Get the module that this global value is contained inside of...

MCInstBuilder & addReg(MCRegister Reg)

Add a new register operand.

MCInstBuilder & addImm(int64_t Val)

Add a new integer immediate operand.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

Wrapper class representing physical registers. Should be passed by value.

void eraseFromParent()

This method unlinks 'this' from the containing function and deletes it.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & setMIFlags(unsigned Flags) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const

Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...

bool isPositionIndependent() const

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

unsigned getUnindexedOpcode(unsigned Opc) const override

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

Thumb2InstrInfo(const ARMSubtarget &STI)

MCInst getNop() const override

Return the noop instruction to use for a noop.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned char getAM5FP16Offset(unsigned AM5Opc)

int getT2SOImmVal(unsigned Arg)

getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...

AddrOpc getAM5Op(unsigned AM5Opc)

AddrOpc getAM5FP16Op(unsigned AM5Opc)

unsigned char getAM5Offset(unsigned AM5Opc)

PredBlockMask

Mask values for IT and VPT Blocks, to be used by MCOperands.

bool isVpred(OperandType op)

@ Tail

Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...

@ Kill

The last use of a register.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

int findFirstVPTPredOperandIdx(const MachineInstr &MI)

ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static bool isVPTOpcode(int Opc)

bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

int countl_zero(T Val)

Count number of 0's from the most significant bit to the least stopping at the first 1.

ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)

getITInstrPredicate - Valid only in Thumb2 mode.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getKillRegState(bool B)

ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)

ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)

getInstrPredicate - If instruction is predicated, returns its predicate condition,...

static MachineOperand condCodeOp(unsigned CCReg=0)

Get the operand corresponding to the conditional code result.

void recomputeVPTBlockMask(MachineInstr &Instr)

void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)

Description of the encoding of one expression Op.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.