Thumb2InstrInfo.cpp Source File (original) (raw)

34#include

36using namespace llvm;

40 cl::desc("Use old-style Thumb2 if-conversion heuristics"),

45 cl::desc("Prefer predicated Move to CSEL"),

61void

68 return;

69 }

86 unsigned Count = 4;

88 if (MBBI->isDebugInstr()) {

90 continue;

91 }

92 if (MBBI->getOpcode() == ARM::t2IT) {

93 unsigned Mask = MBBI->getOperand(1).getImm();

95 MBBI->eraseFromParent();

96 else {

97 unsigned MaskOn = 1 << Count;

98 unsigned MaskOff = ~(MaskOn - 1);

99 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);

100 }

101 return;

102 }

105 }

106

107

108

109 }

110}

111

112bool

115 while (MBBI->isDebugInstr()) {

118 return false;

119 }

120

123}

124

128 bool PreferFalse) const {

129

130

131

134 Register DestReg = MI.getOperand(0).getReg();

135

137 return nullptr;

138

140 get(ARM::t2CSEL), DestReg)

141 .add(MI.getOperand(2))

142 .add(MI.getOperand(1))

143 .add(MI.getOperand(3));

144 SeenMIs.insert(NewMI);

145 return NewMI;

146 }

147 return RV;

148}

149

153 Register SrcReg, bool KillSrc,

154 bool RenamableDest, bool RenamableSrc) const {

155

156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))

158

162}

163

166 Register SrcReg, bool isKill, int FI,

171 if (I != MBB.end()) DL = I->getDebugLoc();

172

178

179 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

186 return;

187 }

188

189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

190

191

192

195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);

196 }

197

200 AddDReg(MIB, SrcReg, ARM::gsub_1, 0);

202 return;

203 }

204

207}

208

221 if (I != MBB.end()) DL = I->getDebugLoc();

222

223 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

229 return;

230 }

231

232 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

233

234

235

238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);

239 }

240

245

248 return;

249 }

250

252}

253

254void Thumb2InstrInfo::expandLoadStackGuard(

258

259 if (M.getStackProtectorGuard() == "tls") {

261 return;

262 }

263

264 const auto *GV = cast((*MI->memoperands_begin())->getValue());

267 if (Subtarget.isTargetELF() && !GV->isDSOLocal())

269 else if (!Subtarget.useMovt())

271 MI, IsPIC ? ARM::t2LDRLIT_ga_pcrel : ARM::tLDRLIT_ga_abs,

272 ARM::t2LDRi12);

273 else if (IsPIC)

275 else

277}

278

280 bool NewMI,

281 unsigned OpIdx1,

282 unsigned OpIdx2) const {

283 switch (MI.getOpcode()) {

284 case ARM::MVE_VMAXNMAf16:

285 case ARM::MVE_VMAXNMAf32:

286 case ARM::MVE_VMINNMAf16:

287 case ARM::MVE_VMINNMAf32:

288

290 return nullptr;

291 }

293}

294

298

299

300

301

302 switch (MI.getOpcode()) {

303 case ARM::t2BTI:

304 case ARM::t2PAC:

305 case ARM::t2PACBTI:

306 case ARM::t2SG:

307 return true;

308 default:

309 break;

310 }

312}

313

317 Register BaseReg, int NumBytes,

320 unsigned MIFlags) {

321 if (NumBytes == 0 && DestReg != BaseReg) {

325 return;

326 }

327

328 bool isSub = NumBytes < 0;

329 if (isSub) NumBytes = -NumBytes;

330

331

332

333 if (DestReg != ARM::SP && DestReg != BaseReg &&

334 NumBytes >= 4096 &&

336 bool Fits = false;

337 if (NumBytes < 65536) {

338

342 Fits = true;

343 } else if ((NumBytes & 0xffff) == 0) {

344

347 .addImm(NumBytes >> 16)

349 Fits = true;

350 }

351

352 if (Fits) {

353 if (isSub) {

360 } else {

361

362

363

364

365

372 }

373 return;

374 }

375 }

376

377 while (NumBytes) {

378 unsigned ThisVal = NumBytes;

379 unsigned Opc = 0;

380 if (DestReg == ARM::SP && BaseReg != ARM::SP) {

381

386 BaseReg = ARM::SP;

387 continue;

388 }

389

390 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&

391 "Writing to SP, from other register.");

392

393

394 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {

395 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");

396 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;

402 break;

403 }

404 bool HasCCOut = true;

406 bool ToSP = DestReg == ARM::SP;

407 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;

408 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;

409 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;

410 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

411 Opc = isSub ? t2SUB : t2ADD;

412

413 if (ImmIsT2SO != -1) {

414 NumBytes = 0;

415 } else if (ThisVal < 4096) {

416

417

418 Opc = isSub ? t2SUBi12 : t2ADDi12;

419 HasCCOut = false;

420 NumBytes = 0;

421 } else {

422

423

426 NumBytes &= ~ThisVal;

428 "Bit extraction didn't work?");

429 }

430

431

437 if (HasCCOut)

439

440 BaseReg = DestReg;

441 }

442}

443

444static unsigned

446{

447 switch (opcode) {

448 case ARM::t2LDRi12: return ARM::t2LDRi8;

449 case ARM::t2LDRHi12: return ARM::t2LDRHi8;

450 case ARM::t2LDRBi12: return ARM::t2LDRBi8;

451 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;

452 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;

453 case ARM::t2STRi12: return ARM::t2STRi8;

454 case ARM::t2STRBi12: return ARM::t2STRBi8;

455 case ARM::t2STRHi12: return ARM::t2STRHi8;

456 case ARM::t2PLDi12: return ARM::t2PLDi8;

457 case ARM::t2PLDWi12: return ARM::t2PLDWi8;

458 case ARM::t2PLIi12: return ARM::t2PLIi8;

459

460 case ARM::t2LDRi8:

461 case ARM::t2LDRHi8:

462 case ARM::t2LDRBi8:

463 case ARM::t2LDRSHi8:

464 case ARM::t2LDRSBi8:

465 case ARM::t2STRi8:

466 case ARM::t2STRBi8:

467 case ARM::t2STRHi8:

468 case ARM::t2PLDi8:

469 case ARM::t2PLDWi8:

470 case ARM::t2PLIi8:

471 return opcode;

472

473 default:

475 }

476}

477

478static unsigned

480{

481 switch (opcode) {

482 case ARM::t2LDRi8: return ARM::t2LDRi12;

483 case ARM::t2LDRHi8: return ARM::t2LDRHi12;

484 case ARM::t2LDRBi8: return ARM::t2LDRBi12;

485 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;

486 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;

487 case ARM::t2STRi8: return ARM::t2STRi12;

488 case ARM::t2STRBi8: return ARM::t2STRBi12;

489 case ARM::t2STRHi8: return ARM::t2STRHi12;

490 case ARM::t2PLDi8: return ARM::t2PLDi12;

491 case ARM::t2PLDWi8: return ARM::t2PLDWi12;

492 case ARM::t2PLIi8: return ARM::t2PLIi12;

493

494 case ARM::t2LDRi12:

495 case ARM::t2LDRHi12:

496 case ARM::t2LDRBi12:

497 case ARM::t2LDRSHi12:

498 case ARM::t2LDRSBi12:

499 case ARM::t2STRi12:

500 case ARM::t2STRBi12:

501 case ARM::t2STRHi12:

502 case ARM::t2PLDi12:

503 case ARM::t2PLDWi12:

504 case ARM::t2PLIi12:

505 return opcode;

506

507 default:

509 }

510}

511

512static unsigned

514{

515 switch (opcode) {

516 case ARM::t2LDRs: return ARM::t2LDRi12;

517 case ARM::t2LDRHs: return ARM::t2LDRHi12;

518 case ARM::t2LDRBs: return ARM::t2LDRBi12;

519 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;

520 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;

521 case ARM::t2STRs: return ARM::t2STRi12;

522 case ARM::t2STRBs: return ARM::t2STRBi12;

523 case ARM::t2STRHs: return ARM::t2STRHi12;

524 case ARM::t2PLDs: return ARM::t2PLDi12;

525 case ARM::t2PLDWs: return ARM::t2PLDWi12;

526 case ARM::t2PLIs: return ARM::t2PLIi12;

527

528 case ARM::t2LDRi12:

529 case ARM::t2LDRHi12:

530 case ARM::t2LDRBi12:

531 case ARM::t2LDRSHi12:

532 case ARM::t2LDRSBi12:

533 case ARM::t2STRi12:

534 case ARM::t2STRBi12:

535 case ARM::t2STRHi12:

536 case ARM::t2PLDi12:

537 case ARM::t2PLDWi12:

538 case ARM::t2PLIi12:

539 case ARM::t2LDRi8:

540 case ARM::t2LDRHi8:

541 case ARM::t2LDRBi8:

542 case ARM::t2LDRSHi8:

543 case ARM::t2LDRSBi8:

544 case ARM::t2STRi8:

545 case ARM::t2STRBi8:

546 case ARM::t2STRHi8:

547 case ARM::t2PLDi8:

548 case ARM::t2PLDWi8:

549 case ARM::t2PLIi8:

550 return opcode;

551

552 default:

554 }

555}

556

561 unsigned Opcode = MI.getOpcode();

564 bool isSub = false;

565

568

569

570 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)

572

573 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;

574 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {

575 Offset += MI.getOperand(FrameRegIdx+1).getImm();

576

579 .definesRegister(ARM::CPSR, nullptr)) {

580

581 MI.setDesc(TII.get(ARM::tMOVr));

582 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

583

584 do MI.removeOperand(FrameRegIdx+1);

585 while (MI.getNumOperands() > FrameRegIdx+1);

588 return true;

589 }

590

591 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);

592

595 isSub = true;

596 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));

597 } else {

598 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));

599 }

600

601

603 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

604 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

605

606 if (!HasCCOut)

609 return true;

610 }

611

613 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {

614 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12

615 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

616 MI.setDesc(TII.get(NewOpc));

617 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

618 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

619

620 if (HasCCOut)

621 MI.removeOperand(MI.getNumOperands()-1);

623 return true;

624 }

625

626

627

630

631

632 Offset &= ~ThisImmVal;

633

635 "Bit extraction didn't work?");

636 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);

637

638 if (!HasCCOut)

640 } else {

641

643 return false;

644

645

646

647 unsigned NewOpc = Opcode;

649 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();

650 if (OffsetReg != 0) {

651 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

653 }

654

655 MI.removeOperand(FrameRegIdx+1);

656 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);

659 }

660

661 unsigned NumBits = 0;

662 unsigned Scale = 1;

665

666

667

668 Offset += MI.getOperand(FrameRegIdx+1).getImm();

671 NumBits = 8;

672 isSub = true;

674 } else {

676 NumBits = 12;

677 }

679

683 InstrOffs *= -1;

684 NumBits = 8;

685 Scale = 4;

686 Offset += InstrOffs * 4;

687 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

690 isSub = true;

691 }

693

697 InstrOffs *= -1;

698 NumBits = 8;

699 Scale = 2;

700 Offset += InstrOffs * 2;

701 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

704 isSub = true;

705 }

709 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

710 unsigned OffsetMask;

714 default: NumBits = 7; OffsetMask = 0x0; break;

715 }

716

717 Scale = 1;

718 assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");

719 (void)OffsetMask;

721 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

722 NumBits = 8 + 2;

723

724 Scale = 1;

725 assert((Offset & 3) == 0 && "Can't encode this offset!");

727 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;

728 NumBits = 8;

729 Scale = 4;

730 assert((Offset & 3) == 0 && "Can't encode this offset!");

731 } else {

733 }

734

735 if (NewOpc != Opcode)

736 MI.setDesc(TII.get(NewOpc));

737

739

740

741

742

743

744 int ImmedOffset = Offset / Scale;

745 unsigned Mask = (1 << NumBits) - 1;

746 if ((unsigned)Offset <= Mask * Scale &&

749

751 if ( MRI ->constrainRegClass(FrameReg, RegClass))

752 llvm_unreachable("Unable to constrain virtual register class.");

753 }

754

755

756 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

757 if (isSub) {

759

760 ImmedOffset |= 1 << NumBits;

761 else

762 ImmedOffset = -ImmedOffset;

763 }

766 return true;

767 }

768

769

770 ImmedOffset = ImmedOffset & Mask;

771 if (isSub) {

773

774 ImmedOffset |= 1 << NumBits;

775 else {

776 ImmedOffset = -ImmedOffset;

777 if (ImmedOffset == 0)

778

780 }

781 }

783 Offset &= ~(Mask*Scale);

784 }

785

788}

789

792 unsigned Opc = MI.getOpcode();

793 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)

796}

797

800

801 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)

803 return i;

804

805 return -1;

806}

807

810

811 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)

813 return i + ARM::SUBOP_vpred_r_inactive;

814

815 return -1;

816}

817

821 if (PIdx == -1) {

822 PredReg = 0;

824 }

825

826 PredReg = MI.getOperand(PIdx+1).getReg();

828}

829

831 assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");

832

834 assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");

835

837 End = Instr.getParent()->end();

838

839 while (Iter != End && Iter->isDebugInstr())

840 ++Iter;

841

842

843

844 assert(Iter != End && "Expected some instructions in any VPT block");

847 "VPT/VPST should be followed by an instruction with a 'then' predicate!");

848 ++Iter;

849

850

852 while (Iter != End) {

853 if (Iter->isDebugInstr()) {

854 ++Iter;

855 continue;

856 }

859 break;

861 ++Iter;

862 }

863

864

865 MaskOp.setImm((int64_t)(BlockMask));

866}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Module.h This file contains the declarations for the Module class.

Promote Memory to Register

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

static unsigned negativeOffsetOpcode(unsigned opcode)

Definition Thumb2InstrInfo.cpp:445

static unsigned positiveOffsetOpcode(unsigned opcode)

Definition Thumb2InstrInfo.cpp:479

static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))

static cl::opt< bool > PreferNoCSEL("prefer-no-csel", cl::Hidden, cl::desc("Prefer predicated Move to CSEL"), cl::init(false))

static unsigned immediateOffsetOpcode(unsigned opcode)

Definition Thumb2InstrInfo.cpp:513

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State) const

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

ARMBaseInstrInfo(const ARMSubtarget &STI, const ARMBaseRegisterInfo &TRI)

const ARMSubtarget & getSubtarget() const

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...

Module * getParent()

Get the module that this global value is contained inside of...

MCInstBuilder & addReg(MCRegister Reg)

Add a new register operand.

MCInstBuilder & addImm(int64_t Val)

Add a new integer immediate operand.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & setMIFlags(unsigned Flags) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

LLVM_ABI void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const

Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...

bool isPositionIndependent() const

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override

Definition Thumb2InstrInfo.cpp:113

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

Definition Thumb2InstrInfo.cpp:295

unsigned getUnindexedOpcode(unsigned Opc) const override

Definition Thumb2InstrInfo.cpp:56

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Definition Thumb2InstrInfo.cpp:279

void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override

Definition Thumb2InstrInfo.cpp:62

Definition Thumb2InstrInfo.cpp:150

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

Definition Thumb2InstrInfo.cpp:126

Thumb2InstrInfo(const ARMSubtarget &STI)

Definition Thumb2InstrInfo.cpp:48

Definition Thumb2InstrInfo.cpp:209

MCInst getNop() const override

Return the noop instruction to use for a noop.

Definition Thumb2InstrInfo.cpp:52

Definition Thumb2InstrInfo.cpp:164

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned char getAM5FP16Offset(unsigned AM5Opc)

int getT2SOImmVal(unsigned Arg)

getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...

AddrOpc getAM5Op(unsigned AM5Opc)

AddrOpc getAM5FP16Op(unsigned AM5Opc)

unsigned char getAM5Offset(unsigned AM5Opc)

PredBlockMask

Mask values for IT and VPT Blocks, to be used by MCOperands.

bool isVpred(OperandType op)

@ Tail

Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...

@ Kill

The last use of a register.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

int findVPTInactiveOperandIdx(const MachineInstr &MI)

Definition Thumb2InstrInfo.cpp:808

constexpr T rotr(T V, int R)

int findFirstVPTPredOperandIdx(const MachineInstr &MI)

Definition Thumb2InstrInfo.cpp:798

ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)

Definition Thumb2InstrInfo.cpp:818

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static bool isVPTOpcode(int Opc)

bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)

Definition Thumb2InstrInfo.cpp:557

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

int countl_zero(T Val)

Count number of 0's from the most significant bit to the least stopping at the first 1.

ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)

getITInstrPredicate - Valid only in Thumb2 mode.

Definition Thumb2InstrInfo.cpp:790

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

FunctionAddr VTableAddr Count

unsigned getKillRegState(bool B)

ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)

ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)

getInstrPredicate - If instruction is predicated, returns its predicate condition,...

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

static MachineOperand condCodeOp(unsigned CCReg=0)

Get the operand corresponding to the conditional code result.

void recomputeVPTBlockMask(MachineInstr &Instr)

Definition Thumb2InstrInfo.cpp:830

void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)

Definition Thumb2InstrInfo.cpp:314

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.