Thumb2InstrInfo.cpp Source File (original) (raw)

34#include

36using namespace llvm;

40 cl::desc("Use old-style Thumb2 if-conversion heuristics"),

45 cl::desc("Prefer predicated Move to CSEL"),

54}

58 return 0;

59}

61void

68 return;

69 }

86 unsigned Count = 4;

87 while (Count && MBBI != E) {

88 if (MBBI->isDebugInstr()) {

90 continue;

91 }

92 if (MBBI->getOpcode() == ARM::t2IT) {

93 unsigned Mask = MBBI->getOperand(1).getImm();

94 if (Count == 4)

96 else {

97 unsigned MaskOn = 1 << Count;

98 unsigned MaskOff = ~(MaskOn - 1);

99 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);

100 }

101 return;

102 }

104 --Count;

105 }

106

107

108

109 }

110}

111

112bool

115 while (MBBI->isDebugInstr()) {

118 return false;

119 }

120

123}

124

128 bool PreferFalse) const {

129

130

131

134 Register DestReg = MI.getOperand(0).getReg();

135

137 return nullptr;

138

140 get(ARM::t2CSEL), DestReg)

141 .add(MI.getOperand(2))

142 .add(MI.getOperand(1))

143 .add(MI.getOperand(3));

144 SeenMIs.insert(NewMI);

145 return NewMI;

146 }

147 return RV;

148}

149

154 bool RenamableDest, bool RenamableSrc) const {

155

156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))

158

162}

163

166 Register SrcReg, bool isKill, int FI,

172 if (I != MBB.end()) DL = I->getDebugLoc();

173

179

180 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

187 return;

188 }

189

190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

191

192

193

196 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);

197 }

198

201 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);

203 return;

204 }

205

208}

209

220 if (I != MBB.end()) DL = I->getDebugLoc();

221

222 if (ARM::GPRRegClass.hasSubClassEq(RC)) {

228 return;

229 }

230

231 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {

232

233

234

237 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);

238 }

239

244

247 return;

248 }

249

252}

253

254void Thumb2InstrInfo::expandLoadStackGuard(

258

259 if (M.getStackProtectorGuard() == "tls") {

261 return;

262 }

263

264 const auto *GV = cast((*MI->memoperands_begin())->getValue());

266 if (Subtarget.isTargetELF() && !GV->isDSOLocal())

268 else if (!Subtarget.useMovt())

272 else

274}

275

277 bool NewMI,

278 unsigned OpIdx1,

279 unsigned OpIdx2) const {

280 switch (MI.getOpcode()) {

281 case ARM::MVE_VMAXNMAf16:

282 case ARM::MVE_VMAXNMAf32:

283 case ARM::MVE_VMINNMAf16:

284 case ARM::MVE_VMINNMAf32:

285

287 return nullptr;

288 }

290}

291

295

296

297

298

299 switch (MI.getOpcode()) {

300 case ARM::t2BTI:

301 case ARM::t2PAC:

302 case ARM::t2PACBTI:

303 case ARM::t2SG:

304 return true;

305 default:

306 break;

307 }

309}

310

314 Register BaseReg, int NumBytes,

317 unsigned MIFlags) {

318 if (NumBytes == 0 && DestReg != BaseReg) {

322 return;

323 }

324

325 bool isSub = NumBytes < 0;

326 if (isSub) NumBytes = -NumBytes;

327

328

329

330 if (DestReg != ARM::SP && DestReg != BaseReg &&

331 NumBytes >= 4096 &&

333 bool Fits = false;

334 if (NumBytes < 65536) {

335

339 Fits = true;

340 } else if ((NumBytes & 0xffff) == 0) {

341

344 .addImm(NumBytes >> 16)

346 Fits = true;

347 }

348

349 if (Fits) {

350 if (isSub) {

357 } else {

358

359

360

361

362

369 }

370 return;

371 }

372 }

373

374 while (NumBytes) {

375 unsigned ThisVal = NumBytes;

376 unsigned Opc = 0;

377 if (DestReg == ARM::SP && BaseReg != ARM::SP) {

378

383 BaseReg = ARM::SP;

384 continue;

385 }

386

387 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&

388 "Writing to SP, from other register.");

389

390

391 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {

392 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");

393 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;

399 break;

400 }

401 bool HasCCOut = true;

403 bool ToSP = DestReg == ARM::SP;

404 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;

405 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;

406 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;

407 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

408 Opc = isSub ? t2SUB : t2ADD;

409

410 if (ImmIsT2SO != -1) {

411 NumBytes = 0;

412 } else if (ThisVal < 4096) {

413

414

415 Opc = isSub ? t2SUBi12 : t2ADDi12;

416 HasCCOut = false;

417 NumBytes = 0;

418 } else {

419

420

422 ThisVal = ThisVal & llvm::rotr<uint32_t>(0xff000000U, RotAmt);

423 NumBytes &= ~ThisVal;

425 "Bit extraction didn't work?");

426 }

427

428

434 if (HasCCOut)

436

437 BaseReg = DestReg;

438 }

439}

440

441static unsigned

443{

444 switch (opcode) {

445 case ARM::t2LDRi12: return ARM::t2LDRi8;

446 case ARM::t2LDRHi12: return ARM::t2LDRHi8;

447 case ARM::t2LDRBi12: return ARM::t2LDRBi8;

448 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;

449 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;

450 case ARM::t2STRi12: return ARM::t2STRi8;

451 case ARM::t2STRBi12: return ARM::t2STRBi8;

452 case ARM::t2STRHi12: return ARM::t2STRHi8;

453 case ARM::t2PLDi12: return ARM::t2PLDi8;

454 case ARM::t2PLDWi12: return ARM::t2PLDWi8;

455 case ARM::t2PLIi12: return ARM::t2PLIi8;

456

457 case ARM::t2LDRi8:

458 case ARM::t2LDRHi8:

459 case ARM::t2LDRBi8:

460 case ARM::t2LDRSHi8:

461 case ARM::t2LDRSBi8:

462 case ARM::t2STRi8:

463 case ARM::t2STRBi8:

464 case ARM::t2STRHi8:

465 case ARM::t2PLDi8:

466 case ARM::t2PLDWi8:

467 case ARM::t2PLIi8:

468 return opcode;

469

470 default:

472 }

473}

474

475static unsigned

477{

478 switch (opcode) {

479 case ARM::t2LDRi8: return ARM::t2LDRi12;

480 case ARM::t2LDRHi8: return ARM::t2LDRHi12;

481 case ARM::t2LDRBi8: return ARM::t2LDRBi12;

482 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;

483 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;

484 case ARM::t2STRi8: return ARM::t2STRi12;

485 case ARM::t2STRBi8: return ARM::t2STRBi12;

486 case ARM::t2STRHi8: return ARM::t2STRHi12;

487 case ARM::t2PLDi8: return ARM::t2PLDi12;

488 case ARM::t2PLDWi8: return ARM::t2PLDWi12;

489 case ARM::t2PLIi8: return ARM::t2PLIi12;

490

491 case ARM::t2LDRi12:

492 case ARM::t2LDRHi12:

493 case ARM::t2LDRBi12:

494 case ARM::t2LDRSHi12:

495 case ARM::t2LDRSBi12:

496 case ARM::t2STRi12:

497 case ARM::t2STRBi12:

498 case ARM::t2STRHi12:

499 case ARM::t2PLDi12:

500 case ARM::t2PLDWi12:

501 case ARM::t2PLIi12:

502 return opcode;

503

504 default:

506 }

507}

508

509static unsigned

511{

512 switch (opcode) {

513 case ARM::t2LDRs: return ARM::t2LDRi12;

514 case ARM::t2LDRHs: return ARM::t2LDRHi12;

515 case ARM::t2LDRBs: return ARM::t2LDRBi12;

516 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;

517 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;

518 case ARM::t2STRs: return ARM::t2STRi12;

519 case ARM::t2STRBs: return ARM::t2STRBi12;

520 case ARM::t2STRHs: return ARM::t2STRHi12;

521 case ARM::t2PLDs: return ARM::t2PLDi12;

522 case ARM::t2PLDWs: return ARM::t2PLDWi12;

523 case ARM::t2PLIs: return ARM::t2PLIi12;

524

525 case ARM::t2LDRi12:

526 case ARM::t2LDRHi12:

527 case ARM::t2LDRBi12:

528 case ARM::t2LDRSHi12:

529 case ARM::t2LDRSBi12:

530 case ARM::t2STRi12:

531 case ARM::t2STRBi12:

532 case ARM::t2STRHi12:

533 case ARM::t2PLDi12:

534 case ARM::t2PLDWi12:

535 case ARM::t2PLIi12:

536 case ARM::t2LDRi8:

537 case ARM::t2LDRHi8:

538 case ARM::t2LDRBi8:

539 case ARM::t2LDRSHi8:

540 case ARM::t2LDRSBi8:

541 case ARM::t2STRi8:

542 case ARM::t2STRBi8:

543 case ARM::t2STRHi8:

544 case ARM::t2PLDi8:

545 case ARM::t2PLDWi8:

546 case ARM::t2PLIi8:

547 return opcode;

548

549 default:

551 }

552}

553

558 unsigned Opcode = MI.getOpcode();

561 bool isSub = false;

562

565 TII.getRegClass(Desc, FrameRegIdx, TRI, MF);

566

567

568 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)

570

571 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;

572 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {

573 Offset += MI.getOperand(FrameRegIdx+1).getImm();

574

577 .definesRegister(ARM::CPSR, nullptr)) {

578

579 MI.setDesc(TII.get(ARM::tMOVr));

580 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

581

582 do MI.removeOperand(FrameRegIdx+1);

583 while (MI.getNumOperands() > FrameRegIdx+1);

586 return true;

587 }

588

589 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);

590

593 isSub = true;

594 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));

595 } else {

596 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));

597 }

598

599

601 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

602 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

603

604 if (!HasCCOut)

607 return true;

608 }

609

611 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {

612 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12

613 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;

614 MI.setDesc(TII.get(NewOpc));

615 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

616 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);

617

618 if (HasCCOut)

619 MI.removeOperand(MI.getNumOperands()-1);

621 return true;

622 }

623

624

625

626 unsigned RotAmt = llvm::countl_zero(Offset);

627 unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xff000000U, RotAmt);

628

629

630 Offset &= ~ThisImmVal;

631

633 "Bit extraction didn't work?");

634 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);

635

636 if (!HasCCOut)

638 } else {

639

641 return false;

642

643

644

645 unsigned NewOpc = Opcode;

647 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();

648 if (OffsetReg != 0) {

649 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

651 }

652

653 MI.removeOperand(FrameRegIdx+1);

654 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);

657 }

658

659 unsigned NumBits = 0;

660 unsigned Scale = 1;

663

664

665

666 Offset += MI.getOperand(FrameRegIdx+1).getImm();

669 NumBits = 8;

670 isSub = true;

672 } else {

674 NumBits = 12;

675 }

677

681 InstrOffs *= -1;

682 NumBits = 8;

683 Scale = 4;

684 Offset += InstrOffs * 4;

685 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

688 isSub = true;

689 }

691

695 InstrOffs *= -1;

696 NumBits = 8;

697 Scale = 2;

698 Offset += InstrOffs * 2;

699 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");

702 isSub = true;

703 }

707 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

708 unsigned OffsetMask;

712 default: NumBits = 7; OffsetMask = 0x0; break;

713 }

714

715 Scale = 1;

716 assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");

717 (void)OffsetMask;

719 Offset += MI.getOperand(FrameRegIdx + 1).getImm();

720 NumBits = 8 + 2;

721

722 Scale = 1;

723 assert((Offset & 3) == 0 && "Can't encode this offset!");

725 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;

726 NumBits = 8;

727 Scale = 4;

728 assert((Offset & 3) == 0 && "Can't encode this offset!");

729 } else {

731 }

732

733 if (NewOpc != Opcode)

734 MI.setDesc(TII.get(NewOpc));

735

737

738

739

740

741

742 int ImmedOffset = Offset / Scale;

743 unsigned Mask = (1 << NumBits) - 1;

744 if ((unsigned)Offset <= Mask * Scale &&

747

749 if ( MRI ->constrainRegClass(FrameReg, RegClass))

750 llvm_unreachable("Unable to constrain virtual register class.");

751 }

752

753

754 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);

755 if (isSub) {

757

758 ImmedOffset |= 1 << NumBits;

759 else

760 ImmedOffset = -ImmedOffset;

761 }

764 return true;

765 }

766

767

768 ImmedOffset = ImmedOffset & Mask;

769 if (isSub) {

771

772 ImmedOffset |= 1 << NumBits;

773 else {

774 ImmedOffset = -ImmedOffset;

775 if (ImmedOffset == 0)

776

778 }

779 }

781 Offset &= ~(Mask*Scale);

782 }

783

786}

787

790 unsigned Opc = MI.getOpcode();

791 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)

794}

795

798

799 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)

801 return i;

802

803 return -1;

804}

805

809 if (PIdx == -1) {

810 PredReg = 0;

812 }

813

814 PredReg = MI.getOperand(PIdx+1).getReg();

816}

817

819 assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");

820

822 assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");

823

825 End = Instr.getParent()->end();

826

827 while (Iter != End && Iter->isDebugInstr())

828 ++Iter;

829

830

831

832 assert(Iter != End && "Expected some instructions in any VPT block");

835 "VPT/VPST should be followed by an instruction with a 'then' predicate!");

836 ++Iter;

837

838

840 while (Iter != End) {

841 if (Iter->isDebugInstr()) {

842 ++Iter;

843 continue;

844 }

847 break;

849 ++Iter;

850 }

851

852

853 MaskOp.setImm((int64_t)(BlockMask));

854}

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const HexagonInstrInfo * TII

Module.h This file contains the declarations for the Module class.

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

static unsigned negativeOffsetOpcode(unsigned opcode)

static unsigned positiveOffsetOpcode(unsigned opcode)

static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))

static cl::opt< bool > PreferNoCSEL("prefer-no-csel", cl::Hidden, cl::desc("Prefer predicated Move to CSEL"), cl::init(false))

static unsigned immediateOffsetOpcode(unsigned opcode)

const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

const ARMSubtarget & getSubtarget() const

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...

Module * getParent()

Get the module that this global value is contained inside of...

MCInstBuilder & addReg(MCRegister Reg)

Add a new register operand.

MCInstBuilder & addImm(int64_t Val)

Add a new integer immediate operand.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

Wrapper class representing physical registers. Should be passed by value.

void eraseFromParent()

This method unlinks 'this' from the containing function and deletes it.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & setMIFlags(unsigned Flags) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const

Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...

bool isPositionIndependent() const

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

unsigned getUnindexedOpcode(unsigned Opc) const override

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

Thumb2InstrInfo(const ARMSubtarget &STI)

MCInst getNop() const override

Return the noop instruction to use for a noop.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned char getAM5FP16Offset(unsigned AM5Opc)

int getT2SOImmVal(unsigned Arg)

getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...

AddrOpc getAM5Op(unsigned AM5Opc)

AddrOpc getAM5FP16Op(unsigned AM5Opc)

unsigned char getAM5Offset(unsigned AM5Opc)

PredBlockMask

Mask values for IT and VPT Blocks, to be used by MCOperands.

bool isVpred(OperandType op)

@ Tail

Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...

@ Kill

The last use of a register.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

int findFirstVPTPredOperandIdx(const MachineInstr &MI)

ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static bool isVPTOpcode(int Opc)

bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

int countl_zero(T Val)

Count number of 0's from the most significant bit to the least stopping at the first 1.

ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)

getITInstrPredicate - Valid only in Thumb2 mode.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getKillRegState(bool B)

ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)

ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)

getInstrPredicate - If instruction is predicated, returns its predicate condition,...

static MachineOperand condCodeOp(unsigned CCReg=0)

Get the operand corresponding to the conditional code result.

void recomputeVPTBlockMask(MachineInstr &Instr)

void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)

Description of the encoding of one expression Op.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.