LLVM: llvm::ARMBaseInstrInfo Class Reference (original) (raw)

#include "[Target/ARM/ARMBaseInstrInfo.h](ARMBaseInstrInfo%5F8h%5Fsource.html)"

Definition at line 42 of file ARMBaseInstrInfo.h.

◆ AddDReg()

◆ analyzeBranch()

Definition at line 182 of file ARMBaseInstrInfo.cpp.

References assert(), Cond, llvm::MachineOperand::CreateImm(), llvm::ARMSubtarget::enableMachinePipeliner(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getOpcode(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), isPredicated(), llvm::isSpeculationBarrierEndBBOpcode(), llvm::isUncondBranchOpcode(), MBB, removeBranch(), and TBB.

◆ analyzeCompare()

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 2634 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by shouldSink().

◆ analyzeLoopForPipelining()

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 6765 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineBasicBlock::instrs(), isCPSRDefined(), llvm::isVCTP(), MRI, and llvm::MachineBasicBlock::pred_begin().

◆ analyzeSelect()

◆ areLoadsFromSameBasePtr()

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1794 of file ARMBaseInstrInfo.cpp.

References llvm::cast(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::isa(), and llvm::SDNode::isMachineOpcode().

◆ breakPartialRegDependency()

Definition at line 5250 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), contains(), llvm::get(), llvm::MachineOperand::getReg(), MI, llvm::predOps(), and TRI.

◆ buildOutlinedFrame()

Definition at line 6373 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::ARMCC::AL, llvm::any_of(), assert(), llvm::BuildMI(), Call, llvm::get(), llvm::MachineFunction::getInfo(), isThumb(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, Opc, and llvm::predOps().

◆ canCauseFpMLxStall()

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 514 of file ARMBaseInstrInfo.h.

◆ ClobbersPredicate()

◆ commuteInstructionImpl()

◆ copyFromCPSR()

Definition at line 654 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::get(), llvm::getKillRegState(), I, llvm::RegState::Implicit, MBB, Opc, and llvm::predOps().

Referenced by copyPhysReg().

◆ copyPhysReg()

Definition at line 718 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::addUnpredicatedMveVpredROp(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, llvm::SmallSet< T, N, C >::insert(), MBB, Opc, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::copyPhysReg(), and insertOutlinedCall().

◆ copyToCPSR()

Definition at line 674 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::Define, llvm::get(), llvm::getKillRegState(), I, llvm::RegState::Implicit, MBB, Opc, and llvm::predOps().

Referenced by copyPhysReg().

◆ createMIROperandComment()

◆ CreateTargetHazardRecognizer()

◆ CreateTargetMIHazardRecognizer()

◆ CreateTargetPostRAHazardRecognizer()

◆ decomposeMachineOperandsTargetFlags()

◆ describeLoadedValue()

◆ duplicate()

◆ expandLoadStackGuardBase()

Definition at line 4758 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::cast(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::get(), llvm::MachinePointerInfo::getGOT(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::RegState::Kill, MBB, MI, llvm::ARMII::MO_COFFSTUB, llvm::ARMII::MO_DLLIMPORT, llvm::ARMII::MO_GOT, llvm::ARMII::MO_NO_FLAG, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::Offset, and llvm::predOps().

◆ expandPostRAPseudo()

Definition at line 1533 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, contains(), llvm::dbgs(), llvm::get(), getRegisterInfo(), llvm::RegState::Implicit, LLVM_DEBUG, MI, llvm::predOps(), and TRI.

◆ extraSizeToPredicateInstructions()

◆ foldImmediate()

foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.

Definition at line 3158 of file ARMBaseInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::condCodeOp(), DefMI, llvm::get(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), MRI, OpIdx, llvm::predOps(), and UseMI.

◆ getExecutionDomain()

◆ getExtractSubregLikeInputs()

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

``[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

• %1:sub1, sub0

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isExtractSubregLike().

Definition at line 5328 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

◆ getFramePred()

◆ getInsertSubregLikeInputs()

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

\[out\] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

• BaseReg: %0:sub0
• InsertedReg: %1:sub1, sub3

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isInsertSubregLike().

Definition at line 5351 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

◆ getInstSizeInBytes()

◆ getNumLDMAddresses()

◆ getNumMicroOps()

Definition at line 3609 of file ARMBaseInstrInfo.cpp.

References llvm::ARMSubtarget::DoubleIssue, llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess, llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSingleIssuePlusExtras(), getNumMicroOpsSwiftLdSt(), llvm::InstrItineraryData::isEmpty(), llvm_unreachable, MI, Opc, llvm::ARMSubtarget::SingleIssue, and llvm::ARMSubtarget::SingleIssuePlusExtras.

◆ getOperandLatency() [1/2]

Definition at line 4209 of file ARMBaseInstrInfo.cpp.

References DefMI, getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isRegSequence(), and UseMI.

Referenced by getOperandLatency().

◆ getOperandLatency() [2/2]

Definition at line 4303 of file ARMBaseInstrInfo.cpp.

References llvm::cast(), llvm::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), llvm::SDNode::isMachineOpcode(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::Opcode.

◆ getOutliningCandidateInfo()

Definition at line 5724 of file ARMBaseInstrInfo.cpp.

References llvm::any_of(), llvm::outliner::Candidate::back(), llvm::ARMFunctionInfo::branchTargetEnforcement(), llvm::CallingConv::C, OutlinerCosts::CallDefault, OutlinerCosts::CallNoLRSave, OutlinerCosts::CallRegSave, OutlinerCosts::CallTailCall, OutlinerCosts::CallThunk, llvm::drop_end(), llvm::erase_if(), OutlinerCosts::FrameDefault, OutlinerCosts::FrameNoLRSave, OutlinerCosts::FrameRegSave, OutlinerCosts::FrameTailCall, OutlinerCosts::FrameThunk, getInstSizeInBytes(), getRegisterInfo(), HasCalls, llvm::MachineInstr::isCall(), isLRAvailable(), llvm::Last, MachineOutlinerDefault, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MI, llvm::partition(), OutlinerCosts::SaveRestoreLROnStack, llvm::ARMFunctionInfo::shouldSignReturnAddress(), TRI, and UnsafeRegsDead.

◆ getOutliningTypeImpl()

Definition at line 6135 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainMVE, llvm::dyn_cast(), llvm::MachineFunction::getFrameInfo(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFrameInfo::getNumObjects(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), HasCalls, llvm::outliner::Illegal, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::outliner::Legal, llvm::outliner::LegalTerminator, LRUnavailableSomewhere, MI, Opc, and TRI.

◆ getPartialRegUpdateClearance()

◆ getPredicate()

◆ getRegisterInfo()

Definition at line 129 of file ARMBaseInstrInfo.h.

References llvm::TargetInstrInfo::getRegisterInfo().

Referenced by AddDReg(), copyPhysReg(), expandPostRAPseudo(), getOperandLatency(), getOutliningCandidateInfo(), getOutliningTypeImpl(), isMBBSafeToOutlineFrom(), isProfitableToIfCvt(), loadRegFromStackSlot(), optimizeCompareInstr(), predictBranchSizeForIfCvt(), setExecutionDomain(), and storeRegToStackSlot().

◆ getRegSequenceLikeInputs()

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

``[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:

• %1:sub1, sub0
• %2<:0>, sub1

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isRegSequenceLike().

Definition at line 5301 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getSerializableBitmaskMachineOperandTargetFlags()

◆ getSerializableDirectMachineOperandTargetFlags()

◆ getSubtarget()

◆ getUnindexedOpcode()

◆ hasNOP()

◆ insertBranch()

Definition at line 325 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::getImm(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, llvm::predOps(), and TBB.

◆ insertOutlinedCall()

Definition at line 6446 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::CFIInstBuilder::buildRegister(), llvm::CFIInstBuilder::buildRestore(), llvm::CallingConv::C, copyPhysReg(), llvm::dwarf_linker::DebugLoc, llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, llvm::get(), llvm::MachineFunction::getName(), llvm::ARMFunctionInfo::isLRSpilled(), isThumb(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, Opc, llvm::predOps(), and llvm::ARMFunctionInfo::shouldSignReturnAddress().

◆ isAddImmediate()

◆ isCopyInstrImpl()

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 887 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by describeLoadedValue().

◆ isCPSRDefined()

◆ isFpMLxInstruction() [1/2]

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 500 of file ARMBaseInstrInfo.h.

◆ isFpMLxInstruction() [2/2]

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.

Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 4851 of file ARMBaseInstrInfo.cpp.

References ARM_MLxTable, and I.

◆ isFunctionSafeToOutlineFrom()

◆ isLoadFromStackSlot()

◆ isLoadFromStackSlotPostFE()

◆ isMBBSafeToOutlineFrom()

Definition at line 6086 of file ARMBaseInstrInfo.cpp.

References llvm::LiveRegUnits::accumulate(), llvm::LiveRegUnits::addLiveOuts(), llvm::any_of(), assert(), llvm::LiveRegUnits::available(), getRegisterInfo(), HasCalls, isLRAvailable(), LRUnavailableSomewhere, MBB, MI, llvm::reverse(), and UnsafeRegsDead.

◆ isPredicable()

isPredicable - Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 551 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineFunction::getInfo(), getSubtarget(), llvm::MachineFunction::getSubtarget(), isEligibleForITBlock(), llvm::isIndirectCall(), llvm::isIndirectControlFlowNotComingBack(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), and MI.

◆ isPredicated()

◆ isProfitableToDupForIfCvt()

◆ isProfitableToIfCvt() [1/2]

◆ isProfitableToIfCvt() [2/2]

◆ isProfitableToUnpredicate()

◆ isSchedulingBoundary()

◆ isStoreToStackSlot()

◆ isStoreToStackSlotPostFE()

◆ isSwiftFastImmShift()

◆ isUnspillableTerminatorImpl()

◆ loadRegFromStackSlot()

Definition at line 1211 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::DefineNoRead, DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), getRegisterInfo(), I, llvm::RegState::ImplicitDefine, llvm::Register::isPhysical(), llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().

◆ mergeOutliningCandidateAttributes()

◆ optimizeCompareInstr()

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.

E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 2860 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, assert(), B(), llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), Cond, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, getCmpToAddCondition(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, llvm::ARMCC::MI, MI, MRI, llvm::ARMCC::NE, Opc, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TRI, llvm::ARMCC::VC, and llvm::ARMCC::VS.

◆ optimizeSelect()

Definition at line 2187 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineInstr::clearKillInfo(), llvm::condCodeOp(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::ARMCC::getOppositeCondition(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasOptionalDef(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, llvm::MCInstrDesc::operands(), llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().

Referenced by llvm::Thumb2InstrInfo::optimizeSelect().

◆ PredicateInstruction()

Definition at line 428 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::get(), llvm::getImm(), llvm::getMatchingCondBranchOpcode(), getReg(), llvm::isUncondBranchOpcode(), MI, Opc, llvm::MachineOperand::setImm(), and llvm::ARMII::ThumbArithFlagSetting.

◆ predictBranchSizeForIfCvt()

◆ produceSameValue()

Definition at line 1707 of file ARMBaseInstrInfo.cpp.

References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARMConstantPoolValue::hasSameValue(), llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineInstr::isIdenticalTo(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::Register::isVirtual(), llvm::MachineConstantPoolEntry::MachineCPVal, MRI, produceSameValue(), and llvm::MachineConstantPoolEntry::Val.

Referenced by produceSameValue().

◆ reMaterialize()

Definition at line 1656 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), duplicateCPV(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, MBB, MI, and TRI.

◆ removeBranch()

◆ reverseBranchCondition()

◆ setExecutionDomain()

Definition at line 4979 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::RegState::Define, ExeNEON, llvm::get(), getCorrespondingDRegAndLane(), getImplicitSPRUseForDPRUse(), getRegisterInfo(), llvm::getUndefRegState(), llvm::RegState::Implicit, isPredicated(), llvm_unreachable, MI, llvm::predOps(), TRI, and llvm::RegState::Undef.

◆ shouldOutlineFromFunctionByDefault()

◆ shouldScheduleLoadsNear()

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1861 of file ARMBaseInstrInfo.cpp.

References assert(), and llvm::SDNode::getMachineOpcode().

◆ shouldSink()

◆ storeRegToStackSlot()

Definition at line 944 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), getRegisterInfo(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().

◆ SubsumesPredicate()

Definition at line 462 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::getImm(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().

The documentation for this class was generated from the following files:

• lib/Target/ARM/ARMBaseInstrInfo.h
• lib/Target/ARM/ARMBaseInstrInfo.cpp