| dbo:abstract |
Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturing defects that could adversely affect the product's correct functioning. Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer's environment. The tests are generally driven by test programs that execute using automatic test equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure. In other words, the response of vectors (patterns) from a good circuit is compared with the response of vectors (using the same patterns) from a DUT (device under test). If the response is the same or matches, the circuit is good. Otherwise, the circuit is not manufactured as it was intended. DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented. (en) 可测试性设计（英語：Design for testing或英語：Design for Testability，DFT）是一种集成电路设计技术。它是一種将特殊结构在设计阶段植入电路的方法，以便生產完成后进行测试，確保檢測過後的電子元件沒有功能或製造上的缺陷。 电路测试有时并不容易，电路的许多内部节点信号在外部难以控制和观测。通过在半導體製程中添加可测试性设计结构，如扫描链等，並利用自動測試設備執行，可以在生產完成後立即進行品質檢測。有些特定的裝置會在其最終產品的組件上加上測試功能，在消費者的使用環境下執行時一併測試。測試程式除了會指出錯誤資訊外，還會一併將測試的紀錄檔保留下來，可供設計人員找出缺陷的來源。 更簡單的說，測試程式會對所有的被測裝置輸入測試訊號，並期待它們給出預期的正確回應。如果被測裝置的回應與預期回應一致，則可得知電路正常，否則即為測試錯誤。 為了方便使用測試程式檢測錯誤，電路設計階段不可忽視可測試性設計。在可測試性設計的規則確認完善下，可以利用自動測試圖樣產生器進行更複雜的測試。 (zh) |
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http://www.corelis.com/education/Tips_DFT_Considerations_Board_Level_Design.htm http://www.corelis.com/education/Tips_DFT_Considerations_Boundary_Scan_Chain.htm https://www.xjtag.com/about-jtag/design-for-test-guidelines/ http://focus.ti.com/lit/an/ssya002c/ssya002c.pdf http://www.eng.tau.ac.il/~bengal/SCI_paper.pdf |
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可测试性设计（英語：Design for testing或英語：Design for Testability，DFT）是一种集成电路设计技术。它是一種将特殊结构在设计阶段植入电路的方法，以便生產完成后进行测试，確保檢測過後的電子元件沒有功能或製造上的缺陷。 电路测试有时并不容易，电路的许多内部节点信号在外部难以控制和观测。通过在半導體製程中添加可测试性设计结构，如扫描链等，並利用自動測試設備執行，可以在生產完成後立即進行品質檢測。有些特定的裝置會在其最終產品的組件上加上測試功能，在消費者的使用環境下執行時一併測試。測試程式除了會指出錯誤資訊外，還會一併將測試的紀錄檔保留下來，可供設計人員找出缺陷的來源。 更簡單的說，測試程式會對所有的被測裝置輸入測試訊號，並期待它們給出預期的正確回應。如果被測裝置的回應與預期回應一致，則可得知電路正常，否則即為測試錯誤。 為了方便使用測試程式檢測錯誤，電路設計階段不可忽視可測試性設計。在可測試性設計的規則確認完善下，可以利用自動測試圖樣產生器進行更複雜的測試。 (zh) Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturing defects that could adversely affect the product's correct functioning. (en) |
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