Cesar Roda Neve - Academia.edu (original) (raw)

Papers by Cesar Roda Neve

Research paper thumbnail of Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

2007 IEEE International SOI Conference, 2007

Abstract The rising integration level of mixed-signal integrated circuits raises new issues for d... more Abstract The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate noise generated by the switching digital part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called" digital substrate noise" on a 0.13-mum SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.

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Research paper thumbnail of Microwave characterization of optically modulated photo-induced switches with a passivation layer using an LSNA

2008 72nd ARFTG Microwave Measurement Symposium, 2008

A measurement set-up has been developed to characterize the electrical response to a pulsed optic... more A measurement set-up has been developed to characterize the electrical response to a pulsed optical excitation on photo-induced switches. The hardware configuration is a combination of a 50 GHz LSNA and a laser modulated by a pulse generator. By making use of vector large-signal measurements, the pulse envelope response is measured which allows the study of transient effects as well

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Research paper thumbnail of ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package

2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015

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Research paper thumbnail of Contactless monitoring of Si substrate permittivity and resistivity from microwave to millimeter wave frequencies

Microwave and Optical Technology Letters, 2010

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Research paper thumbnail of Optical crosstalk reduction in optically controlled microwave circuits on HR-Si using a trap-rich passivation layer

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Research paper thumbnail of Digital Substrate Noise Reduction by Low-Power Circuit Operation and SOI Technology

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Research paper thumbnail of <title>Quasi-optical technique for sensing bond quality of silicon wafers</title>

Micro-Optics 2010, 2010

ABSTRACT In this paper, we investigate a novel fast and reliable method to check the bonding qual... more ABSTRACT In this paper, we investigate a novel fast and reliable method to check the bonding quality of silicon wafers. It is based on illuminating the wafers with a high frequency waves (110 - 170 GHz) using quasi-optical technique. The reflected energy is used to evaluate the bonding strength. The reported experimental study is compared with the Infrared images.

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Research paper thumbnail of RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

2012 IEEE International SOI Conference (SOI), 2012

ABSTRACT In this paper we aim at comparing the static and RF performances of passive and active f... more ABSTRACT In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.

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Research paper thumbnail of Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si

Solid-State Electronics, 2013

ABSTRACT In this work, two novel RF substrate technologies are compared, namely local porous Si R... more ABSTRACT In this work, two novel RF substrate technologies are compared, namely local porous Si RF substrate technology and high resistivity Si with a trap-rich layer on top (trap-rich HR-Si). Using standard Si processing, identical co-planar waveguide transmission lines and test inductors were fabricated on the above two substrates, as well as on quartz and on standard p-type Si. Broadband electrical characterization in the frequency range from 40 MHz to 40 GHz revealed that porous Si substrate provides much higher effective resistivity and lower dielectric constant than trap-rich HR-Si, actually comparable with quartz substrate values. Lower dielectric constant leads to drastic reduction of crosstalk and provides design options for higher characteristic impedance devices. Higher effective substrate resistivity leads to lower attenuation losses and reduced non-linearities, as well as better quality factor for both transmission lines and inductors. Porous Si, which is CMOS-compatible and cost-efficient, demonstrates state-of-the-art RF performances comparable with quartz substrate.

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Research paper thumbnail of Nonlinear Properties of Si Based Substrates for Wireless Systems and SoC Integration

ABSTRACT

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Research paper thumbnail of Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications

ECS Transactions, 2008

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) ... more This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed ...

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Research paper thumbnail of Optical crosstalk reduction using a HR-si substrate with trap-rich passivation layer

2007 European Microwave Conference, 2007

... Abstract — The efficiency of a coplanar waveguide photo-induced Radio Frequency switch on a H... more ... Abstract — The efficiency of a coplanar waveguide photo-induced Radio Frequency switch on a High Resistivity Silicon substrate is presented. ... 2a a cross section of thephoto-induced switch investigated in this paper is shown. ...

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Research paper thumbnail of RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications

2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2013

ABSTRACT We present for the first time the RF and linear performance of commercial 200 mm trap-ri... more ABSTRACT We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.

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Research paper thumbnail of Non-linear characteristics of passive elements on trap-rich high-resistivity Si substrates

2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in Rf Systems, 2014

ABSTRACT RF losses and non-linear behavior of RF passive elements such as coplanar transmission l... more ABSTRACT RF losses and non-linear behavior of RF passive elements such as coplanar transmission lines and inductors are analyzed. The investigated trap-rich HR-Si wafers with a fixed oxide layer of 150 nm-thick show true effective resistivity values higher than 4 kΩ-cm up to 5 GHz and harmonic distortion levels lower than -90 dBm for a 900 MHz input with signal level of +25 dBm. High quality factor of 60 is measured for a 2 nH inductor on a trap-rich HR-Si substrate at 2.73 GHz frequency of operation. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of passive elements for RF systems.

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Research paper thumbnail of Analysis of slow-wave propagation in coplanar transmission lines with inkjet printed multiwalled carbon nanotubes network

Microwave and Optical Technology Letters, 2014

ABSTRACT This paper investigates the propagation along coplanar waveguide (CPW) structures, where... more ABSTRACT This paper investigates the propagation along coplanar waveguide (CPW) structures, where multi-walled carbon nanotubes (MWCNTs) network layers are deposited using inkjet printing. Electrical parameters are extracted from measured S-parameters data over the frequency range from 10 MHz to 26.5 GHz. The results clearly demonstrate two distinct propagation modes. At lowfrequencies, a Slow Wave Factor (SWF) up to 7 is achieved. With increasing frequency, attenuation becomes significant, while the propagation constant tends to a linear TEM regime. An equivalent lumped element circuit for CPW structure with MWCNTs network is developed and describes well the measured behaviour up to 26.5 GHz. Thanks to the extracted equivalent circuit, the origin of the observed slow-wave phenomenon is confirmed: it is ascribed to a larger capacitance per unit length of the CPW line induced by the presence of the CNTs network that prevents/limits the expansion of fields into air.

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Research paper thumbnail of A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

Proceedings of the 5th Electronics System-integration Technology Conference (ESTC), 2014

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Research paper thumbnail of Effect of temperature on advanced Si-based substrates performance for RF passive integration

Microelectronic Engineering, 2014

ABSTRACT This paper analyses RF substrate losses and non-linearity on Si-based substrates. Throug... more ABSTRACT This paper analyses RF substrate losses and non-linearity on Si-based substrates. Through measurements it is shown that trap-rich high resistivity silicon and porous silicon substrates are virtually lossless up to 120 o�C. Although, RF losses and CPW attenuation increases with temperature on both Si-based solutions, they remain acceptable for high temperature RF applications. Porous locally grown silicon shows better linearity than a comparable trap-rich high-resistivity (HR) Si substrate up to 175 �oC. Both Si-based solutions are considered as promising substrates for RF integration and system-on-chip applications.

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Research paper thumbnail of RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

IEEE Transactions on Electron Devices, 2000

ABSTRACT RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon... more ABSTRACT RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.

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Research paper thumbnail of Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

2007 IEEE International SOI Conference, 2007

Abstract The rising integration level of mixed-signal integrated circuits raises new issues for d... more Abstract The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate noise generated by the switching digital part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called&amp;amp;amp;amp;amp;quot; digital substrate noise&amp;amp;amp;amp;amp;quot; on a 0.13-mum SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Microwave characterization of optically modulated photo-induced switches with a passivation layer using an LSNA

2008 72nd ARFTG Microwave Measurement Symposium, 2008

A measurement set-up has been developed to characterize the electrical response to a pulsed optic... more A measurement set-up has been developed to characterize the electrical response to a pulsed optical excitation on photo-induced switches. The hardware configuration is a combination of a 50 GHz LSNA and a laser modulated by a pulse generator. By making use of vector large-signal measurements, the pulse envelope response is measured which allows the study of transient effects as well

Bookmarks Related papers MentionsView impact

Research paper thumbnail of ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package

2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Contactless monitoring of Si substrate permittivity and resistivity from microwave to millimeter wave frequencies

Microwave and Optical Technology Letters, 2010

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Optical crosstalk reduction in optically controlled microwave circuits on HR-Si using a trap-rich passivation layer

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Digital Substrate Noise Reduction by Low-Power Circuit Operation and SOI Technology

Bookmarks Related papers MentionsView impact

Research paper thumbnail of <title>Quasi-optical technique for sensing bond quality of silicon wafers</title>

Micro-Optics 2010, 2010

ABSTRACT In this paper, we investigate a novel fast and reliable method to check the bonding qual... more ABSTRACT In this paper, we investigate a novel fast and reliable method to check the bonding quality of silicon wafers. It is based on illuminating the wafers with a high frequency waves (110 - 170 GHz) using quasi-optical technique. The reflected energy is used to evaluate the bonding strength. The reported experimental study is compared with the Infrared images.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

2012 IEEE International SOI Conference (SOI), 2012

ABSTRACT In this paper we aim at comparing the static and RF performances of passive and active f... more ABSTRACT In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si

Solid-State Electronics, 2013

ABSTRACT In this work, two novel RF substrate technologies are compared, namely local porous Si R... more ABSTRACT In this work, two novel RF substrate technologies are compared, namely local porous Si RF substrate technology and high resistivity Si with a trap-rich layer on top (trap-rich HR-Si). Using standard Si processing, identical co-planar waveguide transmission lines and test inductors were fabricated on the above two substrates, as well as on quartz and on standard p-type Si. Broadband electrical characterization in the frequency range from 40 MHz to 40 GHz revealed that porous Si substrate provides much higher effective resistivity and lower dielectric constant than trap-rich HR-Si, actually comparable with quartz substrate values. Lower dielectric constant leads to drastic reduction of crosstalk and provides design options for higher characteristic impedance devices. Higher effective substrate resistivity leads to lower attenuation losses and reduced non-linearities, as well as better quality factor for both transmission lines and inductors. Porous Si, which is CMOS-compatible and cost-efficient, demonstrates state-of-the-art RF performances comparable with quartz substrate.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Nonlinear Properties of Si Based Substrates for Wireless Systems and SoC Integration

ABSTRACT

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications

ECS Transactions, 2008

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) ... more This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed ...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Optical crosstalk reduction using a HR-si substrate with trap-rich passivation layer

2007 European Microwave Conference, 2007

... Abstract — The efficiency of a coplanar waveguide photo-induced Radio Frequency switch on a H... more ... Abstract — The efficiency of a coplanar waveguide photo-induced Radio Frequency switch on a High Resistivity Silicon substrate is presented. ... 2a a cross section of thephoto-induced switch investigated in this paper is shown. ...

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Research paper thumbnail of RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications

2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2013

ABSTRACT We present for the first time the RF and linear performance of commercial 200 mm trap-ri... more ABSTRACT We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Non-linear characteristics of passive elements on trap-rich high-resistivity Si substrates

2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in Rf Systems, 2014

ABSTRACT RF losses and non-linear behavior of RF passive elements such as coplanar transmission l... more ABSTRACT RF losses and non-linear behavior of RF passive elements such as coplanar transmission lines and inductors are analyzed. The investigated trap-rich HR-Si wafers with a fixed oxide layer of 150 nm-thick show true effective resistivity values higher than 4 kΩ-cm up to 5 GHz and harmonic distortion levels lower than -90 dBm for a 900 MHz input with signal level of +25 dBm. High quality factor of 60 is measured for a 2 nH inductor on a trap-rich HR-Si substrate at 2.73 GHz frequency of operation. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of passive elements for RF systems.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analysis of slow-wave propagation in coplanar transmission lines with inkjet printed multiwalled carbon nanotubes network

Microwave and Optical Technology Letters, 2014

ABSTRACT This paper investigates the propagation along coplanar waveguide (CPW) structures, where... more ABSTRACT This paper investigates the propagation along coplanar waveguide (CPW) structures, where multi-walled carbon nanotubes (MWCNTs) network layers are deposited using inkjet printing. Electrical parameters are extracted from measured S-parameters data over the frequency range from 10 MHz to 26.5 GHz. The results clearly demonstrate two distinct propagation modes. At lowfrequencies, a Slow Wave Factor (SWF) up to 7 is achieved. With increasing frequency, attenuation becomes significant, while the propagation constant tends to a linear TEM regime. An equivalent lumped element circuit for CPW structure with MWCNTs network is developed and describes well the measured behaviour up to 26.5 GHz. Thanks to the extracted equivalent circuit, the origin of the observed slow-wave phenomenon is confirmed: it is ascribed to a larger capacitance per unit length of the CPW line induced by the presence of the CNTs network that prevents/limits the expansion of fields into air.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

Proceedings of the 5th Electronics System-integration Technology Conference (ESTC), 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Effect of temperature on advanced Si-based substrates performance for RF passive integration

Microelectronic Engineering, 2014

ABSTRACT This paper analyses RF substrate losses and non-linearity on Si-based substrates. Throug... more ABSTRACT This paper analyses RF substrate losses and non-linearity on Si-based substrates. Through measurements it is shown that trap-rich high resistivity silicon and porous silicon substrates are virtually lossless up to 120 o�C. Although, RF losses and CPW attenuation increases with temperature on both Si-based solutions, they remain acceptable for high temperature RF applications. Porous locally grown silicon shows better linearity than a comparable trap-rich high-resistivity (HR) Si substrate up to 175 �oC. Both Si-based solutions are considered as promising substrates for RF integration and system-on-chip applications.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

IEEE Transactions on Electron Devices, 2000

ABSTRACT RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon... more ABSTRACT RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

IEEE Transactions on Electron Devices, 2000

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Research paper thumbnail of RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

IEEE Transactions on Electron Devices, 2000

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