A full-custom ASIC design of a 8-bit, 25 MHz, Pipeline ADC using 0.35 um CMOS technology (original) (raw)

A 12-bit high performance low cost pipeline ADC

Aladin Zayegh

2003

View PDFchevron_right

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

sha Kelly

IEEE Journal of Solid-state Circuits, 2009

View PDFchevron_right

Pipelined ADC Design and Enhancement Techniques

Si Ahmed

2010

View PDFchevron_right

Design Implementation of High-Performance Pipelined ADC

International Journal of Scientific Research in Science, Engineering and Technology IJSRSET

International Journal of Scientific Research in Science, Engineering and Technology, 2019

View PDFchevron_right

Implementation of Pipelined ADC Using Open- Loop Residue Amplification

kamalakannan venkataraman

View PDFchevron_right

Design and Implementation of 1-bit Pipeline ADC in 0.18um CMOS Technology .

Ijesrt Journal

International Journal of Engineering Sciences & Research Technology, 2014

View PDFchevron_right

Design of the basic building block of a high-speed flexible and modular pipelined ADC

Arthur van Roermund

View PDFchevron_right

A high speed power efficient pipeline ADC in 0.18μm CMOS

Jafar Sobhi, Ali Dadashi

2013 IEEE Faible Tension Faible Consommation, 2013

View PDFchevron_right

IMPLEMENTATION OF 16-BIT PIPELINED ADC USING 180nm CMOS TECHNOLOGY

IRJET Journal

View PDFchevron_right

A Power Scalable and Low Power Pipelined ADC

Imran Ahmed

Pipelined ADC Design and Enhancement Techniques, 2010

View PDFchevron_right

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

Prasad Rao

International Journal of VLSI Design & Communication Systems, 2011

View PDFchevron_right

DESIGN OF HIGH SPEED,6-BIT PIPELINE ADC WITH BUILT-IN DIGITAL ERROR CORRECTION UNIT USING SUBMICRON CMOS TECHNOLOGY

IJAR Indexing

View PDFchevron_right

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6\ mu m CMOS Process

Michel Paindavoine

2008

View PDFchevron_right

A 13-b Linear, 40MS/s Pipelined ADC With Self-Configured Capacitor Matching

Sourja Ray

IEEE Journal of Solid-state Circuits, 2006

View PDFchevron_right

A Low-Power 9-bit Pipelined CMOS ADC with Amplifier and Comparator Sharing Technique

Yuri Bocharov, Vladimir Butuzov

View PDFchevron_right

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6µm CMOS Process

Michel Paindavoine

arXiv (Cornell University), 2008

View PDFchevron_right

Low Power, 3-bit CMOS Pipeline ADC with Reduced Complexity Flash Architecture

Jugdutt Singh

View PDFchevron_right

A 14-b linear capacitor self-trimming pipelined ADC

Sourja Ray

IEEE Journal of Solid-state Circuits, 2004

View PDFchevron_right

A 1. 5-V, 10-bit, 200-MS/s CMOS Pipeline Analog-to-Digital Converter

Manju Devi

International Journal of Computer Applications, 2014

View PDFchevron_right

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

Norhamizah Idros

Microelectronics International, 2020

View PDFchevron_right

A 1.8V 36-mW 11-bit 80MS/s Pipelined ADC Using Capacitor and Opamp Sharing

Hansen Shi

View PDFchevron_right

Design considerations for high resolution pipeline ADCs in digital CMOS technology

Jorge M Guilherme

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001

View PDFchevron_right

A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques

Sahel Abdinia

View PDFchevron_right

IJERT-Design of high speed pipelined ADC System

IJERT Journal

International Journal of Engineering Research and Technology (IJERT), 2014

View PDFchevron_right

A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC

sunghyun Park

2007

View PDFchevron_right