Clock jitter generator with picoseconds resolution (original) (raw)

Clock jitter estimation based on PM noise measurements

David Howe

IEEE International Frequency Control Sympposium and PDA Exhibition Jointly with the 17th European Frequency and Time Forum, 2003. Proceedings of the 2003

View PDFchevron_right

Low-Cost On-Chip Clock Jitter Measurement Scheme

Cecilia Metra

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015

View PDFchevron_right

An embedded wide-range and high-resolution CLOCK jitter measurement circuit

Ching-Yuan YANG

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

View PDFchevron_right

Modeling timing jitter effects in digital-to-analog converters

Mauro D'Arco

2009

View PDFchevron_right

Clock Jitter Effects on Sampling: A Tutorial

john cheng

View PDFchevron_right

Noise Induced Jitter Performance of Digitally Controlled CMOS Delay Lines

Rui Aguiar

View PDFchevron_right

Approximation Approach for Timing Jitter Characterization in Circuit Simulators

Mark M Gourary, kiran kumar gullapalli

2003

View PDFchevron_right

Jitter analysis of PLL-generated clock propagation using Jitter Mitigation techniques with laser voltage probing

Tung Ton

Microelectronics Reliability, 2009

View PDFchevron_right

Minimization of Jitter in Digital Systems using Dual Phase-locked Loops

Ahmad Abdut-Tawab

2013

View PDFchevron_right

Jitter: Basics, relevance and measurement methods

David Pommerenke

2008 IEEE International Symposium on Electromagnetic Compatibility, 2008

View PDFchevron_right

Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems

Wendem Beyene

2007 IEEE Electrical Performance of Electronic Packaging, 2007

View PDFchevron_right

Jitter analysis for two methods of synchronization for external timing injection

Antonio Cantoni

IEEE Transactions on Communications, 1996

View PDFchevron_right

A low power, low jitter DLL based low frequency (250 kHz) clock generator

Prasun Ghosal

International Journal of Signal and Imaging Systems Engineering, 2014

View PDFchevron_right

Analysis of DLL jitter due to substrate noise

Payam Heydari

2002

View PDFchevron_right

Experimental Evaluation of the Jitter Generated in Timing Transfer

Antonio Cantoni

IEEE Transactions on Communications, 2000

View PDFchevron_right

Low Jitter Circuits in Digital System using Phase Locked Loop

Ahmed Telba

View PDFchevron_right

Characterisation and modelling of the ADC jitter

Pasquale Arpaia

View PDFchevron_right

Jitter transfer characteristics of delay-locked loops - theories and design techniques

Trey Greer

IEEE Journal of Solid-State Circuits, 2003

View PDFchevron_right

A Jitter Attenuating Timing Chain

Jihong Ren

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007

View PDFchevron_right

Modeling the Effect of Nonideal Reference Clocks on the Jitter Generated in Timing Transfer

Antonio Cantoni

IEEE Transactions on Communications, 2000

View PDFchevron_right

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Yo UESUGI

Solid-State Circuits, …, 1996

View PDFchevron_right

A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture

Yo UESUGI

VLSI Circuits, 1995. …, 1995

View PDFchevron_right

Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs

Cecilia Metra

IEEE Transactions on Instrumentation and Measurement, 2005

View PDFchevron_right

Direct digital frequency synthesis of low-jitter clocks

Dorin Calbaza

2000

View PDFchevron_right

Power Integrity Analysis For Jitter Characterization

Linson Thomas

2016

View PDFchevron_right

Accurate and low jitter time-interval generators based on phase shifting method

Zbigniew Jachna

Review of Scientific Instruments, 2012

View PDFchevron_right

A wide range delay locked loop for low power and low jitter applications

Mohammad Javad Ghahramanpour

International Journal of Circuit Theory and Applications, 2017

View PDFchevron_right

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

Ian Flintoft, andy marvin

IEEE Transactions on Electromagnetic Compatibility, 2003

View PDFchevron_right

AN10007 Jitter and measurement

JM KIM

View PDFchevron_right

Measuring the timing jitter of ATE in the frequency domain

solomon kane

IEEE Transactions on Instrumentation and Measurement, 2006

View PDFchevron_right

Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC sample clock synthesis

John McNeill

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013

View PDFchevron_right

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR

Hirotaka Tamura

IEEE Journal of Solid-State Circuits, 2018

View PDFchevron_right

Jitter injection for on-chip jitter measurement in PI-based CDRs

Ali Sheikholeslami

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017

View PDFchevron_right