A 20 Gb/s Injection-Locked Clock and Data Recovery Circuit (original) (raw)
Related papers
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
IEEE Journal of Solid-State Circuits, 2004
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
IEEE Journal of Solid-state Circuits, 2006
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit
IEEE Transactions on Circuits and Systems I-regular Papers, 2006
A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications
A pattern-dependent injection-locked CDR for clock-embedded signaling
Microelectronics Journal, 2020
A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit
IEEE Transactions on Circuits and Systems I-regular Papers, 2006
A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit
Analog Integrated Circuits and Signal Processing, 2007
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique
Circuits and Systems, …, 2006
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
IEEE Journal of Solid-state Circuits, 2004
A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects
IEEE Journal of Solid-State Circuits, 2000
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
A 1.08-Gb/s burst-mode clock and data recovery circuit using the jitter reduction technique
2009 IEEE International Symposium on Circuits and Systems, 2009
A 5Gbit/s CMOS clock and data recovery circuit
2006
IEEE Transactions on Circuits and Systems I-regular Papers, 2015
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface
IEEE Journal of Solid-State Circuits, 2014
A 2.75 Gb/s CMOS clock recovery circuit with broad capture range
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
An 8–11 Gb/s Reference-Less Bang-Bang CDR Enabled by “Phase Reset”
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
IEEE Journal of Solid-State Circuits, 2006
International Journal of Engineering Research and Technology (IJERT), 2018
A 1.6Gbps Digital Clock and Data Recovery Circuit
2006
A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit
IEEE Journal of Solid-State Circuits, 2018
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
IEEE Journal of Solid-State Circuits, 2002
A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs
Journal of Lightwave Technology, 2018
2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR
Radio Frequency Integrated Circuits IEEE Symposium, 2010
A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology
2012 International SoC Design Conference (ISOCC), 2012
IEEE Transactions on Circuits and Systems II: Express Briefs, 2009
1.25/2.5-Gb/s Burst-Mode Clock Recovery Circuit with a Novel Dual Bit-Rate Structure in 0.18-μm CMOS
2006 IEEE International Symposium on Circuits and Systems
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data
Solid-State Circuits, IEEE Journal of, 2001
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops
2008
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS
2011 IEEE International Solid-State Circuits Conference, 2011
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
IEEE Journal of Solid-State Circuits, 2018
A 2.5-Gb/s Clock and Data Recovery Circuit with a 1/4 -Rate Linear Phase Detector
2005 International Conference on Microelectronics, 2005
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator
IEEE Journal of Solid-State Circuits, 2003
Design of a phase locked loop based clocking circuit for high speed serial link applications
2014
Ultralow timing jitter 40Gb/s clock recovery using a self-starting optoelectronic oscillator
IEEE Photonics Technology Letters, 2004