ARMBaseInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H

14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H

29#include "llvm/IR/IntrinsicsARM.h"

31#include

32#include

34#define GET_INSTRINFO_HEADER

35#include "ARMGenInstrInfo.inc"

37namespace llvm {

39class ARMBaseRegisterInfo;

40class ARMSubtarget;

45protected:

51 unsigned LoadImmOpc, unsigned LoadOpc) const;

95 bool

100

101

102

103

104

105

106

108 unsigned OpIdx1,

109 unsigned OpIdx2) const override;

110

111

112

113 std::optional

115

116

117

118 std::optional

120

121public:

122

124

125

126

128

133

135

139

143

147

148

152 bool AllowModify = false) const override;

154 int *BytesRemoved = nullptr) const override;

158 int *BytesAdded = nullptr) const override;

159

160 bool

162

163

165

166

167 std::string

171

173 int PIdx = MI.findFirstPredOperandIdx();

176 }

177

180

183

185 bool SkipDead) const override;

186

188

189

191

192

193

195

197 int &FrameIndex) const override;

199 int &FrameIndex) const override;

201 int &FrameIndex) const override;

203 int &FrameIndex) const override;

204

211

214 bool KillSrc, bool RenamableDest = false,

215 bool RenamableSrc = false) const override;

216

221

227

229

231

233 Register DestReg, unsigned SubIdx,

235

239

241 unsigned SubIdx, unsigned State) const;

242

245

246

247

248

249

250

252 int64_t &Offset2) const override;

253

254

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259

260

261

263 int64_t Offset1, int64_t Offset2,

264 unsigned NumLoads) const override;

265

269

271 unsigned NumCycles, unsigned ExtraPredCycles,

273

276 unsigned NumF, unsigned ExtraF,

278

281 return NumCycles == 1;

282 }

283

285 unsigned NumInsts) const override;

287

290

291

292

293

294

296 Register &SrcReg2, int64_t &CmpMask,

297 int64_t &CmpValue) const override;

298

299

300

301

302

304 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,

306

309 unsigned &FalseOp, bool &Optimizable) const override;

310

313 bool) const override;

314

315

316

319

322

325 unsigned DefIdx,

327 unsigned UseIdx) const override;

329 SDNode *DefNode, unsigned DefIdx,

331 unsigned UseIdx) const override;

332

333

334 std::pair<uint16_t, uint16_t>

337

338 unsigned

343

344

346

347 std::pair<unsigned, unsigned>

353

354

356 bool OutlineFromLinkOnceODRs) const override;

357 std::optional<std::unique_ptroutliner::OutlinedFunction>

360 std::vectoroutliner::Candidate &RepeatedSequenceLocs,

361 unsigned MinRepeats) const override;

363 Function &F, std::vectoroutliner::Candidate &Candidates) const override;

366 unsigned Flags) const override;

368 unsigned &Flags) const override;

375

376

378

380 return MI->getOpcode() == ARM::t2LoopEndDec ||

381 MI->getOpcode() == ARM::t2DoLoopStartTP ||

382 MI->getOpcode() == ARM::t2WhileLoopStartLR ||

383 MI->getOpcode() == ARM::t2WhileLoopStartTP;

384 }

385

386

387

388 std::unique_ptrTargetInstrInfo::PipelinerLoopInfo

390

391private:

392

393

395

396

397

398

399

401 bool CFI, bool Auth) const;

402

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406

409 bool Auth) const;

410

411

412

413

414

416

417

418

420 bool Updt) const;

421

422 unsigned getInstBundleLength(const MachineInstr &MI) const;

423

424 std::optional getVLDMDefCycle(const InstrItineraryData *ItinData,

426 unsigned DefClass, unsigned DefIdx,

427 unsigned DefAlign) const;

428 std::optional getLDMDefCycle(const InstrItineraryData *ItinData,

430 unsigned DefClass, unsigned DefIdx,

431 unsigned DefAlign) const;

432 std::optional getVSTMUseCycle(const InstrItineraryData *ItinData,

434 unsigned UseClass, unsigned UseIdx,

435 unsigned UseAlign) const;

436 std::optional getSTMUseCycle(const InstrItineraryData *ItinData,

438 unsigned UseClass, unsigned UseIdx,

439 unsigned UseAlign) const;

442 unsigned DefIdx, unsigned DefAlign,

444 unsigned UseIdx,

445 unsigned UseAlign) const;

446

447 std::optional getOperandLatencyImpl(

449 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,

451 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;

452

453 unsigned getPredicationCost(const MachineInstr &MI) const override;

454

457 unsigned *PredCost = nullptr) const override;

458

461

462 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,

466 unsigned UseIdx) const override;

469 unsigned DefIdx) const override;

470

471

473 StringRef &ErrInfo) const override;

474

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480

483

484 bool isReMaterializableImpl(const MachineInstr &MI) const override;

485

486private:

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494

496

497public:

498

499

501 return MLxEntryMap.count(Opcode);

502 }

503

504

505

506

508 unsigned &AddSubOpc, bool &NegAcc,

509 bool &HasLane) const;

510

511

512

513

515 return MLxHazardOpcodes.count(Opcode);

516 }

517

518

519

521

522

525

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527

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529

530

531

532 return MI.getOperand(3).getReg();

533 }

534

537};

538

539

540

541

543 unsigned PredReg = 0) {

546}

547

548

549

553

554

555

556

559 true, false,

560 false, isDead);

561}

562

563static inline

565 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;

566}

567

568

569

570

572 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||

573 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||

574 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||

575 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||

576 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||

577 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||

578 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||

579 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||

580 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||

581 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||

582 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||

583 Opc == ARM::MVE_VPST;

584}

585

586static inline

588 switch (Opcode) {

589 default:

590 return 0;

591 case ARM::MVE_VCMPf32:

592 return ARM::MVE_VPTv4f32;

593 case ARM::MVE_VCMPf16:

594 return ARM::MVE_VPTv8f16;

595 case ARM::MVE_VCMPi8:

596 return ARM::MVE_VPTv16i8;

597 case ARM::MVE_VCMPi16:

598 return ARM::MVE_VPTv8i16;

599 case ARM::MVE_VCMPi32:

600 return ARM::MVE_VPTv4i32;

601 case ARM::MVE_VCMPu8:

602 return ARM::MVE_VPTv16u8;

603 case ARM::MVE_VCMPu16:

604 return ARM::MVE_VPTv8u16;

605 case ARM::MVE_VCMPu32:

606 return ARM::MVE_VPTv4u32;

607 case ARM::MVE_VCMPs8:

608 return ARM::MVE_VPTv16s8;

609 case ARM::MVE_VCMPs16:

610 return ARM::MVE_VPTv8s16;

611 case ARM::MVE_VCMPs32:

612 return ARM::MVE_VPTv4s32;

613

614 case ARM::MVE_VCMPf32r:

615 return ARM::MVE_VPTv4f32r;

616 case ARM::MVE_VCMPf16r:

617 return ARM::MVE_VPTv8f16r;

618 case ARM::MVE_VCMPi8r:

619 return ARM::MVE_VPTv16i8r;

620 case ARM::MVE_VCMPi16r:

621 return ARM::MVE_VPTv8i16r;

622 case ARM::MVE_VCMPi32r:

623 return ARM::MVE_VPTv4i32r;

624 case ARM::MVE_VCMPu8r:

625 return ARM::MVE_VPTv16u8r;

626 case ARM::MVE_VCMPu16r:

627 return ARM::MVE_VPTv8u16r;

628 case ARM::MVE_VCMPu32r:

629 return ARM::MVE_VPTv4u32r;

630 case ARM::MVE_VCMPs8r:

631 return ARM::MVE_VPTv16s8r;

632 case ARM::MVE_VCMPs16r:

633 return ARM::MVE_VPTv8s16r;

634 case ARM::MVE_VCMPs32r:

635 return ARM::MVE_VPTv4s32r;

636 }

637}

638

639static inline

641 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;

642}

643

645 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||

646 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||

647 Opc == ARM::t2BR_JT;

648}

649

650static inline

652 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;

653}

654

656 int Opc = MI.getOpcode();

657 switch (Opc) {

658

659 case ARM::BLX:

660 case ARM::BLX_noip:

661 case ARM::BLX_pred:

662 case ARM::BLX_pred_noip:

663 case ARM::BX_CALL:

664 case ARM::BMOVPCRX_CALL:

665 case ARM::TCRETURNri:

666 case ARM::TCRETURNrinotr12:

667 case ARM::TAILJMPr:

668 case ARM::TAILJMPr4:

669 case ARM::tBLXr:

670 case ARM::tBLXr_noip:

671 case ARM::tBLXNSr:

672 case ARM::tBLXNS_CALL:

673 case ARM::tBX_CALL:

674 case ARM::tTAILJMPr:

676 return true;

677

678 case ARM::BL:

679 case ARM::BL_pred:

680 case ARM::BMOVPCB_CALL:

681 case ARM::BL_PUSHLR:

682 case ARM::BLXi:

683 case ARM::TCRETURNdi:

684 case ARM::TAILJMPd:

685 case ARM::SVC:

686 case ARM::HVC:

687 case ARM::TPsoft:

688 case ARM::tTAILJMPd:

689 case ARM::t2SMC:

690 case ARM::t2HVC:

691 case ARM::tBL:

692 case ARM::tBLXi:

693 case ARM::tBL_PUSHLR:

694 case ARM::tTAILJMPdND:

695 case ARM::tSVC:

696 case ARM::tTPsoft:

698 return false;

699 }

701 return false;

702}

703

705 int opc = MI.getOpcode();

708}

709

711 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||

712 Opc == ARM::SpeculationBarrierSBEndBB ||

713 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||

714 Opc == ARM::t2SpeculationBarrierSBEndBB;

715}

716

718 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||

719 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||

720 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;

721}

722

724 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||

725 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;

726}

727

729 return Opc == ARM::SUBri ||

730 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||

731 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||

732 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;

733}

734

736 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;

737}

738

739

740

743

744

745

746

747

748

749 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)

750 return false;

751

752

753

754 if (featureBits[ARM::HasV8_1MMainlineOps] &&

755 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))

756 return false;

757

758 return true;

759}

760

762 unsigned Opc = MI.getOpcode();

763 switch (Opc) {

764 case ARM::SEH_StackAlloc:

765 case ARM::SEH_SaveRegs:

766 case ARM::SEH_SaveRegs_Ret:

767 case ARM::SEH_SaveSP:

768 case ARM::SEH_SaveFRegs:

769 case ARM::SEH_SaveLR:

770 case ARM::SEH_Nop:

771 case ARM::SEH_Nop_Ret:

772 case ARM::SEH_PrologEnd:

773 case ARM::SEH_EpilogStart:

774 case ARM::SEH_EpilogEnd:

775 return true;

776 default:

777 return false;

778 }

779}

780

781

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788

789

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794

795

799 Register BaseReg, int NumBytes,

801 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);

802

806 Register BaseReg, int NumBytes,

808 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);

812 Register BaseReg, int NumBytes,

813 const TargetInstrInfo &TII,

814 const ARMBaseRegisterInfo &MRI,

815 unsigned MIFlags = 0);

816

817

818

819

820

821

823 MachineFunction &MF, MachineInstr *MI,

824 unsigned NumBytes);

825

826

827

828

829

832 const ARMBaseInstrInfo &TII);

833

836 const ARMBaseInstrInfo &TII,

837 const TargetRegisterInfo *TRI);

838

839

842 const TargetRegisterInfo *TRI);

843

844

845

847 const TargetRegisterInfo *TRI);

848

851

854 unsigned Inactive);

855

856

857

858

860 const ARMSubtarget *Subtarget,

861 bool ForCodesize = false);

862

863

864

865

867 const ARMSubtarget *Subtarget,

868 bool ForCodesize = false);

869

870

871

873 int Scale = 1;

874 unsigned ImmOp;

875 switch (MI.getOpcode()) {

876 case ARM::t2ADDri:

877 ImmOp = 2;

878 break;

879 case ARM::t2SUBri:

880 case ARM::t2SUBri12:

881 ImmOp = 2;

882 Scale = -1;

883 break;

884 case ARM::tSUBi3:

885 case ARM::tSUBi8:

886 ImmOp = 3;

887 Scale = -1;

888 break;

889 default:

890 return 0;

891 }

892 return Scale * MI.getOperand(ImmOp).getImm();

893}

894

895

896

903 return std::abs(Imm) < ((1 << 7) * 1);

905 return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;

907 return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;

909 return std::abs(Imm) < ((1 << 8) * 1);

911 return Imm >= 0 && Imm < ((1 << 8) * 1);

913 return Imm < 0 && -Imm < ((1 << 8) * 1);

915 return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;

917 return Imm >= 0 && Imm < ((1 << 12) * 1);

919 return std::abs(Imm) < ((1 << 12) * 1);

920 default:

922 }

923}

924

925

927 if (IntInst == nullptr)

928 return false;

930 return (IntrinsicID == Intrinsic::masked_gather ||

931 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||

932 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||

933 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||

934 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||

935 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||

936 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);

937}

938

939

941 if (IntInst == nullptr)

942 return false;

944 return (IntrinsicID == Intrinsic::masked_scatter ||

945 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||

946 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||

947 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||

948 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||

949 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||

950 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);

951}

952

953

955 if (IntInst == nullptr)

956 return false;

958}

959

960unsigned getBLXOpcode(const MachineFunction &MF);

963

965

966

967 switch (MI->getOpcode()) {

968 case ARM::MVE_SQSHL:

969 case ARM::MVE_SRSHR:

970 case ARM::MVE_UQSHL:

971 case ARM::MVE_URSHR:

972 case ARM::MVE_SQRSHR:

973 case ARM::MVE_UQRSHL:

974 case ARM::MVE_ASRLr:

975 case ARM::MVE_ASRLi:

976 case ARM::MVE_LSLLr:

977 case ARM::MVE_LSLLi:

978 case ARM::MVE_LSRL:

979 case ARM::MVE_SQRSHRL:

980 case ARM::MVE_SQSHLL:

981 case ARM::MVE_SRSHRL:

982 case ARM::MVE_UQRSHLL:

983 case ARM::MVE_UQSHLL:

984 case ARM::MVE_URSHRL:

985 return false;

986 }

990}

991

992}

993

994#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

This file defines the DenseMap class.

TargetInstrInfo::RegSubRegPair RegSubRegPair

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

PowerPC TLS Dynamic Call Fixup

TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

This file defines the SmallSet class.

static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)

bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override

Definition ARMBaseInstrInfo.h:379

static bool isCPSRDefined(const MachineInstr &MI)

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...

bool canCauseFpMLxStall(unsigned Opcode) const

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...

Definition ARMBaseInstrInfo.h:514

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const

unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override

virtual unsigned getUnindexedOpcode(unsigned Opc) const =0

std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override

unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override

unsigned getNumLDMAddresses(const MachineInstr &MI) const

Get the number of addresses by LDM or VLDM or zero for unknown.

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

Definition ARMBaseInstrInfo.h:279

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State) const

bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override

void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override

ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Returns the size of the specified MachineInstr.

void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MCRegister SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override

ARMCC::CondCodes getPredicate(const MachineInstr &MI) const

Definition ARMBaseInstrInfo.h:172

bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override

ARM supports the MachineOutliner.

bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override

Enable outlining by default at -Oz.

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

If the specific machine instruction is an instruction that moves/copies value from one register to an...

MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override

ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override

MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override

std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override

bool isPredicated(const MachineInstr &MI) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const

bool isPredicable(const MachineInstr &MI) const override

isPredicable - Return true if the specified instruction can be predicated.

unsigned getFramePred(const MachineInstr &MI) const

Returns predicate register associated with the given frame instruction.

Definition ARMBaseInstrInfo.h:523

std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override

Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...

std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

const ARMBaseRegisterInfo & getRegisterInfo() const

Definition ARMBaseInstrInfo.h:129

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig) const override

bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override

bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override

bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

bool expandPostRAPseudo(MachineInstr &MI) const override

outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override

bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override

bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override

VFP/NEON execution domains.

bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool isFpMLxInstruction(unsigned Opcode) const

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition ARMBaseInstrInfo.h:500

bool isSwiftFastImmShift(const MachineInstr *MI) const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

ARMBaseInstrInfo(const ARMSubtarget &STI, const ARMBaseRegisterInfo &TRI)

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...

void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override

bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override

void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override

const ARMSubtarget & getSubtarget() const

Definition ARMBaseInstrInfo.h:134

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override

bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

bool shouldSink(const MachineInstr &MI) const override

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Container class for subtarget features.

Itinerary data supplied by a subtarget to be used by a target.

A wrapper class for inspecting calls to intrinsic functions.

Intrinsic::ID getIntrinsicID() const

Return the intrinsic ID of this intrinsic.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

This class contains meta information specific to a module.

MachineOperand class - Representation of each machine instruction operand.

static MachineOperand CreateImm(int64_t Val)

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Represents one node in the SelectionDAG.

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

const TargetRegisterInfo & getRegisterInfo() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

InstrType

Represents how an instruction should be mapped by the outliner.

This is an optimization pass for GlobalISel generic memory operations.

static bool isIndirectCall(const MachineInstr &MI)

Definition ARMBaseInstrInfo.h:655

MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)

Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...

static bool isCondBranchOpcode(int Opc)

bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)

Returns true if Val1 has a lower Constant Materialization Cost than Val2.

static bool isPushOpcode(int Opc)

Definition ARMBaseInstrInfo.h:723

void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)

unsigned getBLXpredOpcode(const MachineFunction &MF)

static bool isIndirectBranchOpcode(int Opc)

static bool isVPTOpcode(int Opc)

Definition ARMBaseInstrInfo.h:571

bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)

Definition ARMBaseInstrInfo.h:897

bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)

bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)

Return true if Reg is defd between From and To.

static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)

Get the operands corresponding to the given Pred value.

Definition ARMBaseInstrInfo.h:542

static bool isMovRegOpcode(int Opc)

Definition ARMBaseInstrInfo.h:735

bool isGather(IntrinsicInst *IntInst)

Definition ARMBaseInstrInfo.h:926

static bool isSEHInstruction(const MachineInstr &MI)

Definition ARMBaseInstrInfo.h:761

static bool isSubImmOpcode(int Opc)

Definition ARMBaseInstrInfo.h:728

bool isGatherScatter(IntrinsicInst *IntInst)

Definition ARMBaseInstrInfo.h:954

bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)

Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...

static bool isJumpTableBranchOpcode(int Opc)

Definition ARMBaseInstrInfo.h:644

bool isMVEVectorInstruction(const MachineInstr *MI)

Definition ARMBaseInstrInfo.h:964

static bool isPopOpcode(int Opc)

Definition ARMBaseInstrInfo.h:717

void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)

static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)

isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...

Definition ARMBaseInstrInfo.h:741

void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)

unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)

Returns the number of instructions required to materialize the given constant in a register,...

bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)

rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.

static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)

Definition ARMBaseInstrInfo.h:704

void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)

emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...

ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)

getInstrPredicate - If instruction is predicated, returns its predicate condition,...

unsigned getMatchingCondBranchOpcode(unsigned Opc)

DWARFExpression::Operation Op

static bool isUncondBranchOpcode(int Opc)

bool isScatter(IntrinsicInst *IntInst)

Definition ARMBaseInstrInfo.h:940

static MachineOperand t1CondCodeOp(bool isDead=false)

Get the operand corresponding to the conditional code result for Thumb1.

Definition ARMBaseInstrInfo.h:557

static unsigned VCMPOpcodeToVPT(unsigned Opcode)

Definition ARMBaseInstrInfo.h:587

static MachineOperand condCodeOp(unsigned CCReg=0)

Get the operand corresponding to the conditional code result.

Definition ARMBaseInstrInfo.h:550

unsigned gettBLXrOpcode(const MachineFunction &MF)

int getAddSubImmediate(MachineInstr &MI)

Definition ARMBaseInstrInfo.h:872

static bool isSpeculationBarrierEndBBOpcode(int Opc)

Definition ARMBaseInstrInfo.h:710

unsigned getBLXOpcode(const MachineFunction &MF)

void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)

void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)

emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...

unsigned convertAddSubFlagsOpcode(unsigned OldOpc)

Map pseudo instructions that imply an 'S' bit onto real opcodes.

void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)

An individual sequence of instructions to be replaced with a call to an outlined function.

The information necessary to create an outlined function for some class of candidate.