LLVM: lib/Target/ARM/Disassembler/ARMDisassembler.cpp Source File (original) (raw)

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29#include

30#include

31#include

32#include

33

34using namespace llvm;

36

37#define DEBUG_TYPE "arm-disassembler"

38

40

41namespace {

42

43

44class ITStatus {

45public:

46

47 unsigned getITCC() {

49 if (instrInITBlock())

50 CC = ITStates.back();

51 return CC;

52 }

53

54

55 void advanceITState() { ITStates.pop_back(); }

56

57

58 bool instrInITBlock() { return !ITStates.empty(); }

59

60

61 bool instrLastInITBlock() { return ITStates.size() == 1; }

62

63

64

65

66

67 void setITState(char Firstcond, char Mask) {

68

70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);

71 assert(NumTZ <= 3 && "Invalid IT mask!");

72

73 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {

74 unsigned Else = (Mask >> Pos) & 1;

75 ITStates.push_back(CCBits ^ Else);

76 }

77 ITStates.push_back(CCBits);

78 }

79

80private:

81 std::vector ITStates;

82};

83

84class VPTStatus {

85public:

86 unsigned getVPTPred() {

88 if (instrInVPTBlock())

89 Pred = VPTStates.back();

90 return Pred;

91 }

92

93 void advanceVPTState() { VPTStates.pop_back(); }

94

95 bool instrInVPTBlock() { return !VPTStates.empty(); }

96

97 bool instrLastInVPTBlock() { return VPTStates.size() == 1; }

98

99 void setVPTState(char Mask) {

100

102 assert(NumTZ <= 3 && "Invalid VPT mask!");

103

104 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {

105 bool T = ((Mask >> Pos) & 1) == 0;

106 if (T)

108 else

110 }

112 }

113

114private:

116};

117

118

120public:

121 std::unique_ptr MCII;

122 mutable ITStatus ITBlock;

123 mutable VPTStatus VPTBlock;

124

128 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)

131 }

132

133 ~ARMDisassembler() override = default;

134

138

140 uint64_t Address) const override;

141

142private:

146

150

154

156};

157

158}

159

163

164

165

166

167

168

169

170

171

172

173

174

175

180

182 isBranch, 0, 0,

183 InstSize);

184}

185

186

187

188

189

190

191

192

193

194

199

200

201

203 ARM::R0, ARM::R1, ARM::R2, ARM::R3,

204 ARM::R4, ARM::R5, ARM::R6, ARM::R7,

205 ARM::R8, ARM::R9, ARM::R10, ARM::R11,

206 ARM::R12, ARM::SP, ARM::LR, ARM::PC

207};

208

210 ARM::R0, ARM::R1, ARM::R2, ARM::R3,

211 ARM::R4, ARM::R5, ARM::R6, ARM::R7,

212 ARM::R8, ARM::R9, ARM::R10, ARM::R11,

213 ARM::R12, 0, ARM::LR, ARM::APSR

214};

215

219 if (RegNo > 15)

221

225}

226

230 if (RegNo > 15)

232

236

239}

240

245

246 if (RegNo == 15)

248

250

251 return S;

252}

253

258

259 if (RegNo == 13)

261

263

264 return S;

265}

266

271

272 if (RegNo == 15)

273 {

276 }

277

279 return S;

280}

281

286

287 if (RegNo == 15)

288 {

291 }

292

293 if (RegNo == 13)

295

297 return S;

298}

299

304 if (RegNo == 13)

307 return S;

308}

309

317

319 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,

320 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP

321};

322

327

328

329

330 if (RegNo > 13)

332

333 if (RegNo & 1)

335

338 return S;

339}

340

344 if (RegNo > 13)

346

349

350 if ((RegNo & 1) || RegNo > 10)

353}

354

358 if (RegNo != 13)

360

364}

365

370 switch (RegNo) {

371 case 0:

373 break;

374 case 1:

376 break;

377 case 2:

379 break;

380 case 3:

382 break;

383 case 9:

385 break;

386 case 12:

388 break;

389 default:

391 }

392

395}

396

401

404

405 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)

407

409 return S;

410}

411

413 ARM::S0, ARM::S1, ARM::S2, ARM::S3,

414 ARM::S4, ARM::S5, ARM::S6, ARM::S7,

415 ARM::S8, ARM::S9, ARM::S10, ARM::S11,

416 ARM::S12, ARM::S13, ARM::S14, ARM::S15,

417 ARM::S16, ARM::S17, ARM::S18, ARM::S19,

418 ARM::S20, ARM::S21, ARM::S22, ARM::S23,

419 ARM::S24, ARM::S25, ARM::S26, ARM::S27,

420 ARM::S28, ARM::S29, ARM::S30, ARM::S31

421};

422

426 if (RegNo > 31)

428

432}

433

439

441 ARM::D0, ARM::D1, ARM::D2, ARM::D3,

442 ARM::D4, ARM::D5, ARM::D6, ARM::D7,

443 ARM::D8, ARM::D9, ARM::D10, ARM::D11,

444 ARM::D12, ARM::D13, ARM::D14, ARM::D15,

445 ARM::D16, ARM::D17, ARM::D18, ARM::D19,

446 ARM::D20, ARM::D21, ARM::D22, ARM::D23,

447 ARM::D24, ARM::D25, ARM::D26, ARM::D27,

448 ARM::D28, ARM::D29, ARM::D30, ARM::D31

449};

450

451

453 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)

454 return true;

457 return featureBits[ARM::FeatureD32];

458}

459

463 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))

465

469}

470

478

486

494

496 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,

497 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,

498 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,

499 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15

500};

501

505 if (RegNo > 31 || (RegNo & 1) != 0)

507 RegNo >>= 1;

508

512}

513

515 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,

516 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,

517 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,

518 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,

519 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,

520 ARM::Q15

521};

522

526 if (RegNo > 30)

528

532}

533

535 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,

536 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,

537 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,

538 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,

539 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,

540 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,

541 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,

542 ARM::D28_D30, ARM::D29_D31

543};

544

548 if (RegNo > 29)

550

554}

555

559 if (RegNo > 7)

561

565}

566

568 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,

569 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7

570};

571

575 if (RegNo > 6)

577

581}

582

584 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,

585 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7

586};

587

591 if (RegNo > 4)

593

597}

598

599

600

606

607 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)

610 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();

616 } else

618 return S;

619}

620

621

622

623

624

625

628 const auto *D = static_cast<const ARMDisassembler *>(Decoder);

630 if (D->getSubtargetInfo().hasFeature(ARM::ModeThumb))

631 CC = D->ITBlock.getITCC();

636}

637

641 if (Val)

643 else

646}

647

648

649

652 const auto *D = static_cast<const ARMDisassembler *>(Decoder);

653

654 MCRegister CCR = D->ITBlock.instrInITBlock() ? ARM::NoRegister : ARM::CPSR;

657}

658

661 const auto *D = static_cast<const ARMDisassembler *>(Decoder);

662 unsigned VCC = D->VPTBlock.getVPTPred();

664

668

670}

671

674 const auto *D = static_cast<const ARMDisassembler *>(Decoder);

675 unsigned VCC = D->VPTBlock.getVPTPred();

677

681

682

683

686 int TiedOpIdx = MCID.getOperandConstraint(InactiveOpIdx, MCOI::TIED_TO);

687 assert(TiedOpIdx >= 0 &&

688 "Inactive register in vpred_r is not tied to an output!");

689

690

692

694}

695

700

704

705

708

710 switch (type) {

711 case 0:

713 break;

714 case 1:

716 break;

717 case 2:

719 break;

720 case 3:

722 break;

723 }

724

727

728 unsigned Op = Shift | (imm << 3);

730

731 return S;

732}

733

738

742

743

748

750 switch (type) {

751 case 0:

753 break;

754 case 1:

756 break;

757 case 2:

759 break;

760 case 3:

762 break;

763 }

764

766

767 return S;

768}

769

774

775 bool NeedDisjointWriteback = false;

777 bool CLRM = false;

779 default:

780 break;

781 case ARM::LDMIA_UPD:

782 case ARM::LDMDB_UPD:

783 case ARM::LDMIB_UPD:

784 case ARM::LDMDA_UPD:

785 case ARM::t2LDMIA_UPD:

786 case ARM::t2LDMDB_UPD:

787 case ARM::t2STMIA_UPD:

788 case ARM::t2STMDB_UPD:

789 NeedDisjointWriteback = true;

791 break;

792 case ARM::t2CLRM:

793 CLRM = true;

794 break;

795 }

796

797

799 for (unsigned i = 0; i < 16; ++i) {

800 if (Val & (1 << i)) {

801 if (CLRM) {

804 }

805 } else {

808

809 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())

811 }

812 }

813 }

814

815 return S;

816}

817

822

825

826

827 if (regs == 0 || (Vd + regs) > 32) {

828 regs = Vd + regs > 32 ? 32 - Vd : regs;

829 regs = std::max( 1u, regs);

831 }

832

835 for (unsigned i = 0; i < (regs - 1); ++i) {

838 }

839

840 return S;

841}

842

847

850

851

852 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;

853 if (regs == 0 || (Vd + regs) > MaxReg) {

854 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;

855 regs = std::max( 1u, regs);

856 regs = std::min(MaxReg, regs);

858 }

859

862 for (unsigned i = 0; i < (regs - 1); ++i) {

865 }

866

867 return S;

868}

869

873

874

875

876

877

880

882 if (lsb > msb) {

884

885

886

887 lsb = msb;

888 }

889

890 uint32_t msb_mask = 0xFFFFFFFF;

891 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;

892 uint32_t lsb_mask = (1U << lsb) - 1;

893

895 return S;

896}

897

902

911

913 case ARM::LDC_OFFSET:

914 case ARM::LDC_PRE:

915 case ARM::LDC_POST:

916 case ARM::LDC_OPTION:

917 case ARM::LDCL_OFFSET:

918 case ARM::LDCL_PRE:

919 case ARM::LDCL_POST:

920 case ARM::LDCL_OPTION:

921 case ARM::STC_OFFSET:

922 case ARM::STC_PRE:

923 case ARM::STC_POST:

924 case ARM::STC_OPTION:

925 case ARM::STCL_OFFSET:

926 case ARM::STCL_PRE:

927 case ARM::STCL_POST:

928 case ARM::STCL_OPTION:

929 case ARM::t2LDC_OFFSET:

930 case ARM::t2LDC_PRE:

931 case ARM::t2LDC_POST:

932 case ARM::t2LDC_OPTION:

933 case ARM::t2LDCL_OFFSET:

934 case ARM::t2LDCL_PRE:

935 case ARM::t2LDCL_POST:

936 case ARM::t2LDCL_OPTION:

937 case ARM::t2STC_OFFSET:

938 case ARM::t2STC_PRE:

939 case ARM::t2STC_POST:

940 case ARM::t2STC_OPTION:

941 case ARM::t2STCL_OFFSET:

942 case ARM::t2STCL_PRE:

943 case ARM::t2STCL_POST:

944 case ARM::t2STCL_OPTION:

945 case ARM::t2LDC2_OFFSET:

946 case ARM::t2LDC2L_OFFSET:

947 case ARM::t2LDC2_PRE:

948 case ARM::t2LDC2L_PRE:

949 case ARM::t2STC2_OFFSET:

950 case ARM::t2STC2L_OFFSET:

951 case ARM::t2STC2_PRE:

952 case ARM::t2STC2L_PRE:

953 case ARM::LDC2_OFFSET:

954 case ARM::LDC2L_OFFSET:

955 case ARM::LDC2_PRE:

956 case ARM::LDC2L_PRE:

957 case ARM::STC2_OFFSET:

958 case ARM::STC2L_OFFSET:

959 case ARM::STC2_PRE:

960 case ARM::STC2L_PRE:

961 case ARM::t2LDC2_OPTION:

962 case ARM::t2STC2_OPTION:

963 case ARM::t2LDC2_POST:

964 case ARM::t2LDC2L_POST:

965 case ARM::t2STC2_POST:

966 case ARM::t2STC2L_POST:

967 case ARM::LDC2_POST:

968 case ARM::LDC2L_POST:

969 case ARM::STC2_POST:

970 case ARM::STC2L_POST:

971 if (coproc == 0xA || coproc == 0xB ||

972 (featureBits[ARM::HasV8_1MMainlineOps] &&

973 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||

974 coproc == 0xE || coproc == 0xF)))

976 break;

977 default:

978 break;

979 }

980

981 if (featureBits[ARM::HasV8Ops] && (coproc != 14))

983

988

990 case ARM::t2LDC2_OFFSET:

991 case ARM::t2LDC2L_OFFSET:

992 case ARM::t2LDC2_PRE:

993 case ARM::t2LDC2L_PRE:

994 case ARM::t2STC2_OFFSET:

995 case ARM::t2STC2L_OFFSET:

996 case ARM::t2STC2_PRE:

997 case ARM::t2STC2L_PRE:

998 case ARM::LDC2_OFFSET:

999 case ARM::LDC2L_OFFSET:

1000 case ARM::LDC2_PRE:

1001 case ARM::LDC2L_PRE:

1002 case ARM::STC2_OFFSET:

1003 case ARM::STC2L_OFFSET:

1004 case ARM::STC2_PRE:

1005 case ARM::STC2L_PRE:

1006 case ARM::t2LDC_OFFSET:

1007 case ARM::t2LDCL_OFFSET:

1008 case ARM::t2LDC_PRE:

1009 case ARM::t2LDCL_PRE:

1010 case ARM::t2STC_OFFSET:

1011 case ARM::t2STCL_OFFSET:

1012 case ARM::t2STC_PRE:

1013 case ARM::t2STCL_PRE:

1014 case ARM::LDC_OFFSET:

1015 case ARM::LDCL_OFFSET:

1016 case ARM::LDC_PRE:

1017 case ARM::LDCL_PRE:

1018 case ARM::STC_OFFSET:

1019 case ARM::STCL_OFFSET:

1020 case ARM::STC_PRE:

1021 case ARM::STCL_PRE:

1024 break;

1025 case ARM::t2LDC2_POST:

1026 case ARM::t2LDC2L_POST:

1027 case ARM::t2STC2_POST:

1028 case ARM::t2STC2L_POST:

1029 case ARM::LDC2_POST:

1030 case ARM::LDC2L_POST:

1031 case ARM::STC2_POST:

1032 case ARM::STC2L_POST:

1033 case ARM::t2LDC_POST:

1034 case ARM::t2LDCL_POST:

1035 case ARM::t2STC_POST:

1036 case ARM::t2STCL_POST:

1037 case ARM::LDC_POST:

1038 case ARM::LDCL_POST:

1039 case ARM::STC_POST:

1040 case ARM::STCL_POST:

1041 imm |= U << 8;

1042 [[fallthrough]];

1043 default:

1044

1045

1047 break;

1048 }

1049

1051 case ARM::LDC_OFFSET:

1052 case ARM::LDC_PRE:

1053 case ARM::LDC_POST:

1054 case ARM::LDC_OPTION:

1055 case ARM::LDCL_OFFSET:

1056 case ARM::LDCL_PRE:

1057 case ARM::LDCL_POST:

1058 case ARM::LDCL_OPTION:

1059 case ARM::STC_OFFSET:

1060 case ARM::STC_PRE:

1061 case ARM::STC_POST:

1062 case ARM::STC_OPTION:

1063 case ARM::STCL_OFFSET:

1064 case ARM::STCL_PRE:

1065 case ARM::STCL_POST:

1066 case ARM::STCL_OPTION:

1069 break;

1070 case ARM::t2LDC2L_OFFSET:

1071 case ARM::t2LDC2L_OPTION:

1072 case ARM::t2LDC2L_POST:

1073 case ARM::t2LDC2L_PRE:

1074 case ARM::t2LDC2_OFFSET:

1075 case ARM::t2LDC2_OPTION:

1076 case ARM::t2LDC2_POST:

1077 case ARM::t2LDC2_PRE:

1078 case ARM::t2LDCL_OFFSET:

1079 case ARM::t2LDCL_OPTION:

1080 case ARM::t2LDCL_POST:

1081 case ARM::t2LDCL_PRE:

1082 case ARM::t2LDC_OFFSET:

1083 case ARM::t2LDC_OPTION:

1084 case ARM::t2LDC_POST:

1085 case ARM::t2LDC_PRE:

1086 case ARM::t2STC2L_OFFSET:

1087 case ARM::t2STC2L_OPTION:

1088 case ARM::t2STC2L_POST:

1089 case ARM::t2STC2L_PRE:

1090 case ARM::t2STC2_OFFSET:

1091 case ARM::t2STC2_OPTION:

1092 case ARM::t2STC2_POST:

1093 case ARM::t2STC2_PRE:

1094 case ARM::t2STCL_OFFSET:

1095 case ARM::t2STCL_OPTION:

1096 case ARM::t2STCL_POST:

1097 case ARM::t2STCL_PRE:

1098 case ARM::t2STC_OFFSET:

1099 case ARM::t2STC_OPTION:

1100 case ARM::t2STC_POST:

1101 case ARM::t2STC_PRE:

1103 break;

1104 default:

1105 break;

1106 }

1107

1108 return S;

1109}

1110

1115

1124

1125

1127 case ARM::STR_POST_IMM:

1128 case ARM::STR_POST_REG:

1129 case ARM::STRB_POST_IMM:

1130 case ARM::STRB_POST_REG:

1131 case ARM::STRT_POST_REG:

1132 case ARM::STRT_POST_IMM:

1133 case ARM::STRBT_POST_REG:

1134 case ARM::STRBT_POST_IMM:

1137 break;

1138 default:

1139 break;

1140 }

1141

1144

1145

1147 case ARM::LDR_POST_IMM:

1148 case ARM::LDR_POST_REG:

1149 case ARM::LDRB_POST_IMM:

1150 case ARM::LDRB_POST_REG:

1151 case ARM::LDRBT_POST_REG:

1152 case ARM::LDRBT_POST_IMM:

1153 case ARM::LDRT_POST_REG:

1154 case ARM::LDRT_POST_IMM:

1157 break;

1158 default:

1159 break;

1160 }

1161

1164

1168

1169 bool writeback = (P == 0) || (W == 1);

1170 unsigned idx_mode = 0;

1171 if (P && writeback)

1173 else if ( && writeback)

1175

1176 if (writeback && (Rn == 15 || Rn == Rt))

1178

1179 if (reg) {

1184 case 0:

1186 break;

1187 case 1:

1189 break;

1190 case 2:

1192 break;

1193 case 3:

1195 break;

1196 default:

1198 }

1203

1205 } else {

1209 }

1210

1213

1214 return S;

1215}

1216

1221

1227

1229 switch (type) {

1230 case 0:

1232 break;

1233 case 1:

1235 break;

1236 case 2:

1238 break;

1239 case 3:

1241 break;

1242 }

1243

1246

1251 unsigned shift;

1252 if (U)

1254 else

1257

1258 return S;

1259}

1260

1266

1267

1268

1269

1271 if (Inst.getOpcode() == ARM::t2TSB)

1274}

1275

1280

1290 unsigned Rt2 = Rt + 1;

1291

1292 bool writeback = (W == 1) | (P == 0);

1293

1294

1296 case ARM::STRD:

1297 case ARM::STRD_PRE:

1298 case ARM::STRD_POST:

1299 case ARM::LDRD:

1300 case ARM::LDRD_PRE:

1301 case ARM::LDRD_POST:

1303 break;

1304 default:

1305 break;

1306 }

1308 case ARM::STRD:

1309 case ARM::STRD_PRE:

1310 case ARM::STRD_POST:

1311 if (P == 0 && W == 1)

1313

1314 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))

1316 if (type && Rm == 15)

1318 if (Rt2 == 15)

1322 break;

1323 case ARM::STRH:

1324 case ARM::STRH_PRE:

1325 case ARM::STRH_POST:

1326 if (Rt == 15)

1328 if (writeback && (Rn == 15 || Rn == Rt))

1330 if (!type && Rm == 15)

1332 break;

1333 case ARM::LDRD:

1334 case ARM::LDRD_PRE:

1335 case ARM::LDRD_POST:

1336 if (type && Rn == 15) {

1337 if (Rt2 == 15)

1339 break;

1340 }

1341 if (P == 0 && W == 1)

1343 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))

1345 if (!type && writeback && Rn == 15)

1347 if (writeback && (Rn == Rt || Rn == Rt2))

1349 break;

1350 case ARM::LDRH:

1351 case ARM::LDRH_PRE:

1352 case ARM::LDRH_POST:

1353 if (type && Rn == 15) {

1354 if (Rt == 15)

1356 break;

1357 }

1358 if (Rt == 15)

1360 if (!type && Rm == 15)

1362 if (!type && writeback && (Rn == 15 || Rn == Rt))

1364 break;

1365 case ARM::LDRSH:

1366 case ARM::LDRSH_PRE:

1367 case ARM::LDRSH_POST:

1368 case ARM::LDRSB:

1369 case ARM::LDRSB_PRE:

1370 case ARM::LDRSB_POST:

1371 if (type && Rn == 15) {

1372 if (Rt == 15)

1374 break;

1375 }

1376 if (type && (Rt == 15 || (writeback && Rn == Rt)))

1378 if (!type && (Rt == 15 || Rm == 15))

1380 if (!type && writeback && (Rn == 15 || Rn == Rt))

1382 break;

1383 default:

1384 break;

1385 }

1386

1387 if (writeback) {

1388 if (P)

1390 else

1392

1393

1395 case ARM::STRD:

1396 case ARM::STRD_PRE:

1397 case ARM::STRD_POST:

1398 case ARM::STRH:

1399 case ARM::STRH_PRE:

1400 case ARM::STRH_POST:

1403 break;

1404 default:

1405 break;

1406 }

1407 }

1408

1412 case ARM::STRD:

1413 case ARM::STRD_PRE:

1414 case ARM::STRD_POST:

1415 case ARM::LDRD:

1416 case ARM::LDRD_PRE:

1417 case ARM::LDRD_POST:

1420 break;

1421 default:

1422 break;

1423 }

1424

1425 if (writeback) {

1426

1428 case ARM::LDRD:

1429 case ARM::LDRD_PRE:

1430 case ARM::LDRD_POST:

1431 case ARM::LDRH:

1432 case ARM::LDRH_PRE:

1433 case ARM::LDRH_POST:

1434 case ARM::LDRSH:

1435 case ARM::LDRSH_PRE:

1436 case ARM::LDRSH_POST:

1437 case ARM::LDRSB:

1438 case ARM::LDRSB_PRE:

1439 case ARM::LDRSB_POST:

1440 case ARM::LDRHTr:

1441 case ARM::LDRSBTr:

1444 break;

1445 default:

1446 break;

1447 }

1448 }

1449

1452

1453 if (type) {

1456 } else {

1460 }

1461

1464

1465 return S;

1466}

1467

1472

1476

1477 return S;

1478}

1479

1487

1489

1490

1491

1496

1497

1498

1499

1500

1501

1503

1504 if (imod && M) {

1509 } else if (imod && !M) {

1514 } else if (!imod && M) {

1518 } else {

1519

1523 }

1524

1525 return S;

1526}

1527

1532

1537

1538 if (pred == 0xF)

1540

1549 return S;

1550}

1551

1557

1561

1562 if (pred == 0xF) {

1563

1565 case ARM::LDMDA:

1567 break;

1568 case ARM::LDMDA_UPD:

1570 break;

1571 case ARM::LDMDB:

1573 break;

1574 case ARM::LDMDB_UPD:

1576 break;

1577 case ARM::LDMIA:

1579 break;

1580 case ARM::LDMIA_UPD:

1582 break;

1583 case ARM::LDMIB:

1585 break;

1586 case ARM::LDMIB_UPD:

1588 break;

1589 case ARM::STMDA:

1591 break;

1592 case ARM::STMDA_UPD:

1594 break;

1595 case ARM::STMDB:

1597 break;

1598 case ARM::STMDB_UPD:

1600 break;

1601 case ARM::STMIA:

1603 break;

1604 case ARM::STMIA_UPD:

1606 break;

1607 case ARM::STMIB:

1609 break;

1610 case ARM::STMIB_UPD:

1612 break;

1613 default:

1615 }

1616

1617

1619

1623

1626 return S;

1627 }

1628

1630 }

1631

1640

1641 return S;

1642}

1643

1644

1652

1654

1656

1659

1660

1661

1662 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))

1664

1665 return S;

1666}

1667

1675

1677

1678

1679

1680

1681

1682

1684

1685 if (imod && M) {

1690 } else if (imod && !M) {

1695 } else if (!imod && M) {

1699 } else {

1700

1702

1707 }

1708

1709 return S;

1710}

1711

1716

1717 unsigned Opcode = ARM::t2HINT;

1718

1719 if (imm == 0x0D) {

1720 Opcode = ARM::t2PACBTI;

1721 } else if (imm == 0x1D) {

1722 Opcode = ARM::t2PAC;

1723 } else if (imm == 0x2D) {

1724 Opcode = ARM::t2AUT;

1725 } else if (imm == 0x0F) {

1726 Opcode = ARM::t2BTI;

1727 }

1728

1730 if (Opcode == ARM::t2HINT) {

1733 }

1734

1736}

1737

1742

1744 unsigned imm = 0;

1745

1750

1751 if (Inst.getOpcode() == ARM::t2MOVTi16)

1756

1759

1761 return S;

1762}

1763

1768

1771 unsigned imm = 0;

1772

1775

1776 if (Inst.getOpcode() == ARM::MOVTi16)

1779

1782

1785

1788

1789 return S;

1790}

1791

1796

1802

1803 if (pred == 0xF)

1805

1814

1817

1818 return S;

1819}

1820

1825

1827

1830

1831 if (!FeatureBits[ARM::HasV8_1aOps] ||

1832 !FeatureBits[ARM::HasV8Ops])

1834

1835

1836

1843

1846

1847 return S;

1848}

1849

1854

1858

1859 if (Pred == 0xF)

1861

1868

1869 return S;

1870}

1871

1876

1880

1883

1884 if (!add) imm *= -1;

1885 if (imm == 0 && !add) imm = INT32_MIN;

1887 if (Rn == 15)

1889

1890 return S;

1891}

1892

1897

1899

1902

1905

1906 if (U)

1908 else

1910

1911 return S;

1912}

1913

1918

1920

1923

1926

1927 if (U)

1929 else

1931

1932 return S;

1933}

1934

1940

1945

1946

1947

1948

1949

1950

1951

1955 unsigned I1 = !(J1 ^ S);

1956 unsigned I2 = !(J2 ^ S);

1959 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;

1962 true, 4, Inst, Decoder))

1964

1967}

1968

1973

1976

1977 if (pred == 0xF) {

1981 true, 4, Inst, Decoder))

1983 return S;

1984 }

1985

1987 true, 4, Inst, Decoder))

1989

1990

1991

1992 if (Inst.getOpcode() != ARM::BL)

1995

1996 return S;

1997}

1998

2003

2006

2009 if (!align)

2011 else

2013

2014 return S;

2015}

2016

2021

2028

2029

2031 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:

2032 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:

2033 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:

2034 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:

2035 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:

2036 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:

2037 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:

2038 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:

2039 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:

2042 break;

2043 case ARM::VLD2b16:

2044 case ARM::VLD2b32:

2045 case ARM::VLD2b8:

2046 case ARM::VLD2b16wb_fixed:

2047 case ARM::VLD2b16wb_register:

2048 case ARM::VLD2b32wb_fixed:

2049 case ARM::VLD2b32wb_register:

2050 case ARM::VLD2b8wb_fixed:

2051 case ARM::VLD2b8wb_register:

2054 break;

2055 default:

2058 }

2059

2060

2062 case ARM::VLD3d8:

2063 case ARM::VLD3d16:

2064 case ARM::VLD3d32:

2065 case ARM::VLD3d8_UPD:

2066 case ARM::VLD3d16_UPD:

2067 case ARM::VLD3d32_UPD:

2068 case ARM::VLD4d8:

2069 case ARM::VLD4d16:

2070 case ARM::VLD4d32:

2071 case ARM::VLD4d8_UPD:

2072 case ARM::VLD4d16_UPD:

2073 case ARM::VLD4d32_UPD:

2076 break;

2077 case ARM::VLD3q8:

2078 case ARM::VLD3q16:

2079 case ARM::VLD3q32:

2080 case ARM::VLD3q8_UPD:

2081 case ARM::VLD3q16_UPD:

2082 case ARM::VLD3q32_UPD:

2083 case ARM::VLD4q8:

2084 case ARM::VLD4q16:

2085 case ARM::VLD4q32:

2086 case ARM::VLD4q8_UPD:

2087 case ARM::VLD4q16_UPD:

2088 case ARM::VLD4q32_UPD:

2091 break;

2092 default:

2093 break;

2094 }

2095

2096

2098 case ARM::VLD3d8:

2099 case ARM::VLD3d16:

2100 case ARM::VLD3d32:

2101 case ARM::VLD3d8_UPD:

2102 case ARM::VLD3d16_UPD:

2103 case ARM::VLD3d32_UPD:

2104 case ARM::VLD4d8:

2105 case ARM::VLD4d16:

2106 case ARM::VLD4d32:

2107 case ARM::VLD4d8_UPD:

2108 case ARM::VLD4d16_UPD:

2109 case ARM::VLD4d32_UPD:

2112 break;

2113 case ARM::VLD3q8:

2114 case ARM::VLD3q16:

2115 case ARM::VLD3q32:

2116 case ARM::VLD3q8_UPD:

2117 case ARM::VLD3q16_UPD:

2118 case ARM::VLD3q32_UPD:

2119 case ARM::VLD4q8:

2120 case ARM::VLD4q16:

2121 case ARM::VLD4q32:

2122 case ARM::VLD4q8_UPD:

2123 case ARM::VLD4q16_UPD:

2124 case ARM::VLD4q32_UPD:

2127 break;

2128 default:

2129 break;

2130 }

2131

2132

2134 case ARM::VLD4d8:

2135 case ARM::VLD4d16:

2136 case ARM::VLD4d32:

2137 case ARM::VLD4d8_UPD:

2138 case ARM::VLD4d16_UPD:

2139 case ARM::VLD4d32_UPD:

2142 break;

2143 case ARM::VLD4q8:

2144 case ARM::VLD4q16:

2145 case ARM::VLD4q32:

2146 case ARM::VLD4q8_UPD:

2147 case ARM::VLD4q16_UPD:

2148 case ARM::VLD4q32_UPD:

2151 break;

2152 default:

2153 break;

2154 }

2155

2156

2158 case ARM::VLD1d8wb_fixed:

2159 case ARM::VLD1d16wb_fixed:

2160 case ARM::VLD1d32wb_fixed:

2161 case ARM::VLD1d64wb_fixed:

2162 case ARM::VLD1d8wb_register:

2163 case ARM::VLD1d16wb_register:

2164 case ARM::VLD1d32wb_register:

2165 case ARM::VLD1d64wb_register:

2166 case ARM::VLD1q8wb_fixed:

2167 case ARM::VLD1q16wb_fixed:

2168 case ARM::VLD1q32wb_fixed:

2169 case ARM::VLD1q64wb_fixed:

2170 case ARM::VLD1q8wb_register:

2171 case ARM::VLD1q16wb_register:

2172 case ARM::VLD1q32wb_register:

2173 case ARM::VLD1q64wb_register:

2174 case ARM::VLD1d8Twb_fixed:

2175 case ARM::VLD1d8Twb_register:

2176 case ARM::VLD1d16Twb_fixed:

2177 case ARM::VLD1d16Twb_register:

2178 case ARM::VLD1d32Twb_fixed:

2179 case ARM::VLD1d32Twb_register:

2180 case ARM::VLD1d64Twb_fixed:

2181 case ARM::VLD1d64Twb_register:

2182 case ARM::VLD1d8Qwb_fixed:

2183 case ARM::VLD1d8Qwb_register:

2184 case ARM::VLD1d16Qwb_fixed:

2185 case ARM::VLD1d16Qwb_register:

2186 case ARM::VLD1d32Qwb_fixed:

2187 case ARM::VLD1d32Qwb_register:

2188 case ARM::VLD1d64Qwb_fixed:

2189 case ARM::VLD1d64Qwb_register:

2190 case ARM::VLD2d8wb_fixed:

2191 case ARM::VLD2d16wb_fixed:

2192 case ARM::VLD2d32wb_fixed:

2193 case ARM::VLD2q8wb_fixed:

2194 case ARM::VLD2q16wb_fixed:

2195 case ARM::VLD2q32wb_fixed:

2196 case ARM::VLD2d8wb_register:

2197 case ARM::VLD2d16wb_register:

2198 case ARM::VLD2d32wb_register:

2199 case ARM::VLD2q8wb_register:

2200 case ARM::VLD2q16wb_register:

2201 case ARM::VLD2q32wb_register:

2202 case ARM::VLD2b8wb_fixed:

2203 case ARM::VLD2b16wb_fixed:

2204 case ARM::VLD2b32wb_fixed:

2205 case ARM::VLD2b8wb_register:

2206 case ARM::VLD2b16wb_register:

2207 case ARM::VLD2b32wb_register:

2209 break;

2210 case ARM::VLD3d8_UPD:

2211 case ARM::VLD3d16_UPD:

2212 case ARM::VLD3d32_UPD:

2213 case ARM::VLD3q8_UPD:

2214 case ARM::VLD3q16_UPD:

2215 case ARM::VLD3q32_UPD:

2216 case ARM::VLD4d8_UPD:

2217 case ARM::VLD4d16_UPD:

2218 case ARM::VLD4d32_UPD:

2219 case ARM::VLD4q8_UPD:

2220 case ARM::VLD4q16_UPD:

2221 case ARM::VLD4q32_UPD:

2224 break;

2225 default:

2226 break;

2227 }

2228

2229

2232

2233

2235 default:

2236

2237

2238

2239

2240

2241

2242 if (Rm == 0xd) {

2244 break;

2245 }

2246

2247 [[fallthrough]];

2248 case ARM::VLD1d8wb_fixed:

2249 case ARM::VLD1d16wb_fixed:

2250 case ARM::VLD1d32wb_fixed:

2251 case ARM::VLD1d64wb_fixed:

2252 case ARM::VLD1d8Twb_fixed:

2253 case ARM::VLD1d16Twb_fixed:

2254 case ARM::VLD1d32Twb_fixed:

2255 case ARM::VLD1d64Twb_fixed:

2256 case ARM::VLD1d8Qwb_fixed:

2257 case ARM::VLD1d16Qwb_fixed:

2258 case ARM::VLD1d32Qwb_fixed:

2259 case ARM::VLD1d64Qwb_fixed:

2260 case ARM::VLD1d8wb_register:

2261 case ARM::VLD1d16wb_register:

2262 case ARM::VLD1d32wb_register:

2263 case ARM::VLD1d64wb_register:

2264 case ARM::VLD1q8wb_fixed:

2265 case ARM::VLD1q16wb_fixed:

2266 case ARM::VLD1q32wb_fixed:

2267 case ARM::VLD1q64wb_fixed:

2268 case ARM::VLD1q8wb_register:

2269 case ARM::VLD1q16wb_register:

2270 case ARM::VLD1q32wb_register:

2271 case ARM::VLD1q64wb_register:

2272

2273

2274

2275 if (Rm != 0xD && Rm != 0xF &&

2278 break;

2279 case ARM::VLD2d8wb_fixed:

2280 case ARM::VLD2d16wb_fixed:

2281 case ARM::VLD2d32wb_fixed:

2282 case ARM::VLD2b8wb_fixed:

2283 case ARM::VLD2b16wb_fixed:

2284 case ARM::VLD2b32wb_fixed:

2285 case ARM::VLD2q8wb_fixed:

2286 case ARM::VLD2q16wb_fixed:

2287 case ARM::VLD2q32wb_fixed:

2288 break;

2289 }

2290

2292 return S;

2293}

2294

2299

2306

2307

2309 case ARM::VST1d8wb_fixed:

2310 case ARM::VST1d16wb_fixed:

2311 case ARM::VST1d32wb_fixed:

2312 case ARM::VST1d64wb_fixed:

2313 case ARM::VST1d8wb_register:

2314 case ARM::VST1d16wb_register:

2315 case ARM::VST1d32wb_register:

2316 case ARM::VST1d64wb_register:

2317 case ARM::VST1q8wb_fixed:

2318 case ARM::VST1q16wb_fixed:

2319 case ARM::VST1q32wb_fixed:

2320 case ARM::VST1q64wb_fixed:

2321 case ARM::VST1q8wb_register:

2322 case ARM::VST1q16wb_register:

2323 case ARM::VST1q32wb_register:

2324 case ARM::VST1q64wb_register:

2325 case ARM::VST1d8Twb_fixed:

2326 case ARM::VST1d16Twb_fixed:

2327 case ARM::VST1d32Twb_fixed:

2328 case ARM::VST1d64Twb_fixed:

2329 case ARM::VST1d8Twb_register:

2330 case ARM::VST1d16Twb_register:

2331 case ARM::VST1d32Twb_register:

2332 case ARM::VST1d64Twb_register:

2333 case ARM::VST1d8Qwb_fixed:

2334 case ARM::VST1d16Qwb_fixed:

2335 case ARM::VST1d32Qwb_fixed:

2336 case ARM::VST1d64Qwb_fixed:

2337 case ARM::VST1d8Qwb_register:

2338 case ARM::VST1d16Qwb_register:

2339 case ARM::VST1d32Qwb_register:

2340 case ARM::VST1d64Qwb_register:

2341 case ARM::VST2d8wb_fixed:

2342 case ARM::VST2d16wb_fixed:

2343 case ARM::VST2d32wb_fixed:

2344 case ARM::VST2d8wb_register:

2345 case ARM::VST2d16wb_register:

2346 case ARM::VST2d32wb_register:

2347 case ARM::VST2q8wb_fixed:

2348 case ARM::VST2q16wb_fixed:

2349 case ARM::VST2q32wb_fixed:

2350 case ARM::VST2q8wb_register:

2351 case ARM::VST2q16wb_register:

2352 case ARM::VST2q32wb_register:

2353 case ARM::VST2b8wb_fixed:

2354 case ARM::VST2b16wb_fixed:

2355 case ARM::VST2b32wb_fixed:

2356 case ARM::VST2b8wb_register:

2357 case ARM::VST2b16wb_register:

2358 case ARM::VST2b32wb_register:

2359 if (Rm == 0xF)

2362 break;

2363 case ARM::VST3d8_UPD:

2364 case ARM::VST3d16_UPD:

2365 case ARM::VST3d32_UPD:

2366 case ARM::VST3q8_UPD:

2367 case ARM::VST3q16_UPD:

2368 case ARM::VST3q32_UPD:

2369 case ARM::VST4d8_UPD:

2370 case ARM::VST4d16_UPD:

2371 case ARM::VST4d32_UPD:

2372 case ARM::VST4q8_UPD:

2373 case ARM::VST4q16_UPD:

2374 case ARM::VST4q32_UPD:

2377 break;

2378 default:

2379 break;

2380 }

2381

2382

2385

2386

2388 default:

2389 if (Rm == 0xD)

2391 else if (Rm != 0xF) {

2394 }

2395 break;

2396 case ARM::VST1d8wb_fixed:

2397 case ARM::VST1d16wb_fixed:

2398 case ARM::VST1d32wb_fixed:

2399 case ARM::VST1d64wb_fixed:

2400 case ARM::VST1q8wb_fixed:

2401 case ARM::VST1q16wb_fixed:

2402 case ARM::VST1q32wb_fixed:

2403 case ARM::VST1q64wb_fixed:

2404 case ARM::VST1d8Twb_fixed:

2405 case ARM::VST1d16Twb_fixed:

2406 case ARM::VST1d32Twb_fixed:

2407 case ARM::VST1d64Twb_fixed:

2408 case ARM::VST1d8Qwb_fixed:

2409 case ARM::VST1d16Qwb_fixed:

2410 case ARM::VST1d32Qwb_fixed:

2411 case ARM::VST1d64Qwb_fixed:

2412 case ARM::VST2d8wb_fixed:

2413 case ARM::VST2d16wb_fixed:

2414 case ARM::VST2d32wb_fixed:

2415 case ARM::VST2q8wb_fixed:

2416 case ARM::VST2q16wb_fixed:

2417 case ARM::VST2q32wb_fixed:

2418 case ARM::VST2b8wb_fixed:

2419 case ARM::VST2b16wb_fixed:

2420 case ARM::VST2b32wb_fixed:

2421 break;

2422 }

2423

2424

2426 case ARM::VST1q16:

2427 case ARM::VST1q32:

2428 case ARM::VST1q64:

2429 case ARM::VST1q8:

2430 case ARM::VST1q16wb_fixed:

2431 case ARM::VST1q16wb_register:

2432 case ARM::VST1q32wb_fixed:

2433 case ARM::VST1q32wb_register:

2434 case ARM::VST1q64wb_fixed:

2435 case ARM::VST1q64wb_register:

2436 case ARM::VST1q8wb_fixed:

2437 case ARM::VST1q8wb_register:

2438 case ARM::VST2d16:

2439 case ARM::VST2d32:

2440 case ARM::VST2d8:

2441 case ARM::VST2d16wb_fixed:

2442 case ARM::VST2d16wb_register:

2443 case ARM::VST2d32wb_fixed:

2444 case ARM::VST2d32wb_register:

2445 case ARM::VST2d8wb_fixed:

2446 case ARM::VST2d8wb_register:

2449 break;

2450 case ARM::VST2b16:

2451 case ARM::VST2b32:

2452 case ARM::VST2b8:

2453 case ARM::VST2b16wb_fixed:

2454 case ARM::VST2b16wb_register:

2455 case ARM::VST2b32wb_fixed:

2456 case ARM::VST2b32wb_register:

2457 case ARM::VST2b8wb_fixed:

2458 case ARM::VST2b8wb_register:

2461 break;

2462 default:

2465 }

2466

2467

2469 case ARM::VST3d8:

2470 case ARM::VST3d16:

2471 case ARM::VST3d32:

2472 case ARM::VST3d8_UPD:

2473 case ARM::VST3d16_UPD:

2474 case ARM::VST3d32_UPD:

2475 case ARM::VST4d8:

2476 case ARM::VST4d16:

2477 case ARM::VST4d32:

2478 case ARM::VST4d8_UPD:

2479 case ARM::VST4d16_UPD:

2480 case ARM::VST4d32_UPD:

2483 break;

2484 case ARM::VST3q8:

2485 case ARM::VST3q16:

2486 case ARM::VST3q32:

2487 case ARM::VST3q8_UPD:

2488 case ARM::VST3q16_UPD:

2489 case ARM::VST3q32_UPD:

2490 case ARM::VST4q8:

2491 case ARM::VST4q16:

2492 case ARM::VST4q32:

2493 case ARM::VST4q8_UPD:

2494 case ARM::VST4q16_UPD:

2495 case ARM::VST4q32_UPD:

2498 break;

2499 default:

2500 break;

2501 }

2502

2503

2505 case ARM::VST3d8:

2506 case ARM::VST3d16:

2507 case ARM::VST3d32:

2508 case ARM::VST3d8_UPD:

2509 case ARM::VST3d16_UPD:

2510 case ARM::VST3d32_UPD:

2511 case ARM::VST4d8:

2512 case ARM::VST4d16:

2513 case ARM::VST4d32:

2514 case ARM::VST4d8_UPD:

2515 case ARM::VST4d16_UPD:

2516 case ARM::VST4d32_UPD:

2519 break;

2520 case ARM::VST3q8:

2521 case ARM::VST3q16:

2522 case ARM::VST3q32:

2523 case ARM::VST3q8_UPD:

2524 case ARM::VST3q16_UPD:

2525 case ARM::VST3q32_UPD:

2526 case ARM::VST4q8:

2527 case ARM::VST4q16:

2528 case ARM::VST4q32:

2529 case ARM::VST4q8_UPD:

2530 case ARM::VST4q16_UPD:

2531 case ARM::VST4q32_UPD:

2534 break;

2535 default:

2536 break;

2537 }

2538

2539

2541 case ARM::VST4d8:

2542 case ARM::VST4d16:

2543 case ARM::VST4d32:

2544 case ARM::VST4d8_UPD:

2545 case ARM::VST4d16_UPD:

2546 case ARM::VST4d32_UPD:

2549 break;

2550 case ARM::VST4q8:

2551 case ARM::VST4q16:

2552 case ARM::VST4q32:

2553 case ARM::VST4q8_UPD:

2554 case ARM::VST4q16_UPD:

2555 case ARM::VST4q32_UPD:

2558 break;

2559 default:

2560 break;

2561 }

2562

2564 return S;

2565}

2566

2580

2596

2610

2621

2626

2633

2634 if (size == 0 && align == 1)

2636 align *= (1 << size);

2637

2639 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:

2640 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:

2641 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:

2642 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:

2645 break;

2646 default:

2649 break;

2650 }

2651 if (Rm != 0xF) {

2654 }

2655

2659

2660

2661

2662

2663 if (Rm != 0xD && Rm != 0xF &&

2666

2668 return S;

2669}

2670

2675

2682 align *= 2*size;

2683

2685 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:

2686 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:

2687 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:

2688 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:

2691 break;

2692 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:

2693 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:

2694 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:

2695 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:

2698 break;

2699 default:

2702 break;

2703 }

2704

2705 if (Rm != 0xF)

2707

2711

2712 if (Rm != 0xD && Rm != 0xF) {

2715 }

2716

2718 return S;

2719}

2720

2725

2731

2738 if (Rm != 0xF) {

2741 }

2742

2746

2747 if (Rm == 0xD)

2749 else if (Rm != 0xF) {

2752 }

2753

2755 return S;

2756}

2757

2762

2770

2771 if (size == 0x3) {

2772 if (align == 0)

2774 align = 16;

2775 } else {

2776 if (size == 2) {

2777 align *= 8;

2778 } else {

2780 align *= 4*size;

2781 }

2782 }

2783

2792 if (Rm != 0xF) {

2795 }

2796

2800

2801 if (Rm == 0xD)

2803 else if (Rm != 0xF) {

2806 }

2807

2809 return S;

2810}

2811

2816

2825

2826 if (Q) {

2829 } else {

2832 }

2833

2835

2837 case ARM::VORRiv4i16:

2838 case ARM::VORRiv2i32:

2839 case ARM::VBICiv4i16:

2840 case ARM::VBICiv2i32:

2843 break;

2844 case ARM::VORRiv8i16:

2845 case ARM::VORRiv4i32:

2846 case ARM::VBICiv8i16:

2847 case ARM::VBICiv4i32:

2850 break;

2851 default:

2852 break;

2853 }

2854

2856 return S;

2857}

2858

2863

2870 imm |= cmode << 8;

2872

2873 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)

2875

2878

2880

2882 return S;

2883}

2884

2889

2895

2906

2908 return S;

2909}

2910

2915

2921

2927

2929 return S;

2930}

2931

2938

2945

2952

2959

2964

2972

2975 if (op) {

2978 }

2979

2981 case ARM::VTBL2:

2982 case ARM::VTBX2:

2985 break;

2986 default:

2989 }

2990

2993

2995 return S;

2996}

2997

3002

3005

3008

3010 default:

3012 case ARM::tADR:

3013 break;

3014 case ARM::tADDrSPi:

3016 break;

3017 }

3018

3021 return S;

3022}

3023

3028 true, 2, Inst, Decoder))

3031}

3032

3037 true, 4, Inst, Decoder))

3040}

3041

3046 true, 2, Inst, Decoder))

3049}

3050

3055

3058

3063

3064 return S;

3065}

3066

3071

3074

3078

3079 return S;

3080}

3081

3085 unsigned imm = Val << 2;

3086

3089

3091}

3092

3101

3106

3110

3111

3113 case ARM::t2STRHs:

3114 case ARM::t2STRBs:

3115 case ARM::t2STRs:

3116 if (Rn == 15)

3118 break;

3119 default:

3120 break;

3121 }

3122

3128

3129 return S;

3130}

3131

3136

3140

3143

3144 bool hasV7Ops = featureBits[ARM::HasV7Ops];

3145

3146 if (Rt == 15) {

3148 case ARM::t2LDRBpci:

3149 case ARM::t2LDRHpci:

3151 break;

3152 case ARM::t2LDRSBpci:

3154 break;

3155 case ARM::t2LDRSHpci:

3157 default:

3158 break;

3159 }

3160 }

3161

3163 case ARM::t2PLDpci:

3164 break;

3165 case ARM::t2PLIpci:

3166 if (!hasV7Ops)

3168 break;

3169 default:

3172 }

3173

3174 if (!U) {

3175

3176 if (imm == 0)

3177 imm = INT32_MIN;

3178 else

3179 imm = -imm;

3180 }

3182

3184 return S;

3185}

3186

3191

3194

3197

3198 bool hasMP = featureBits[ARM::FeatureMP];

3199 bool hasV7Ops = featureBits[ARM::HasV7Ops];

3200

3201 if (Rn == 15) {

3203 case ARM::t2LDRBs:

3205 break;

3206 case ARM::t2LDRHs:

3208 break;

3209 case ARM::t2LDRSHs:

3210 Inst.setOpcode(ARM::t2LDRSHpci);

3211 break;

3212 case ARM::t2LDRSBs:

3213 Inst.setOpcode(ARM::t2LDRSBpci);

3214 break;

3215 case ARM::t2LDRs:

3217 break;

3218 case ARM::t2PLDs:

3220 break;

3221 case ARM::t2PLIs:

3223 break;

3224 default:

3226 }

3227

3229 }

3230

3231 if (Rt == 15) {

3233 case ARM::t2LDRSHs:

3235 case ARM::t2LDRHs:

3237 break;

3238 case ARM::t2LDRSBs:

3240 break;

3241 default:

3242 break;

3243 }

3244 }

3245

3247 case ARM::t2PLDs:

3248 break;

3249 case ARM::t2PLIs:

3250 if (!hasV7Ops)

3252 break;

3253 case ARM::t2PLDWs:

3254 if (!hasV7Ops || !hasMP)

3256 break;

3257 default:

3260 }

3261

3267

3269 return S;

3270}

3271

3274 int imm = Val & 0xFF;

3275 if (Val == 0)

3276 imm = INT32_MIN;

3277 else if (!(Val & 0x100))

3278 imm *= -1;

3280

3282}

3283

3288

3291

3292

3294 case ARM::t2STRT:

3295 case ARM::t2STRBT:

3296 case ARM::t2STRHT:

3297 case ARM::t2STRi8:

3298 case ARM::t2STRHi8:

3299 case ARM::t2STRBi8:

3300 if (Rn == 15)

3302 break;

3303 default:

3304 break;

3305 }

3306

3307

3309 case ARM::t2LDRT:

3310 case ARM::t2LDRBT:

3311 case ARM::t2LDRHT:

3312 case ARM::t2LDRSBT:

3313 case ARM::t2LDRSHT:

3314 case ARM::t2STRT:

3315 case ARM::t2STRBT:

3316 case ARM::t2STRHT:

3317 imm |= 0x100;

3318 break;

3319 default:

3320 break;

3321 }

3322

3327

3328 return S;

3329}

3330

3335

3340 imm |= (U << 8);

3341 imm |= (Rn << 9);

3343

3346

3347 bool hasMP = featureBits[ARM::FeatureMP];

3348 bool hasV7Ops = featureBits[ARM::HasV7Ops];

3349

3350 if (Rn == 15) {

3352 case ARM::t2LDRi8:

3354 break;

3355 case ARM::t2LDRBi8:

3357 break;

3358 case ARM::t2LDRSBi8:

3359 Inst.setOpcode(ARM::t2LDRSBpci);

3360 break;

3361 case ARM::t2LDRHi8:

3363 break;

3364 case ARM::t2LDRSHi8:

3365 Inst.setOpcode(ARM::t2LDRSHpci);

3366 break;

3367 case ARM::t2PLDi8:

3369 break;

3370 case ARM::t2PLIi8:

3372 break;

3373 default:

3375 }

3377 }

3378

3379 if (Rt == 15) {

3381 case ARM::t2LDRSHi8:

3383 case ARM::t2LDRHi8:

3384 if (!add)

3386 break;

3387 case ARM::t2LDRSBi8:

3389 break;

3390 default:

3391 break;

3392 }

3393 }

3394

3396 case ARM::t2PLDi8:

3397 break;

3398 case ARM::t2PLIi8:

3399 if (!hasV7Ops)

3401 break;

3402 case ARM::t2PLDWi8:

3403 if (!hasV7Ops || !hasMP)

3405 break;

3406 default:

3409 }

3410

3414 return S;

3415}

3416

3421

3424

3425

3427 case ARM::t2STRi12:

3428 case ARM::t2STRBi12:

3429 case ARM::t2STRHi12:

3430 if (Rn == 15)

3432 break;

3433 default:

3434 break;

3435 }

3436

3440

3441 return S;

3442}

3443

3448

3452 imm |= (Rn << 13);

3453

3456

3457 bool hasMP = featureBits[ARM::FeatureMP];

3458 bool hasV7Ops = featureBits[ARM::HasV7Ops];

3459

3460 if (Rn == 15) {

3462 case ARM::t2LDRi12:

3464 break;

3465 case ARM::t2LDRHi12:

3467 break;

3468 case ARM::t2LDRSHi12:

3469 Inst.setOpcode(ARM::t2LDRSHpci);

3470 break;

3471 case ARM::t2LDRBi12:

3473 break;

3474 case ARM::t2LDRSBi12:

3475 Inst.setOpcode(ARM::t2LDRSBpci);

3476 break;

3477 case ARM::t2PLDi12:

3479 break;

3480 case ARM::t2PLIi12:

3482 break;

3483 default:

3485 }

3487 }

3488

3489 if (Rt == 15) {

3491 case ARM::t2LDRSHi12:

3493 case ARM::t2LDRHi12:

3495 break;

3496 case ARM::t2LDRSBi12:

3498 break;

3499 default:

3500 break;

3501 }

3502 }

3503

3505 case ARM::t2PLDi12:

3506 break;

3507 case ARM::t2PLIi12:

3508 if (!hasV7Ops)

3510 break;

3511 case ARM::t2PLDWi12:

3512 if (!hasV7Ops || !hasMP)

3514 break;

3515 default:

3518 }

3519

3523 return S;

3524}

3525

3529

3533 imm |= (Rn << 9);

3534

3535 if (Rn == 15) {

3537 case ARM::t2LDRT:

3539 break;

3540 case ARM::t2LDRBT:

3542 break;

3543 case ARM::t2LDRHT:

3545 break;

3546 case ARM::t2LDRSBT:

3547 Inst.setOpcode(ARM::t2LDRSBpci);

3548 break;

3549 case ARM::t2LDRSHT:

3550 Inst.setOpcode(ARM::t2LDRSHpci);

3551 break;

3552 default:

3554 }

3556 }

3557

3563 return S;

3564}

3565

3568 if (Val == 0)

3570 else {

3571 int imm = Val & 0xFF;

3572

3573 if (!(Val & 0x100)) imm *= -1;

3575 }

3576

3578}

3579

3582 if (Val == 0)

3584 else {

3585 int imm = Val & 0x7F;

3586

3587 if (!(Val & 0x80))

3588 imm *= -1;

3590 }

3591

3593}

3594

3599

3602

3607

3608 return S;

3609}

3610

3615

3618

3623

3624 return S;

3625}

3626

3631

3634

3637

3639

3640 return S;

3641}

3642

3643template

3646 int imm = Val & 0x7F;

3647 if (Val == 0)

3648 imm = INT32_MIN;

3649 else if (!(Val & 0x80))

3650 imm *= -1;

3651 if (imm != INT32_MIN)

3652 imm *= (1U << shift);

3654

3656}

3657

3658template

3663

3666

3671

3672 return S;

3673}

3674

3675template <int shift, int WriteBack>

3680

3683 if (WriteBack) {

3690

3691 return S;

3692}

3693

3698

3703 addr |= Rn << 9;

3705

3706 if (Rn == 15) {

3708 case ARM::t2LDR_PRE:

3709 case ARM::t2LDR_POST:

3711 break;

3712 case ARM::t2LDRB_PRE:

3713 case ARM::t2LDRB_POST:

3715 break;

3716 case ARM::t2LDRH_PRE:

3717 case ARM::t2LDRH_POST:

3719 break;

3720 case ARM::t2LDRSB_PRE:

3721 case ARM::t2LDRSB_POST:

3722 if (Rt == 15)

3724 else

3725 Inst.setOpcode(ARM::t2LDRSBpci);

3726 break;

3727 case ARM::t2LDRSH_PRE:

3728 case ARM::t2LDRSH_POST:

3729 Inst.setOpcode(ARM::t2LDRSHpci);

3730 break;

3731 default:

3733 }

3735 }

3736

3737 if () {

3740 }

3741

3744

3748 }

3749

3752

3754 return S;

3755}

3756

3769

3774

3775 if (Inst.getOpcode() == ARM::tADDrSP) {

3778

3784 } else if (Inst.getOpcode() == ARM::tADDspr) {

3786

3791 }

3792

3794 return S;

3795}

3796

3808

3815

3819

3820 return S;

3821}

3822

3829

3834

3835 return S;

3836}

3837

3838template

3845

3848

3850 if (imm == 0)

3851 imm = INT32_MIN;

3852 else

3853 imm *= -1;

3854 }

3855 if (imm != INT32_MIN)

3856 imm *= (1U << shift);

3858

3859 return S;

3860}

3861

3865

3866

3867

3868

3869

3870

3871

3872 unsigned S = (Val >> 23) & 1;

3873 unsigned J1 = (Val >> 22) & 1;

3874 unsigned J2 = (Val >> 21) & 1;

3875 unsigned I1 = !(J1 ^ S);

3876 unsigned I2 = !(J2 ^ S);

3877 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);

3879

3881 (Address & ~2u) + imm32 + 4,

3882 true, 4, Inst, Decoder))

3885}

3886

3890 if (Val == 0xA || Val == 0xB)

3892

3895

3898

3901}

3902

3909

3912

3919 return S;

3920}

3921

3925 if (Val & ~0xf)

3927

3930}

3931

3936

3938 if (pred == 0xE || pred == 0xF) {

3940 switch (opc) {

3941 default:

3943 case 0xf3bf8f4:

3945 break;

3946 case 0xf3bf8f5:

3948 break;

3949 case 0xf3bf8f6:

3951 break;

3952 }

3953

3956 }

3957

3963

3968

3969 return S;

3970}

3971

3972

3973

3974

3978 if (ctrl == 0) {

3981 switch (byte) {

3982 case 0:

3984 break;

3985 case 1:

3987 break;

3988 case 2:

3990 break;

3991 case 3:

3993 (imm << 8) | imm));

3994 break;

3995 }

3996 } else {

4001 }

4002

4004}

4005

4010 true, 2, Inst, Decoder))

4013}

4014

4018

4019

4020

4021

4022

4023

4024

4025 unsigned S = (Val >> 23) & 1;

4026 unsigned J1 = (Val >> 22) & 1;

4027 unsigned J2 = (Val >> 21) & 1;

4028 unsigned I1 = !(J1 ^ S);

4029 unsigned I2 = !(J2 ^ S);

4030 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);

4032

4034 true, 4, Inst, Decoder))

4037}

4038

4042 if (Val & ~0xf)

4044

4047}

4048

4054

4055 if (FeatureBits[ARM::FeatureMClass]) {

4056 unsigned ValLow = Val & 0xff;

4057

4058

4059 switch (ValLow) {

4060 case 0:

4061 case 1:

4062 case 2:

4063 case 3:

4064 case 5:

4065 case 6:

4066 case 7:

4067 case 8:

4068 case 9:

4069 case 16:

4070 case 20:

4071 break;

4072 case 17:

4073 case 18:

4074 case 19:

4075 if (!(FeatureBits[ARM::HasV7Ops]))

4076

4078 break;

4079 case 0x8a:

4080 case 0x8b:

4081 case 0x91:

4082 case 0x93:

4083 if (!(FeatureBits[ARM::HasV8MMainlineOps]))

4085 [[fallthrough]];

4086 case 10:

4087 case 11:

4088 case 0x88:

4089 case 0x89:

4090 case 0x90:

4091 case 0x94:

4092 case 0x98:

4093 if (!(FeatureBits[ARM::Feature8MSecExt]))

4095 break;

4096 case 0x20:

4097 case 0x21:

4098 case 0x22:

4099 case 0x23:

4100 case 0x24:

4101 case 0x25:

4102 case 0x26:

4103 case 0x27:

4104 case 0xa0:

4105 case 0xa1:

4106 case 0xa2:

4107 case 0xa3:

4108 case 0xa4:

4109 case 0xa5:

4110 case 0xa6:

4111 case 0xa7:

4112 if (!(FeatureBits[ARM::FeaturePACBTI]))

4114 break;

4115 default:

4116

4118 break;

4119 }

4120

4121 if (Inst.getOpcode() == ARM::t2MSR_M) {

4123 if (!(FeatureBits[ARM::HasV7Ops])) {

4124

4125

4126 if (Mask != 2)

4128 }

4129 else {

4130

4131

4132

4133

4134

4135

4136 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||

4137 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))

4139 }

4140 }

4141 } else {

4142

4143 if (Val == 0)

4145 }

4147 return S;

4148}

4149

4155

4156

4157

4158

4159 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))

4161

4164}

4165

4170

4174

4175 if (Rn == 0xF)

4177

4184

4185 return S;

4186}

4187

4192

4197

4200

4201 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)

4203

4210

4211 return S;

4212}

4213

4218

4225

4227

4236

4237 return S;

4238}

4239

4244

4252

4255

4264

4265 return S;

4266}

4267

4272

4279

4281

4290

4291 return S;

4292}

4293

4298

4305

4307

4316

4317 return S;

4318}

4319

4323

4329

4330 unsigned align = 0;

4331 unsigned index = 0;

4332 switch (size) {

4333 default:

4335 case 0:

4339 break;

4340 case 1:

4345 align = 2;

4346 break;

4347 case 2:

4351

4353 case 0 :

4354 align = 0; break;

4355 case 3:

4356 align = 4; break;

4357 default:

4359 }

4360 break;

4361 }

4362

4365 if (Rm != 0xF) {

4368 }

4372 if (Rm != 0xF) {

4373 if (Rm != 0xD) {

4376 } else

4378 }

4379

4383

4385 return S;

4386}

4387

4391

4397

4398 unsigned align = 0;

4399 unsigned index = 0;

4400 switch (size) {

4401 default:

4403 case 0:

4407 break;

4408 case 1:

4413 align = 2;

4414 break;

4415 case 2:

4419

4421 case 0:

4422 align = 0; break;

4423 case 3:

4424 align = 4; break;

4425 default:

4427 }

4428 break;

4429 }

4430

4431 if (Rm != 0xF) {

4434 }

4438 if (Rm != 0xF) {

4439 if (Rm != 0xD) {

4442 } else

4444 }

4445

4449

4451 return S;

4452}

4453

4457

4463

4464 unsigned align = 0;

4465 unsigned index = 0;

4466 unsigned inc = 1;

4467 switch (size) {

4468 default:

4470 case 0:

4473 align = 2;

4474 break;

4475 case 1:

4478 align = 4;

4480 inc = 2;

4481 break;

4482 case 2:

4487 align = 8;

4489 inc = 2;

4490 break;

4491 }

4492

4497 if (Rm != 0xF) {

4500 }

4504 if (Rm != 0xF) {

4505 if (Rm != 0xD) {

4508 } else

4510 }

4511

4517

4519 return S;

4520}

4521

4525

4531

4532 unsigned align = 0;

4533 unsigned index = 0;

4534 unsigned inc = 1;

4535 switch (size) {

4536 default:

4538 case 0:

4541 align = 2;

4542 break;

4543 case 1:

4546 align = 4;

4548 inc = 2;

4549 break;

4550 case 2:

4555 align = 8;

4557 inc = 2;

4558 break;

4559 }

4560

4561 if (Rm != 0xF) {

4564 }

4568 if (Rm != 0xF) {

4569 if (Rm != 0xD) {

4572 } else

4574 }

4575

4581

4583 return S;

4584}

4585

4589

4595

4596 unsigned align = 0;

4597 unsigned index = 0;

4598 unsigned inc = 1;

4599 switch (size) {

4600 default:

4602 case 0:

4606 break;

4607 case 1:

4612 inc = 2;

4613 break;

4614 case 2:

4619 inc = 2;

4620 break;

4621 }

4622

4629

4630 if (Rm != 0xF) {

4633 }

4637 if (Rm != 0xF) {

4638 if (Rm != 0xD) {

4641 } else

4643 }

4644

4652

4654 return S;

4655}

4656

4660

4666

4667 unsigned align = 0;

4668 unsigned index = 0;

4669 unsigned inc = 1;

4670 switch (size) {

4671 default:

4673 case 0:

4677 break;

4678 case 1:

4683 inc = 2;

4684 break;

4685 case 2:

4690 inc = 2;

4691 break;

4692 }

4693

4694 if (Rm != 0xF) {

4697 }

4701 if (Rm != 0xF) {

4702 if (Rm != 0xD) {

4705 } else

4707 }

4708

4716

4718 return S;

4719}

4720

4724

4730

4731 unsigned align = 0;

4732 unsigned index = 0;

4733 unsigned inc = 1;

4734 switch (size) {

4735 default:

4737 case 0:

4739 align = 4;

4741 break;

4742 case 1:

4744 align = 8;

4747 inc = 2;

4748 break;

4749 case 2:

4751 case 0:

4752 align = 0; break;

4753 case 3:

4755 default:

4757 }

4758

4761 inc = 2;

4762 break;

4763 }

4764

4773

4774 if (Rm != 0xF) {

4777 }

4781 if (Rm != 0xF) {

4782 if (Rm != 0xD) {

4785 } else

4787 }

4788

4798

4800 return S;

4801}

4802

4806

4812

4813 unsigned align = 0;

4814 unsigned index = 0;

4815 unsigned inc = 1;

4816 switch (size) {

4817 default:

4819 case 0:

4821 align = 4;

4823 break;

4824 case 1:

4826 align = 8;

4829 inc = 2;

4830 break;

4831 case 2:

4833 case 0:

4834 align = 0; break;

4835 case 3:

4837 default:

4839 }

4840

4843 inc = 2;

4844 break;

4845 }

4846

4847 if (Rm != 0xF) {

4850 }

4854 if (Rm != 0xF) {

4855 if (Rm != 0xD) {

4858 } else

4860 }

4861

4871

4873 return S;

4874}

4875

4884

4885 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)

4887

4898

4899 return S;

4900}

4901

4910

4911 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)

4913

4924

4925 return S;

4926}

4927

4933

4934 if (pred == 0xF) {

4935 pred = 0xE;

4937 }

4938

4939 if (mask == 0x0)

4941

4942

4943

4944

4945

4946 if (pred & 1) {

4947 unsigned LowBit = mask & -mask;

4948 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);

4949 mask ^= BitsAboveLowBit;

4950 }

4951

4954 return S;

4955}

4956

4961

4969 bool writeback = (W == 1) | (P == 0);

4970

4971 addr |= (U << 8) | (Rn << 9);

4972

4973 if (writeback && (Rn == Rt || Rn == Rt2))

4975 if (Rt == Rt2)

4977

4978

4981

4984

4987

4990

4992 return S;

4993}

4994

4999

5007 bool writeback = (W == 1) | (P == 0);

5008

5009 addr |= (U << 8) | (Rn << 9);

5010

5011 if (writeback && (Rn == Rt || Rn == Rt2))

5013

5014

5017

5020

5023

5026

5028 return S;

5029}

5030

5039

5043

5044 if (sign1) {

5045

5046

5047 if (!Val) {

5050 } else

5051 Val = -Val;

5052 }

5055 return S;

5056}

5057

5062

5063

5066 return S;

5067}

5068

5075

5076 if (pred == 0xF)

5078

5080

5081 if (Rt == Rn || Rn == Rt2)

5083

5092

5093 return S;

5094}

5095

5100 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];

5101

5109

5111

5112

5113 if (!(imm & 0x38)) {

5114 if (cmode == 0xF) {

5117 }

5118 if (hasFullFP16) {

5119 if (cmode == 0xE) {

5120 if (op == 1) {

5122 } else {

5124 }

5125 }

5126 if (cmode == 0xD) {

5127 if (op == 1) {

5129 } else {

5131 }

5132 }

5133 if (cmode == 0xC) {

5134 if (op == 1) {

5136 } else {

5138 }

5139 }

5140 }

5142 }

5143

5145

5151

5153 return S;

5154}

5155

5160 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];

5161

5169

5171

5172

5173 if (!(imm & 0x38)) {

5174 if (cmode == 0xF) {

5177 }

5178 if (hasFullFP16) {

5179 if (cmode == 0xE) {

5180 if (op == 1) {

5182 } else {

5184 }

5185 }

5186 if (cmode == 0xD) {

5187 if (op == 1) {

5189 } else {

5191 }

5192 }

5193 if (cmode == 0xC) {

5194 if (op == 1) {

5196 } else {

5198 }

5199 }

5200 }

5202 }

5203

5205

5211

5213 return S;

5214}

5215

5228

5230

5232

5233 if ((S, DestRegDecoder(Inst, Vd, Address, Decoder)))

5235 if ((S, DestRegDecoder(Inst, Vd, Address, Decoder)))

5237 if ((S, DestRegDecoder(Inst, Vn, Address, Decoder)))

5241

5242

5245

5246 return S;

5247}

5248

5252

5258

5261

5272

5273 return S;

5274}

5275

5280

5286

5287 if ((cop & ~0x1) == 0xa)

5289

5290 if (Rt == Rt2)

5292

5293

5294

5295

5296

5297

5298

5299

5300

5301

5302

5303 if (Inst.getOpcode() == ARM::MRRC2) {

5308 }

5311 if (Inst.getOpcode() == ARM::MCRR2) {

5316 }

5318

5319 return S;

5320}

5321

5328

5329

5330

5332 case ARM::VMSR_FPSCR_NZCVQC:

5334 break;

5335 case ARM::VMSR_P0:

5337 break;

5338 }

5339

5340 if (Inst.getOpcode() != ARM::FMSTAT) {

5342

5343 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {

5344 if (Rt == 13 || Rt == 15)

5347 } else

5349 }

5350

5351

5353 case ARM::VMRS_FPSCR_NZCVQC:

5355 break;

5356 case ARM::VMRS_P0:

5358 break;

5359 }

5360

5361 if (featureBits[ARM::ModeThumb]) {

5364 } else {

5368 }

5369

5370 return S;

5371}

5372

5373template <bool isSigned, bool isNeg, bool zeroPermitted, int size>

5378 if (Val == 0 && !zeroPermitted)

5380

5384 else

5385 DecVal = (Val << 1);

5386

5388 Decoder))

5390 return S;

5391}

5392

5396

5398 Val = LocImm + (2 << Val);

5400 Decoder))

5403}

5404

5413

5417

5418 if (Inst.getOpcode() == ARM::MVE_LCTP) {

5420 return S;

5421 }

5422

5426 case ARM::t2LEUpdate:

5427 case ARM::MVE_LETP:

5430 [[fallthrough]];

5431 case ARM::t2LE:

5433 Inst, Imm, Address, Decoder)))

5435 break;

5436 case ARM::t2WLS:

5437 case ARM::MVE_WLSTP_8:

5438 case ARM::MVE_WLSTP_16:

5439 case ARM::MVE_WLSTP_32:

5440 case ARM::MVE_WLSTP_64:

5444 Address, Decoder)) ||

5446 Inst, Imm, Address, Decoder)))

5448 break;

5449 case ARM::t2DLS:

5450 case ARM::MVE_DLSTP_8:

5451 case ARM::MVE_DLSTP_16:

5452 case ARM::MVE_DLSTP_32:

5453 case ARM::MVE_DLSTP_64:

5455 if (Rn == 0xF) {

5456

5457

5458

5459 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;

5460 if ((Insn & ~SBZMask) != CanonicalLCTP)

5462 if (Insn != CanonicalLCTP)

5464

5467 } else {

5471 Address, Decoder)))

5473 }

5474 break;

5475 }

5476 return S;

5477}

5478

5483

5484 if (Val == 0)

5485 Val = 32;

5486

5488

5489 return S;

5490}

5491

5495 if ((RegNo) + 1 > 11)

5497

5501}

5502

5506 if ((RegNo) > 14)

5508

5512}

5513

5518 if (RegNo == 15) {

5521 }

5522

5525

5526 if (RegNo == 13)

5528

5530}

5531

5535

5539 if (regs == 0) {

5540

5541 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {

5546 }

5547 } else {

5550

5551

5552 unsigned max_reg = Vd + regs;

5553 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))

5555 unsigned max_sreg = std::min(32u, max_reg);

5556 unsigned max_dreg = std::min(32u, max_reg / 2);

5557 for (unsigned i = Vd; i < max_sreg; ++i)

5560 for (unsigned i = 16; i < max_dreg; ++i)

5563 }

5565

5566 return S;

5567}

5568

5573

5574

5575

5576

5577 unsigned Imm = 0;

5578

5579 unsigned CurBit = 0;

5580 for (int i = 3; i >= 0; --i) {

5581

5582

5583 CurBit ^= (Val >> i) & 1U;

5584

5585

5586 Imm |= (CurBit << i);

5587

5588

5589 if ((Val & ~(~0U << i)) == 0) {

5590 Imm |= 1U << i;

5591 break;

5592 }

5593 }

5594

5596

5597 return S;

5598}

5599

5606

5610 unsigned Code;

5611 switch (Val & 0x3) {

5612 case 0:

5614 break;

5615 case 1:

5617 break;

5618 case 2:

5620 break;

5621 case 3:

5623 break;

5624 }

5627}

5628

5635

5639 unsigned Code;

5640 switch (Val) {

5641 default:

5643 case 0:

5645 break;

5646 case 1:

5648 break;

5649 case 4:

5651 break;

5652 case 5:

5654 break;

5655 case 6:

5657 break;

5658 case 7:

5660 break;

5661 }

5662

5665}

5666

5671

5672 unsigned DecodedVal = 64 - Val;

5673

5675 case ARM::MVE_VCVTf16s16_fix:

5676 case ARM::MVE_VCVTs16f16_fix:

5677 case ARM::MVE_VCVTf16u16_fix:

5678 case ARM::MVE_VCVTu16f16_fix:

5679 if (DecodedVal > 16)

5681 break;

5682 case ARM::MVE_VCVTf32s32_fix:

5683 case ARM::MVE_VCVTs32f32_fix:

5684 case ARM::MVE_VCVTf32u32_fix:

5685 case ARM::MVE_VCVTu32f32_fix:

5686 if (DecodedVal > 32)

5688 break;

5689 }

5690

5692

5693 return S;

5694}

5695

5697 switch (Opcode) {

5698 case ARM::VSTR_P0_off:

5699 case ARM::VSTR_P0_pre:

5700 case ARM::VSTR_P0_post:

5701 case ARM::VLDR_P0_off:

5702 case ARM::VLDR_P0_pre:

5703 case ARM::VLDR_P0_post:

5704 return ARM::P0;

5705 case ARM::VSTR_FPSCR_NZCVQC_off:

5706 case ARM::VSTR_FPSCR_NZCVQC_pre:

5707 case ARM::VSTR_FPSCR_NZCVQC_post:

5708 case ARM::VLDR_FPSCR_NZCVQC_off:

5709 case ARM::VLDR_FPSCR_NZCVQC_pre:

5710 case ARM::VLDR_FPSCR_NZCVQC_post:

5711 return ARM::FPSCR;

5712 default:

5713 return 0;

5714 }

5715}

5716

5717template

5722 case ARM::VSTR_FPSCR_pre:

5723 case ARM::VSTR_FPSCR_NZCVQC_pre:

5724 case ARM::VLDR_FPSCR_pre:

5725 case ARM::VLDR_FPSCR_NZCVQC_pre:

5726 case ARM::VSTR_FPSCR_off:

5727 case ARM::VSTR_FPSCR_NZCVQC_off:

5728 case ARM::VLDR_FPSCR_off:

5729 case ARM::VLDR_FPSCR_NZCVQC_off:

5730 case ARM::VSTR_FPSCR_post:

5731 case ARM::VSTR_FPSCR_NZCVQC_post:

5732 case ARM::VLDR_FPSCR_post:

5733 case ARM::VLDR_FPSCR_NZCVQC_post:

5736

5737 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])

5739 }

5740

5747

5748 if (Writeback) {

5751 }

5754

5757

5758 return S;

5759}

5760

5766

5770

5771 if ((S, RnDecoder(Inst, Rn, Address, Decoder)))

5775 if ((S, AddrDecoder(Inst, addr, Address, Decoder)))

5777

5779 return S;

5780}

5781

5782template

5791

5792template

5801

5802template

5811

5812template <unsigned MinLog, unsigned MaxLog>

5817

5818 if (Val < MinLog || Val > MaxLog)

5820

5822 return S;

5823}

5824

5825template

5830

5832

5833 return S;

5834}

5835

5845

5856

5858 return S;

5859}

5860

5870

5883

5885 return S;

5886}

5887

5892

5896

5897 if (RdaHi == 14) {

5898

5899

5900

5901

5902

5904

5906 case ARM::MVE_ASRLr:

5907 case ARM::MVE_SQRSHRL:

5908 Inst.setOpcode(ARM::MVE_SQRSHR);

5909 break;

5910 case ARM::MVE_LSLLr:

5911 case ARM::MVE_UQRSHLL:

5912 Inst.setOpcode(ARM::MVE_UQRSHL);

5913 break;

5914 default:

5916 }

5917

5918

5921

5922

5925

5926

5929

5931

5934

5935 if (Rda == Rm)

5937

5938 return S;

5939 }

5940

5941

5942

5943

5944

5949

5950

5955

5956

5959

5960 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||

5961 Inst.getOpcode() == ARM::MVE_UQRSHLL) {

5963

5965 }

5966

5968 return S;

5969}

5970

5980

5988 return S;

5989}

5990

5991template <bool scalar, OperandDecoder predicate_decoder>

5999

6000 unsigned fc;

6001

6002 if (scalar) {

6009 } else {

6017 }

6018

6019 if ((S, predicate_decoder(Inst, fc, Address, Decoder)))

6021

6023 return S;

6024}

6025

6036

6046

6059 if (sign1 != sign2)

6061

6062

6068 if (TypeT3) {

6069 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);

6072 } else {

6073 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);

6074 if ((DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder)))

6079 }

6080

6081 return DS;

6082}

6083

6088

6090

6091

6092

6095

6097

6098

6100

6101 return S;

6102}

6103

6104#include "ARMGenDisassemblerTables.inc"

6105

6106

6111 switch (MI.getOpcode()) {

6112 case ARM::HVC: {

6113

6114

6116 if (Cond == 0xF)

6118 if (Cond != 0xE)

6120 return Result;

6121 }

6122 case ARM::t2ADDri:

6123 case ARM::t2ADDri12:

6124 case ARM::t2ADDrr:

6125 case ARM::t2ADDrs:

6126 case ARM::t2SUBri:

6127 case ARM::t2SUBri12:

6128 case ARM::t2SUBrr:

6129 case ARM::t2SUBrs:

6130 if (MI.getOperand(0).getReg() == ARM::SP &&

6131 MI.getOperand(1).getReg() != ARM::SP)

6133 return Result;

6134 default: return Result;

6135 }

6136}

6137

6140

6141

6142

6143 if (!STI.hasFeature(ARM::ModeThumb))

6144 return 4;

6145

6146

6147

6148

6149

6150

6151

6152

6153

6154

6155

6156

6157

6158 if (Bytes.size() < 2)

6159 return 2;

6160

6162 Bytes.data(), InstructionEndianness);

6163 return Insn16 < 0xE800 ? 2 : 4;

6164}

6165

6166DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

6167 ArrayRef<uint8_t> Bytes,

6169 raw_ostream &CS) const {

6171 if (STI.hasFeature(ARM::ModeThumb))

6172 S = getThumbInstruction(MI, Size, Bytes, Address, CS);

6173 else

6174 S = getARMInstruction(MI, Size, Bytes, Address, CS);

6175 if (S == DecodeStatus::Fail)

6176 return S;

6177

6178

6179 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());

6183 Twine(MI.getNumOperands()) + "\n");

6184 }

6185

6186 return S;

6187}

6188

6189DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,

6190 ArrayRef<uint8_t> Bytes,

6192 raw_ostream &CS) const {

6193 CommentStream = &CS;

6194

6195 assert(!STI.hasFeature(ARM::ModeThumb) &&

6196 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "

6197 "mode!");

6198

6199

6200 if (Bytes.size() < 4) {

6203 }

6204

6205

6207 InstructionEndianness);

6208

6209

6211 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);

6215 }

6216

6217 const uint8_t *Tables[] = {

6218 DecoderTableVFP32, DecoderTableVFPV832,

6219 DecoderTableNEONData32, DecoderTableNEONLoadStore32,

6220 DecoderTableNEONDup32, DecoderTablev8NEON32,

6221 DecoderTablev8Crypto32,

6222 };

6223

6224 for (const uint8_t *Table : Tables) {

6225 Result = decodeInstruction(Table, MI, Insn, Address, this, STI);

6229 }

6230 }

6231

6233 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);

6237 }

6238

6241}

6242

6243bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {

6244 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());

6245 for (unsigned i = 0; i < MCID.NumOperands; ++i) {

6247 return true;

6248 }

6249 return false;

6250}

6251

6252

6253

6254

6255

6257ARMDisassembler::checkThumbPredicate(MCInst &MI) const {

6259

6260 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();

6261

6262 switch (MI.getOpcode()) {

6263 case ARM::tBcc:

6264 case ARM::t2Bcc:

6265 case ARM::tCBZ:

6266 case ARM::tCBNZ:

6267 case ARM::tCPS:

6268 case ARM::t2CPS3p:

6269 case ARM::t2CPS2p:

6270 case ARM::t2CPS1p:

6271 case ARM::t2CSEL:

6272 case ARM::t2CSINC:

6273 case ARM::t2CSINV:

6274 case ARM::t2CSNEG:

6275 case ARM::tMOVSr:

6276 case ARM::tSETEND:

6277

6278

6279 if (ITBlock.instrInITBlock())

6281 else

6283 break;

6284 case ARM::t2HINT:

6285 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)

6287 break;

6288 case ARM::tB:

6289 case ARM::t2B:

6290 case ARM::t2TBB:

6291 case ARM::t2TBH:

6292

6293

6294 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())

6296 break;

6297 default:

6298 break;

6299 }

6300

6301

6302

6306

6307 if (ITBlock.instrInITBlock())

6308 ITBlock.advanceITState();

6309 else if (VPTBlock.instrInVPTBlock())

6310 VPTBlock.advanceVPTState();

6311

6312 return S;

6313}

6314

6315

6316

6317

6318

6319

6320void ARMDisassembler::UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const {

6321 unsigned CC;

6322 CC = ITBlock.getITCC();

6323 if (CC == 0xF)

6325 if (ITBlock.instrInITBlock())

6326 ITBlock.advanceITState();

6327 else if (VPTBlock.instrInVPTBlock()) {

6328 CC = VPTBlock.getVPTPred();

6329 VPTBlock.advanceVPTState();

6330 }

6331

6332 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());

6336 for (unsigned i = 0; i < NumOps; ++i, ++I) {

6337 if (OpInfo[i].isPredicate() ) {

6340 I->setImm(CC);

6341 ++I;

6343 I->setReg(ARM::NoRegister);

6344 else

6345 I->setReg(ARM::CPSR);

6346 return;

6347 }

6348 }

6349}

6350

6351DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,

6352 ArrayRef<uint8_t> Bytes,

6354 raw_ostream &CS) const {

6355 CommentStream = &CS;

6356

6357 assert(STI.hasFeature(ARM::ModeThumb) &&

6358 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");

6359

6360

6361 if (Bytes.size() < 2) {

6364 }

6365

6367 Bytes.data(), InstructionEndianness);

6369 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);

6372 Check(Result, checkThumbPredicate(MI));

6374 }

6375

6376 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,

6377 STI);

6378 if (Result) {

6380 Check(Result, checkThumbPredicate(MI));

6382 }

6383

6385 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);

6388

6389

6390

6391 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())

6393

6394 Check(Result, checkThumbPredicate(MI));

6395

6396

6397

6398

6399 if (MI.getOpcode() == ARM::t2IT) {

6400 unsigned Firstcond = MI.getOperand(0).getImm();

6401 unsigned Mask = MI.getOperand(1).getImm();

6402 ITBlock.setITState(Firstcond, Mask);

6403

6404

6406 CS << "unpredictable IT predicate sequence";

6407 }

6408

6410 }

6411

6412

6413 if (Bytes.size() < 4) {

6416 }

6417

6418 uint32_t Insn32 =

6420 Bytes.data() + 2, InstructionEndianness);

6421

6423 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);

6426

6427

6428

6429 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())

6431

6432 Check(Result, checkThumbPredicate(MI));

6433

6435 unsigned Mask = MI.getOperand(0).getImm();

6436 VPTBlock.setVPTState(Mask);

6437 }

6438

6440 }

6441

6443 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);

6446 Check(Result, checkThumbPredicate(MI));

6448 }

6449

6451 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);

6454 Check(Result, checkThumbPredicate(MI));

6456 }

6457

6460 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);

6463 UpdateThumbPredicate(Result, MI);

6465 }

6466 }

6467

6469 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);

6473 }

6474

6476 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,

6477 STI);

6480 UpdateThumbPredicate(Result, MI);

6482 }

6483 }

6484

6486 uint32_t NEONLdStInsn = Insn32;

6487 NEONLdStInsn &= 0xF0FFFFFF;

6488 NEONLdStInsn |= 0x04000000;

6489 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,

6493 Check(Result, checkThumbPredicate(MI));

6495 }

6496 }

6497

6499 uint32_t NEONDataInsn = Insn32;

6500 NEONDataInsn &= 0xF0FFFFFF;

6501 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;

6502 NEONDataInsn |= 0x12000000;

6503 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,

6507 Check(Result, checkThumbPredicate(MI));

6509 }

6510

6511 uint32_t NEONCryptoInsn = Insn32;

6512 NEONCryptoInsn &= 0xF0FFFFFF;

6513 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;

6514 NEONCryptoInsn |= 0x12000000;

6515 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,

6520 }

6521

6522 uint32_t NEONv8Insn = Insn32;

6523 NEONv8Insn &= 0xF3FFFFFF;

6524 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,

6525 this, STI);

6529 }

6530 }

6531

6534 ? DecoderTableThumb2CDE32

6535 : DecoderTableThumb2CoProc32;

6537 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);

6540 Check(Result, checkThumbPredicate(MI));

6542 }

6543

6544

6545

6546 if (ITBlock.instrInITBlock())

6547 ITBlock.advanceITState();

6550}

6551

6555 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());

6556}

6557

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

AMDGPU Mark last scratch load

static bool isVectorPredicable(const MCInstrDesc &MCID)

static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:546

static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:638

static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1112

static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3627

static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3417

static const uint16_t GPRPairDecoderTable[]

Definition ARMDisassembler.cpp:318

static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4240

static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:342

static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4188

static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3975

static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3526

static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1999

static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:6037

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:216

static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5992

static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5861

static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2939

static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1914

static const MCPhysReg QQPRDecoderTable[]

Definition ARMDisassembler.cpp:567

static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3132

static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:502

static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2953

static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4721

static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:843

static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5276

static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3082

static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5827

static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:241

static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1764

static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3284

static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:397

static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3659

static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1969

static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3611

static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const MCDisassembler *Decoder)

tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...

Definition ARMDisassembler.cpp:195

static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:268

static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:696

static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2946

static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2622

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler()

Definition ARMDisassembler.cpp:6559

static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1738

static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3694

static const MCPhysReg DPairDecoderTable[]

Definition ARMDisassembler.cpp:514

static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1261

static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5783

static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4166

static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3067

static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5813

static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3580

static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1528

static const MCPhysReg DPairSpacedDecoderTable[]

Definition ARMDisassembler.cpp:534

static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3024

static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5601

static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4294

static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:423

static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1821

static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3770

static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:588

static DecodeStatus DecodeVpredNOperand(MCInst &Inst, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:659

static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4454

static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:6047

static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition ARMDisassembler.cpp:6552

static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3444

static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)

Definition ARMDisassembler.cpp:5696

static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4388

static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5249

static const MCPhysReg QPRDecoderTable[]

Definition ARMDisassembler.cpp:495

static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4657

static const MCPhysReg SPRDecoderTable[]

Definition ARMDisassembler.cpp:412

static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5393

static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5630

static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1217

static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:310

static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:227

static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1893

static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:572

static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4902

static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5515

DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:160

static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4015

static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3887

static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1276

static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1792

static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5069

static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:283

static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5096

static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2295

static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:898

static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:487

static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1668

static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4006

static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5803

static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1935

static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3093

static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4995

static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4320

static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:452

static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3272

static const uint16_t CLRMGPRDecoderTable[]

Definition ARMDisassembler.cpp:209

static const MCPhysReg DPRDecoderTable[]

Definition ARMDisassembler.cpp:440

static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3809

static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4586

static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4957

static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5058

static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3566

static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3797

static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1480

static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2998

static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5608

static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5156

static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:818

static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:323

static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4049

static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2911

static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:556

static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)

tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...

Definition ARMDisassembler.cpp:176

static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3331

static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2597

static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:301

static const uint16_t GPRDecoderTable[]

Definition ARMDisassembler.cpp:202

static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3839

static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3644

static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:460

static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3042

static DecodeStatus DecodeVpredROperand(MCInst &Inst, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:672

static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5793

static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5971

static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5667

static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5836

static const MCPhysReg QQQQPRDecoderTable[]

Definition ARMDisassembler.cpp:583

static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5479

static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3823

static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2859

static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4928

static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:355

static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:734

static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2611

static DecodeStatus DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder)

Definition ARMDisassembler.cpp:5762

static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:870

static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2758

static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3595

static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3903

static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:6026

static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)

Definition ARMDisassembler.cpp:6107

static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5718

static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4803

static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3922

static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2671

static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5217

static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4268

static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:366

static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5405

static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4522

static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5569

static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:770

static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5889

static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2017

static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:601

static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3102

static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2932

static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3676

static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2581

static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1850

static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1872

static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2960

static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4214

static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1713

static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3757

static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5374

static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:434

static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:523

static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2812

static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5637

static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1645

static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5532

static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3033

static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2885

static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1468

static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2721

static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1941

static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3932

static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5031

static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:471

static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5503

static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3051

static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4150

static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5492

static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:1553

static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3862

static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:254

static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:2567

static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:479

static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4876

static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:6084

static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:3187

static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5322

static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:4039

static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition ARMDisassembler.cpp:5414

static constexpr unsigned long long mask(BlockVerifier::State S)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

#define LLVM_EXTERNAL_VISIBILITY

static bool isNeg(Value *V)

Returns true if the operation is a negation of V, and it works for both integers and floats.

static bool isSigned(unsigned int Opcode)

amode Optimize addressing mode

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

static bool isBranch(unsigned Opcode)

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Container class for subtarget features.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

const MCSubtargetInfo & getSubtargetInfo() const

void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

unsigned getNumOperands() const

SmallVectorImpl< MCOperand >::iterator iterator

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

unsigned short NumOperands

bool isPredicable() const

Return true if this instruction has a predicate operand that controls execution.

bool isVariadic() const

Return true if this instruction can have a variable number of operands.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Instances of this class represent operands of the MCInst class.

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegister getReg() const

Returns the register number.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

Wrapper class representing virtual and physical registers.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)

unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)

getAM5Opc - This function encodes the addrmode5 opc field.

unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)

getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.

bool isVpred(OperandType op)

bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)

@ D16

Only 16 D registers.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

value_type read(const void *memory, endianness endian)

Read a value of a particular endianness from memory.

This is an optimization pass for GlobalISel generic memory operations.

constexpr T rotr(T V, int R)

auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)

Get the size of a range.

Target & getTheThumbBETarget()

static bool isVPTOpcode(int Opc)

LLVM_ABI void reportFatalInternalError(Error Err)

Report a fatal error that indicates a bug in LLVM.

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)

isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

Target & getTheARMLETarget()

Target & getTheARMBETarget()

Target & getTheThumbLETarget()

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.