LLVM: lib/Target/ARM/Disassembler/ARMDisassembler.cpp File Reference (original) (raw)

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◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-disassembler"

◆ OperandDecoder

◆ checkDecodedInstruction()

◆ createARMDisassembler()

◆ DecodeAddrMode2IdxInstruction()

Definition at line 1112 of file ARMDisassembler.cpp.

References llvm::ARM_AM::add, llvm::MCInst::addOperand(), llvm::ARM_AM::asr, Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeGPRnopcRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::ARM_AM::getAM2Opc(), llvm::MCInst::getOpcode(), llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, Opc, P, llvm::ARM_AM::ror, llvm::ARM_AM::rrx, llvm::MCDisassembler::SoftFail, llvm::ARM_AM::sub, and llvm::MCDisassembler::Success.

◆ DecodeAddrMode3Instruction()

Definition at line 1276 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, P, llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

◆ DecodeAddrMode5FP16Operand()

◆ DecodeAddrMode5Operand()

◆ DecodeAddrMode6Operand()

◆ DecodeAddrMode7Operand()

◆ DecodeAddrModeImm12Operand()

◆ DecodeArmMOVTWInstruction()

◆ DecodeBankedReg()

◆ DecodeBFAfterTargetOperand()

◆ DecodeBFLabelOperand()

template<bool isSigned, bool isNeg, bool zeroPermitted, int size>

◆ DecodeBitfieldMaskOperand()

◆ DecodeBranchImmInstruction()

Definition at line 1969 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::MCInst::setOpcode(), llvm::SignExtend32(), llvm::MCDisassembler::Success, and tryAddingSymbolicOperand().

◆ DecodeCCOutOperand() [1/2]

◆ DecodeCCOutOperand() [2/2]

◆ DecodeCLRMGPRRegisterClass()

◆ DecodeCopMemInstruction()

Definition at line 898 of file ARMDisassembler.cpp.

References llvm::ARM_AM::add, llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::ARM_AM::getAM5Opc(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::ARM_AM::sub, and llvm::MCDisassembler::Success.

◆ DecodeCoprocessor()

◆ DecodeCPSInstruction()

◆ DecodeDoubleRegLoad()

◆ DecodeDoubleRegStore()

◆ DecodeDPairRegisterClass()

◆ DecodeDPairSpacedRegisterClass()

◆ DecodeDPR_8RegisterClass()

◆ DecodeDPR_VFP2RegisterClass()

◆ DecodeDPRRegisterClass()

Definition at line 460 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), DPRDecoderTable, llvm::MCDisassembler::Fail, PermitsD32(), and llvm::MCDisassembler::Success.

Referenced by DecodeDPR_8RegisterClass(), DecodeDPR_VFP2RegisterClass(), DecodeDPRRegListOperand(), DecodeNEONComplexLane64Instruction(), DecodeTBLInstruction(), DecodeVCVTD(), DecodeVLD1DupInstruction(), DecodeVLD1LN(), DecodeVLD2DupInstruction(), DecodeVLD2LN(), DecodeVLD3DupInstruction(), DecodeVLD3LN(), DecodeVLD4DupInstruction(), DecodeVLD4LN(), DecodeVLDInstruction(), DecodeVMOVModImmInstruction(), DecodeVSCCLRM(), DecodeVSHLMaxInstruction(), DecodeVST1LN(), DecodeVST2LN(), DecodeVST3LN(), DecodeVST4LN(), and DecodeVSTInstruction().

◆ DecodeDPRRegListOperand()

◆ DecodeForVMRSandVMSR()

Definition at line 5322 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARMCC::AL, Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeGPRnopcRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

◆ DecodeGPRnopcRegisterClass()

Definition at line 241 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

Referenced by DecodeAddrMode2IdxInstruction(), DecodeArmMOVTWInstruction(), DecodeDoubleRegStore(), DecodeForVMRSandVMSR(), DecodeLDR(), DecodeMveAddrModeRQ(), DecodePostIdxReg(), DecodeQADDInstruction(), DecoderForMRRC2AndMCRR2(), DecodeSMLAInstruction(), DecodeSORegRegOperand(), DecodeSwap(), DecodeT2AddrModeImm0_1020s4(), DecodeT2AddrModeImm7(), DecodeT2AddrModeImm7s4(), and DecodeVSTRVLDR_SYSREG().

◆ DecodeGPRnospRegisterClass()

◆ DecodeGPRPairnospRegisterClass()

◆ DecodeGPRPairRegisterClass()

◆ DecodeGPRRegisterClass()

Definition at line 216 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, GPRDecoderTable, and llvm::MCDisassembler::Success.

Referenced by DecodeAddrMode2IdxInstruction(), DecodeAddrMode3Instruction(), DecodeAddrMode5FP16Operand(), DecodeAddrMode5Operand(), DecodeAddrMode6Operand(), DecodeAddrMode7Operand(), DecodeAddrModeImm12Operand(), DecodeCopMemInstruction(), DecodeDoubleRegLoad(), DecodeDoubleRegStore(), DecodeForVMRSandVMSR(), DecodeGPRnopcRegisterClass(), DecodeGPRnospRegisterClass(), DecodeGPRwithAPSRRegisterClass(), DecodeGPRwithZRRegisterClass(), DecodeLazyLoadStoreMul(), DecodeLDRPreImm(), DecodeLDRPreReg(), DecodeMemMultipleWritebackInstruction(), DecodeMVEVMOVDRegtoQ(), DecodeMVEVMOVQtoDReg(), DecodeRegListOperand(), DecodeRFEInstruction(), DecoderGPRRegisterClass(), DecodeSORegMemOperand(), DecodeSTRPreImm(), DecodeSTRPreReg(), DecodeT2AddrModeImm12(), DecodeT2AddrModeImm8(), DecodeT2AddrModeImm8s4(), DecodeT2AddrModeSOReg(), DecodeT2LdStPre(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodetGPRRegisterClass(), DecodeThumbAddSPReg(), DecodeThumbTableBranch(), DecodeTSTInstruction(), DecodeVLD1DupInstruction(), DecodeVLD1LN(), DecodeVLD2DupInstruction(), DecodeVLD2LN(), DecodeVLD3DupInstruction(), DecodeVLD3LN(), DecodeVLD4DupInstruction(), DecodeVLD4LN(), DecodeVLDInstruction(), DecodeVMOVRRS(), DecodeVMOVSRR(), DecodeVST1LN(), DecodeVST2LN(), DecodeVST3LN(), DecodeVST4LN(), and DecodeVSTInstruction().

◆ DecodeGPRspRegisterClass()

◆ DecodeGPRwithAPSR_NZCVnospRegisterClass()

◆ DecodeGPRwithAPSRRegisterClass()

◆ DecodeGPRwithZRnospRegisterClass()

◆ DecodeGPRwithZRRegisterClass()

◆ DecodeHINTInstruction()

◆ DecodeHPRRegisterClass()

◆ DecodeInstSyncBarrierOption()

◆ DecodeIT()

◆ DecodeLazyLoadStoreMul()

◆ DecodeLDR()

◆ DecodeLDRPreImm()

◆ DecodeLDRPreReg()

◆ DecodeLOLoop()

Definition at line 5414 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createReg(), DecodeBFLabelOperand(), DecodePredicateOperand(), DecoderGPRRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::MCInst::setOpcode(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

◆ DecodeLongShiftOperand()

◆ DecodeMemBarrierOption()

◆ DecodeMemMultipleWritebackInstruction()

Definition at line 1553 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeGPRRegisterClass(), DecodePredicateOperand(), DecodeRegListOperand(), DecodeRFEInstruction(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeMQPRRegisterClass()

Definition at line 556 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, QPRDecoderTable, and llvm::MCDisassembler::Success.

Referenced by DecodeMVE_MEM_3_pre(), DecodeMVE_MEM_pre(), DecodeMveAddrModeQ(), DecodeMveAddrModeRQ(), DecodeMVEModImmInstruction(), DecodeMVEVADCInstruction(), DecodeMVEVCMP(), DecodeMVEVCVTt1fp(), DecodeMVEVMOVDRegtoQ(), and DecodeMVEVMOVQtoDReg().

◆ DecodeMQQPRRegisterClass()

◆ DecodeMQQQQPRRegisterClass()

◆ DecodeMSRMask()

◆ DecodeMVE_MEM_1_pre()

◆ DecodeMVE_MEM_2_pre()

◆ DecodeMVE_MEM_3_pre()

◆ DecodeMVE_MEM_pre()

◆ DecodeMveAddrModeQ()

◆ DecodeMveAddrModeRQ()

◆ DecodeMVEModImmInstruction()

◆ DecodeMVEOverlappingLongShift()

Definition at line 5889 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodePredicateOperand(), DecoderGPRRegisterClass(), DecodetGPREvenRegisterClass(), DecodetGPROddRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm_unreachable, llvm::MCInst::setOpcode(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

◆ DecodeMVEPairVectorIndexOperand()

◆ DecodeMVEVADCInstruction()

◆ DecodeMVEVCMP()

template<bool scalar, OperandDecoder predicate_decoder>

◆ DecodeMveVCTP()

◆ DecodeMVEVCVTt1fp()

◆ DecodeMVEVMOVDRegtoQ()

◆ DecodeMVEVMOVQtoDReg()

◆ DecodeMVEVPNOT()

◆ DecodeNEONComplexLane64Instruction()

◆ DecodePostIdxReg()

◆ DecodePowerTwoOperand()

◆ DecodePredicateOperand() [1/2]

◆ DecodePredicateOperand() [2/2]

Definition at line 601 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARMCC::AL, Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, llvm::MCInstrInfo::get(), llvm::MCInst::getOpcode(), llvm::MCInstrDesc::isPredicable(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

Referenced by DecodeAddrMode2IdxInstruction(), DecodeAddrMode3Instruction(), DecodeArmMOVTWInstruction(), DecodeBranchImmInstruction(), DecodeCopMemInstruction(), DecodeDoubleRegLoad(), DecodeDoubleRegStore(), DecodeForVMRSandVMSR(), DecodeHINTInstruction(), DecodeLazyLoadStoreMul(), DecodeLDR(), DecodeLDRPreImm(), DecodeLDRPreReg(), DecodeLOLoop(), DecodeMemMultipleWritebackInstruction(), DecodeMVEOverlappingLongShift(), DecodeMVEVMOVDRegtoQ(), DecodeMVEVMOVQtoDReg(), DecodeQADDInstruction(), DecodeSMLAInstruction(), DecodeSTRPreImm(), DecodeSTRPreReg(), DecodeSwap(), DecodeT2AddSubSPImm(), DecodeT2Adr(), DecodeT2BInstruction(), DecodeT2CPSInstruction(), DecodeT2HintSpaceInstruction(), DecodeT2LDRDPreInstruction(), DecodeT2LdStPre(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodeT2LoadT(), DecodeT2MOVTWInstruction(), DecodeT2STRDPreInstruction(), DecodeTBLInstruction(), DecodeThumb2BCCInstruction(), DecodeThumbAddSpecialReg(), DecodeThumbAddSPImm(), DecodeThumbAddSPReg(), DecodeThumbTableBranch(), DecodeTSBInstruction(), DecodeTSTInstruction(), DecodeVCVTD(), DecodeVCVTQ(), DecodeVLD1DupInstruction(), DecodeVLD1LN(), DecodeVLD2DupInstruction(), DecodeVLD2LN(), DecodeVLD3DupInstruction(), DecodeVLD3LN(), DecodeVLD4DupInstruction(), DecodeVLD4LN(), DecodeVLDInstruction(), DecodeVMOVModImmInstruction(), DecodeVMOVRRS(), DecodeVMOVSRR(), DecodeVSHLMaxInstruction(), DecodeVST1LN(), DecodeVST2LN(), DecodeVST3LN(), DecodeVST4LN(), and DecodeVSTInstruction().

◆ DecodePredNoALOperand()

◆ DecodeQADDInstruction()

◆ DecodeQPRRegisterClass()

◆ DecodeRegListOperand()

◆ DecodeRestrictedFPPredicateOperand()

◆ DecodeRestrictedIPredicateOperand()

◆ DecodeRestrictedSPredicateOperand()

◆ DecodeRestrictedUPredicateOperand()

◆ DecodeRFEInstruction()

◆ DecoderForMRRC2AndMCRR2()

◆ DecoderGPRRegisterClass()

Definition at line 397 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

Referenced by DecodeLOLoop(), DecodeMVE_MEM_2_pre(), DecodeMVEOverlappingLongShift(), DecodeMveVCTP(), DecodeSORegImmOperand(), DecodeT2AddrModeImm7(), DecodeT2AddrModeSOReg(), DecodeT2Adr(), DecodeT2LDRDPreInstruction(), DecodeT2LoadT(), DecodeT2MOVTWInstruction(), DecodeT2STRDPreInstruction(), and DecodeThumbTableBranch().

◆ DecodeSETPANInstruction()

◆ DecodeShiftRight16Imm()

◆ DecodeShiftRight32Imm()

◆ DecodeShiftRight64Imm()

◆ DecodeShiftRight8Imm()

◆ DecodeSMLAInstruction()

◆ DecodeSORegImmOperand()

Definition at line 696 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARM_AM::asr, Check, llvm::MCOperand::createImm(), DecoderGPRRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::ARM_AM::ror, llvm::ARM_AM::rrx, and llvm::MCDisassembler::Success.

◆ DecodeSORegMemOperand()

Definition at line 1217 of file ARMDisassembler.cpp.

References llvm::ARM_AM::add, llvm::MCInst::addOperand(), llvm::ARM_AM::asr, Check, llvm::MCOperand::createImm(), DecodeGPRRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::ARM_AM::getAM2Opc(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::ARM_AM::ror, llvm::ARM_AM::rrx, llvm::ARM_AM::sub, and llvm::MCDisassembler::Success.

Referenced by DecodeLDRPreReg(), and DecodeSTRPreReg().

◆ DecodeSORegRegOperand()

Definition at line 734 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARM_AM::asr, Check, llvm::MCOperand::createImm(), DecodeGPRnopcRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::ARM_AM::ror, and llvm::MCDisassembler::Success.

◆ DecodeSPR_8RegisterClass()

◆ DecodeSPRRegisterClass()

◆ DecodeSPRRegListOperand()

◆ DecodeSTRPreImm()

◆ DecodeSTRPreReg()

◆ DecodeSwap()

◆ DecodeT2AddrModeImm0_1020s4()

◆ DecodeT2AddrModeImm12()

◆ DecodeT2AddrModeImm7()

template<int shift, int WriteBack>

◆ DecodeT2AddrModeImm7s4()

◆ DecodeT2AddrModeImm8()

◆ DecodeT2AddrModeImm8s4()

◆ DecodeT2AddrModeSOReg()

◆ DecodeT2AddSubSPImm()

Definition at line 6047 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeCCOutOperand(), DecodeGPRspRegisterClass(), DecodePredicateOperand(), DecodeT2SOImm(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeT2Adr()

◆ DecodeT2BInstruction()

◆ DecodeT2BROperand()

◆ DecodeT2CPSInstruction()

◆ DecodeT2HintSpaceInstruction()

◆ DecodeT2Imm7()

◆ DecodeT2Imm7S4()

◆ DecodeT2Imm8()

◆ DecodeT2Imm8S4()

◆ DecodeT2LDRDPreInstruction()

◆ DecodeT2LdStPre()

Definition at line 3694 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), DecodePredicateOperand(), DecodeT2AddrModeImm8(), DecodeT2LoadLabel(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), load, llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeT2LoadImm12()

Definition at line 3444 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), DecodePredicateOperand(), DecodeT2AddrModeImm12(), DecodeT2LoadLabel(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeT2LoadImm8()

Definition at line 3331 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), DecodePredicateOperand(), DecodeT2AddrModeImm8(), DecodeT2LoadLabel(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeT2LoadLabel()

Definition at line 3132 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

Referenced by DecodeT2LdStPre(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadShift(), and DecodeT2LoadT().

◆ DecodeT2LoadShift()

Definition at line 3187 of file ARMDisassembler.cpp.

References Check, DecodeGPRRegisterClass(), DecodePredicateOperand(), DecodeT2AddrModeSOReg(), DecodeT2LoadLabel(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeT2LoadT()

◆ DecodeT2MOVTWInstruction()

◆ DecodeT2ShifterImmOperand()

◆ DecodeT2SOImm()

◆ DecodeT2STRDPreInstruction()

◆ DecodeTAddrModeImm7()

◆ DecodeTBLInstruction()

◆ DecodetcGPRRegisterClass()

◆ DecodetGPREvenRegisterClass()

◆ DecodetGPROddRegisterClass()

◆ DecodetGPRRegisterClass()

◆ DecodeThumb2BCCInstruction()

◆ DecodeThumbAddrModeIS()

◆ DecodeThumbAddrModePC()

◆ DecodeThumbAddrModeRR()

◆ DecodeThumbAddrModeSP()

◆ DecodeThumbAddSpecialReg()

◆ DecodeThumbAddSPImm()

◆ DecodeThumbAddSPReg()

◆ DecodeThumbBCCTargetOperand()

◆ DecodeThumbBLTargetOperand()

◆ DecodeThumbBLXOffset()

◆ DecodeThumbBROperand()

◆ DecodeThumbCmpBROperand()

◆ DecodeThumbCPS()

◆ DecodeThumbTableBranch()

◆ DecodeTSBInstruction()

◆ DecodeTSTInstruction()

◆ DecodeVCVTD()

Definition at line 5096 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeDPRRegisterClass(), DecodePredicateOperand(), DecodeVMOVModImmInstruction(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCDisassembler::getSubtargetInfo(), op, llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeVCVTImmOperand()

◆ DecodeVCVTQ()

Definition at line 5156 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodePredicateOperand(), DecodeQPRRegisterClass(), DecodeVMOVModImmInstruction(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCDisassembler::getSubtargetInfo(), op, llvm::MCInst::setOpcode(), and llvm::MCDisassembler::Success.

◆ DecodeVLD1DupInstruction()

Definition at line 2622 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeDPairRegisterClass(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD1LN()

Definition at line 4320 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD2DupInstruction()

Definition at line 2671 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeDPairRegisterClass(), DecodeDPairSpacedRegisterClass(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD2LN()

Definition at line 4454 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD3DupInstruction()

◆ DecodeVLD3LN()

Definition at line 4586 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD4DupInstruction()

Definition at line 2758 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLD4LN()

Definition at line 4721 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVLDInstruction()

Definition at line 2017 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeAddrMode6Operand(), DecodeDPairRegisterClass(), DecodeDPairSpacedRegisterClass(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), and llvm::MCDisassembler::Success.

Referenced by DecodeVLDST1Instruction(), DecodeVLDST2Instruction(), DecodeVLDST3Instruction(), and DecodeVLDST4Instruction().

◆ DecodeVLDST1Instruction()

◆ DecodeVLDST2Instruction()

◆ DecodeVLDST3Instruction()

◆ DecodeVLDST4Instruction()

◆ DecodeVMOVModImmInstruction()

Definition at line 2812 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), DecodeDPRRegisterClass(), DecodePredicateOperand(), DecodeQPRRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), and llvm::MCDisassembler::Success.

Referenced by DecodeVCVTD(), and DecodeVCVTQ().

◆ DecodeVMOVRRS()

◆ DecodeVMOVSRR()

◆ DecodeVpredNOperand()

◆ DecodeVpredROperand()

Definition at line 672 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), D(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::ARMVCC::None, llvm::MCDisassembler::Success, and llvm::MCOI::TIED_TO.

Referenced by DecodeMVEModImmInstruction(), DecodeMVEVADCInstruction(), and DecodeMVEVCVTt1fp().

◆ DecodeVPTMaskOperand()

◆ DecodeVSCCLRM()

Definition at line 5532 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARMCC::AL, Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeDPRRegListOperand(), DecodeSPRRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

◆ DecodeVSHLMaxInstruction()

◆ DecodeVST1LN()

Definition at line 4388 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVST2LN()

Definition at line 4522 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVST3LN()

Definition at line 4657 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVST4LN()

Definition at line 4803 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::size(), and llvm::MCDisassembler::Success.

◆ DecodeVSTInstruction()

Definition at line 2295 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeAddrMode6Operand(), DecodeDPairRegisterClass(), DecodeDPairSpacedRegisterClass(), DecodeDPRRegisterClass(), DecodeGPRRegisterClass(), DecodePredicateOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), and llvm::MCDisassembler::Success.

Referenced by DecodeVLDST1Instruction(), DecodeVLDST2Instruction(), DecodeVLDST3Instruction(), and DecodeVLDST4Instruction().

◆ DecodeVSTRVLDR_SYSREG()

Definition at line 5718 of file ARMDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::ARMCC::AL, Check, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeGPRnopcRegisterClass(), DecodeT2AddrModeImm7s4(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), FixedRegForVSTRVLDR_SYSREG(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCInst::getOpcode(), llvm::MCDisassembler::getSubtargetInfo(), and llvm::MCDisassembler::Success.

◆ FixedRegForVSTRVLDR_SYSREG()

◆ LLVMInitializeARMDisassembler()

◆ PermitsD32()

◆ tryAddingPcLoadReferenceComment()

tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load instruction with the base register that is the Pc.

These can often be values in a literal pool near the Address of the instruction. The Address of the instruction and its immediate Value are used as a possible literal pool entry. The SymbolLookUp call back will return the name of a symbol referenced by the literal pool's entry if the referenced address is that of a symbol. Or it will return a pointer to a literal 'C' string if the referenced address of the literal pool's entry is an address into a section with 'C' string literals.

Definition at line 195 of file ARMDisassembler.cpp.

References llvm::MCDisassembler::tryAddingPcLoadReferenceComment().

Referenced by DecodeAddrModeImm12Operand(), and DecodeThumbAddrModePC().

◆ tryAddingSymbolicOperand()

tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCInst.

The immediate Value has had any PC adjustment made by the caller. If the instruction is a branch instruction then isBranch is true, else false. If the getOpInfo() function was set as part of the setupForSymbolicDisassembly() call then that function is called to get any symbolic information at the Address for this instruction. If that returns non-zero then the symbolic information it returns is used to create an MCExpr and that is added as an operand to the MCInst. If getOpInfo() returns zero and isBranch is true then a symbol look up for Value is done and if a symbol is found an MCExpr is created with that, else an MCExpr with Value is created. This function returns true if it adds an operand to the MCInst and false otherwise.

Definition at line 176 of file ARMDisassembler.cpp.

References isBranch(), MI, and llvm::MCDisassembler::tryAddingSymbolicOperand().

Referenced by DecodeArmMOVTWInstruction(), DecodeBFAfterTargetOperand(), DecodeBFLabelOperand(), decodeBranch(), DecodeBranchImmInstruction(), DecodeT2BInstruction(), DecodeT2BROperand(), DecodeT2MOVTWInstruction(), DecodeThumbBCCTargetOperand(), DecodeThumbBLTargetOperand(), DecodeThumbBLXOffset(), DecodeThumbBROperand(), and DecodeThumbCmpBROperand().

◆ CLRMGPRDecoderTable

Initial value:

= {

ARM::R0, ARM::R1, ARM::R2, ARM::R3,

ARM::R4, ARM::R5, ARM::R6, ARM::R7,

ARM::R8, ARM::R9, ARM::R10, ARM::R11,

ARM::R12, 0, ARM::LR, ARM::APSR

}

Definition at line 209 of file ARMDisassembler.cpp.

Referenced by DecodeCLRMGPRRegisterClass().

◆ DPairDecoderTable

Initial value:

= {

ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,

ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,

ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,

ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,

ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,

ARM::Q15

}

Definition at line 514 of file ARMDisassembler.cpp.

Referenced by DecodeDPairRegisterClass().

◆ DPairSpacedDecoderTable

Initial value:

= {

ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,

ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,

ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,

ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,

ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,

ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,

ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,

ARM::D28_D30, ARM::D29_D31

}

Definition at line 534 of file ARMDisassembler.cpp.

Referenced by DecodeDPairSpacedRegisterClass().

◆ DPRDecoderTable

Initial value:

= {

ARM::D0, ARM::D1, ARM::D2, ARM::D3,

ARM::D4, ARM::D5, ARM::D6, ARM::D7,

ARM::D8, ARM::D9, ARM::D10, ARM::D11,

ARM::D12, ARM::D13, ARM::D14, ARM::D15,

ARM::D16, ARM::D17, ARM::D18, ARM::D19,

ARM::D20, ARM::D21, ARM::D22, ARM::D23,

ARM::D24, ARM::D25, ARM::D26, ARM::D27,

ARM::D28, ARM::D29, ARM::D30, ARM::D31

}

@ D16

Only 16 D registers.

Definition at line 440 of file ARMDisassembler.cpp.

Referenced by DecodeDPRRegisterClass().

◆ GPRDecoderTable

Initial value:

= {

ARM::R0, ARM::R1, ARM::R2, ARM::R3,

ARM::R4, ARM::R5, ARM::R6, ARM::R7,

ARM::R8, ARM::R9, ARM::R10, ARM::R11,

ARM::R12, ARM::SP, ARM::LR, ARM::PC

}

Definition at line 202 of file ARMDisassembler.cpp.

Referenced by DecodeGPR8RegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRspRegisterClass(), DecodeGPRwithAPSR_NZCVnospRegisterClass(), DecodeLD8loRegisterClass(), DecodeLD8RegisterClass(), decodeLoadStore(), decodeMemoryOpValue(), DecodemGPRRegisterClass(), DecodeRegSeqOperand(), decodeRiMemoryValue(), decodeRrMemoryValue(), DecodesGPRRegisterClass(), decodeSplsValue(), DecodetGPREvenRegisterClass(), and DecodetGPROddRegisterClass().

◆ GPRPairDecoderTable

Initial value:

= {

ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,

ARM::R8_R9, ARM::R10_R11, ARM::R12_SP

}

Definition at line 318 of file ARMDisassembler.cpp.

Referenced by DecodeDREGSRegisterClass(), DecodeGPRPairnospRegisterClass(), DecodeGPRPairRegisterClass(), DecodeGPRPairRegisterClass(), and DecodeIWREGSRegisterClass().

◆ QPRDecoderTable

Initial value:

= {

ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,

ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,

ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,

ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15

}

Definition at line 495 of file ARMDisassembler.cpp.

Referenced by DecodeMQPRRegisterClass(), and DecodeQPRRegisterClass().

◆ QQPRDecoderTable

◆ QQQQPRDecoderTable

◆ SPRDecoderTable

Initial value:

= {

ARM::S0, ARM::S1, ARM::S2, ARM::S3,

ARM::S4, ARM::S5, ARM::S6, ARM::S7,

ARM::S8, ARM::S9, ARM::S10, ARM::S11,

ARM::S12, ARM::S13, ARM::S14, ARM::S15,

ARM::S16, ARM::S17, ARM::S18, ARM::S19,

ARM::S20, ARM::S21, ARM::S22, ARM::S23,

ARM::S24, ARM::S25, ARM::S26, ARM::S27,

ARM::S28, ARM::S29, ARM::S30, ARM::S31

}

Definition at line 412 of file ARMDisassembler.cpp.

Referenced by DecodeSPRRegisterClass().