MachineScheduler.cpp File Reference (original) (raw)

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Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Functions
	STATISTIC (NumClustered, "Number of load/store pairs clustered")

cl::opt< MISched::Direction >	llvm::PreRADirection ("misched-prera-direction", cl::Hidden, cl::desc("Pre reg-alloc list scheduling direction"), cl::init(MISched::Unspecified), cl::values(clEnumValN(MISched::TopDown, "topdown", "Force top-down pre reg-alloc list scheduling"), clEnumValN(MISched::BottomUp, "bottomup", "Force bottom-up pre reg-alloc list scheduling"), clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional pre reg-alloc list scheduling")))

cl::opt< bool >	llvm::VerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))

cl::opt< bool >	llvm::ViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))

cl::opt< bool >	llvm::PrintDAGs ("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs"))

	INITIALIZE_PASS_BEGIN (MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler

	INITIALIZE_PASS_BEGIN (PostMachineScheduler, "postmisched", "PostRA Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(PostMachineScheduler

static ScheduleDAGInstrs *	useDefaultMachineSched (MachineSchedContext *C)
	A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.

static MachineBasicBlock::const_iterator	priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg)
	Decrement this iterator until reaching the top or a non-debug instr.

static MachineBasicBlock::iterator	priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg)
	Non-const version.

static MachineBasicBlock::const_iterator	nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End)
	If this iterator is a debug value, increment until reaching the End or a non-debug instruction.

static MachineBasicBlock::iterator	nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End)
	Non-const version.

static bool	isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock MBB, MachineFunction MF, const TargetInstrInfo *TII)
	Return true of the given instruction should not be included in a scheduling region.

static void	getSchedRegions (MachineBasicBlock *MBB, MBBRegionsVector &Regions, bool RegionsTopDown)

std::unique_ptr< ScheduleDAGMutation >	llvm::createLoadClusterDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI, bool ReorderWhileClustering=false)
	If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.

std::unique_ptr< ScheduleDAGMutation >	llvm::createStoreClusterDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI, bool ReorderWhileClustering=false)
	If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.

std::unique_ptr< ScheduleDAGMutation >	llvm::createCopyConstrainDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI)

static bool	checkResourceLimit (unsigned LFactor, unsigned Count, unsigned Latency, bool AfterSchedNode)
	Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited.

static unsigned	computeRemLatency (SchedBoundary &CurrZone)
	Compute remaining latency.

bool	llvm::tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
	Return true if this heuristic determines order.

bool	llvm::tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

bool	llvm::tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)

static void	tracePick (GenericSchedulerBase::CandReason Reason, bool IsTop)

static void	tracePick (const GenericSchedulerBase::SchedCandidate &Cand)

bool	llvm::tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)

unsigned	llvm::getWeakLeft (const SUnit *SU, bool isTop)

int	llvm::biasPhysReg (const SUnit *SU, bool isTop)
	Minimize physical register live ranges.

static ScheduleDAGInstrs *	createConvergingSched (MachineSchedContext *C)

static ScheduleDAGInstrs *	createILPMaxScheduler (MachineSchedContext *C)

static ScheduleDAGInstrs *	createILPMinScheduler (MachineSchedContext *C)

static ScheduleDAGInstrs *	createInstructionShuffler (MachineSchedContext *C)

static bool	sortIntervals (const ResourceSegments::IntervalTy &A, const ResourceSegments::IntervalTy &B)
	Sort predicate for the intervals stored in an instance of ResourceSegments.

Variables
cl::opt< MISched::Direction >	llvm::PostRADirection ("misched-postra-direction", cl::Hidden, cl::desc("Post reg-alloc list scheduling direction"), cl::init(MISched::Unspecified), cl::values(clEnumValN(MISched::TopDown, "topdown", "Force top-down post reg-alloc list scheduling"), clEnumValN(MISched::BottomUp, "bottomup", "Force bottom-up post reg-alloc list scheduling"), clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional post reg-alloc list scheduling")))

cl::opt< bool >	llvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout"))

cl::opt< bool >	llvm::MISchedDumpReservedCycles ("misched-dump-reserved-cycles", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary."))

cl::opt< bool >	llvm::MischedDetailResourceBooking ("misched-detail-resource-booking", cl::Hidden, cl::init(false), cl::desc("Show details of invoking getNextResoufceCycle."))

static cl::opt< unsigned >	ViewMISchedCutoff ("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))
	In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them.

static cl::opt< unsigned >	MISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))

static cl::opt< std::string >	SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))

static cl::opt< unsigned >	SchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))

static cl::opt< unsigned >	ReadyListLimit ("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))
	Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists.

static cl::opt< bool >	EnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))

static cl::opt< bool >	EnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))

static cl::opt< bool >	EnableMemOpCluster ("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))

static cl::opt< bool >	ForceFastCluster ("force-fast-cluster", cl::Hidden, cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities"), cl::init(false))

static cl::opt< unsigned >	FastClusterThreshold ("fast-cluster-threshold", cl::Hidden, cl::desc("The threshold for fast cluster"), cl::init(1000))

static cl::opt< bool >	MISchedDumpScheduleTrace ("misched-dump-schedule-trace", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary."))

static cl::opt< unsigned >	HeaderColWidth ("misched-dump-schedule-trace-col-header-width", cl::Hidden, cl::desc("Set width of the columns with " "the resources and schedule units"), cl::init(19))

static cl::opt< unsigned >	ColWidth ("misched-dump-schedule-trace-col-width", cl::Hidden, cl::desc("Set width of the columns showing resource booking."), cl::init(5))

static cl::opt< bool >	MISchedSortResourcesInTrace ("misched-sort-resources-in-trace", cl::Hidden, cl::init(true), cl::desc("Sort the resources printed in the dump trace"))

static cl::opt< unsigned >	MIResourceCutOff ("misched-resource-cutoff", cl::Hidden, cl::desc("Number of intervals to track"), cl::init(10))

static const unsigned	MinSubtreeSize = 8

	DEBUG_TYPE

Machine Instruction	Scheduler

Machine Instruction	false

	postmisched

static cl::opt< MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser< MachineSchedRegistry > >	MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))
	MachineSchedOpt allows command line selection of the scheduler.

static MachineSchedRegistry	DefaultSchedRegistry ("default", "Use the target's default scheduler choice.", useDefaultMachineSched)

static cl::opt< bool >	EnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static cl::opt< bool >	EnablePostRAMachineSched ("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static const char *	scheduleTableLegend = " i: issue\n x: resource booked"

static const unsigned	InvalidCycle = ~0U

static MachineSchedRegistry	GenericSchedRegistry ("converge", "Standard converging scheduler.", createConvergingSched)

static MachineSchedRegistry	ILPMaxRegistry ("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler)

static MachineSchedRegistry	ILPMinRegistry ("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler)

static MachineSchedRegistry	ShufflerRegistry ("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler)

◆ DEBUG_TYPE

#define DEBUG_TYPE "machine-scheduler"

◆ MBBRegionsVector

◆ checkResourceLimit()

◆ computeRemLatency()

◆ createConvergingSched()

◆ createILPMaxScheduler()

◆ createILPMinScheduler()

◆ createInstructionShuffler()

◆ getSchedRegions()

Definition at line 542 of file MachineScheduler.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MachineBasicBlock::begin(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::MachineBasicBlock::end(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), I, isSchedBoundary(), MBB, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ INITIALIZE_PASS_BEGIN() [1/2]

INITIALIZE_PASS_BEGIN	(	MachineScheduler	,
DEBUG_TYPE	,
"Machine Instruction Scheduler"	,
false	,
false
)

◆ INITIALIZE_PASS_BEGIN() [2/2]

INITIALIZE_PASS_BEGIN	(	PostMachineScheduler	,
"postmisched"	,
"PostRA Machine Instruction Scheduler"	,
false	,
false
)

◆ isSchedBoundary()

Return true of the given instruction should not be included in a scheduling region.

MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.

Definition at line 513 of file MachineScheduler.cpp.

References llvm::HexagonInstrInfo::isSchedulingBoundary(), MBB, MI, and TII.

Referenced by getSchedRegions().

◆ nextIfDebug() [1/2]

◆ nextIfDebug() [2/2]

◆ priorNonDebug() [1/2]

◆ priorNonDebug() [2/2]

◆ sortIntervals()

Sort predicate for the intervals stored in an instance of ResourceSegments.

Intervals are always disjoint (no intersection for any pairs of intervals), therefore we can sort the totality of the intervals by looking only at the left boundary.

Definition at line 4471 of file MachineScheduler.cpp.

References A, and B.

◆ STATISTIC()

STATISTIC	(	NumClustered	,
"Number of load/store pairs clustered"
)

◆ tracePick() [1/2]

◆ tracePick() [2/2]

◆ useDefaultMachineSched()

A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.

Definition at line 323 of file MachineScheduler.cpp.

◆ ColWidth

cl::opt< unsigned > ColWidth("misched-dump-schedule-trace-col-width", cl::Hidden, cl::desc("Set width of the columns showing resource booking."), cl::init(5)) ( "misched-dump-schedule-trace-col-width" , cl::Hidden , cl::desc("Set width of the columns showing resource booking.") , cl::init(5) )	static

◆ DEBUG_TYPE

◆ DefaultSchedRegistry

◆ EnableCyclicPath

cl::opt< bool > EnableCyclicPath("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true)) ( "misched-cyclicpath" , cl::Hidden , cl::desc("Enable cyclic critical path analysis.") , cl::init(true) )	static

◆ EnableMachineSched

cl::opt< bool > EnableMachineSched("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden) ( "enable-misched" , cl::desc("Enable the machine instruction scheduling pass.") , cl::init(true) , cl::Hidden )	static

◆ EnableMemOpCluster

cl::opt< bool > EnableMemOpCluster("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true)) ( "misched-cluster" , cl::Hidden , cl::desc("Enable memop clustering.") , cl::init(true) )	static

◆ EnablePostRAMachineSched

cl::opt< bool > EnablePostRAMachineSched("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden) ( "enable-post-misched" , cl::desc("Enable the post-ra machine instruction scheduling pass.") , cl::init(true) , cl::Hidden )	static

◆ EnableRegPressure

cl::opt< bool > EnableRegPressure("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true)) ( "misched-regpressure" , cl::Hidden , cl::desc("Enable register pressure scheduling.") , cl::init(true) )	static

◆ false

◆ FastClusterThreshold

cl::opt< unsigned > FastClusterThreshold("fast-cluster-threshold", cl::Hidden, cl::desc("The threshold for fast cluster"), cl::init(1000)) ( "fast-cluster-threshold" , cl::Hidden , cl::desc("The threshold for fast cluster") , cl::init(1000) )	static

◆ ForceFastCluster

cl::opt< bool > ForceFastCluster("force-fast-cluster", cl::Hidden, cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities"), cl::init(false)) ( "force-fast-cluster" , cl::Hidden , cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities") , cl::init(false) )	static

◆ GenericSchedRegistry

◆ HeaderColWidth

cl::opt< unsigned > HeaderColWidth("misched-dump-schedule-trace-col-header-width", cl::Hidden, cl::desc("Set width of the columns with " "the resources and schedule units"), cl::init(19)) ( "misched-dump-schedule-trace-col-header-width" , cl::Hidden , cl::desc("Set width of the columns with " "the resources and schedule units") , cl::init(19) )	static

◆ ILPMaxRegistry

◆ ILPMinRegistry

◆ InvalidCycle

◆ MachineSchedOpt

MachineSchedOpt allows command line selection of the scheduler.

◆ MinSubtreeSize

◆ MIResourceCutOff

cl::opt< unsigned > MIResourceCutOff("misched-resource-cutoff", cl::Hidden, cl::desc("Number of intervals to track"), cl::init(10)) ( "misched-resource-cutoff" , cl::Hidden , cl::desc("Number of intervals to track") , cl::init(10) )	static

◆ MISchedCutoff

cl::opt< unsigned > MISchedCutoff("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U)) ( "misched-cutoff" , cl::Hidden , cl::desc("Stop scheduling after N instructions") , cl::init(~0U) )	static

◆ MISchedDumpScheduleTrace

cl::opt< bool > MISchedDumpScheduleTrace("misched-dump-schedule-trace", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary.")) ( "misched-dump-schedule-trace" , cl::Hidden , cl::init(false) , cl::desc("Dump resource usage at schedule boundary.") )	static

◆ MISchedSortResourcesInTrace

cl::opt< bool > MISchedSortResourcesInTrace("misched-sort-resources-in-trace", cl::Hidden, cl::init(true), cl::desc("Sort the resources printed in the dump trace")) ( "misched-sort-resources-in-trace" , cl::Hidden , cl::init(true) , cl::desc("Sort the resources printed in the dump trace") )	static

◆ postmisched

◆ ReadyListLimit

cl::opt< unsigned > ReadyListLimit("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256)) ( "misched-limit" , cl::Hidden , cl::desc("Limit ready list to N instructions") , cl::init(256) )	static

◆ SchedOnlyBlock

◆ SchedOnlyFunc

cl::opt< std::string > SchedOnlyFunc("misched-only-func", cl::Hidden, cl::desc("Only schedule this function")) ( "misched-only-func" , cl::Hidden , cl::desc("Only schedule this function") )	static

◆ Scheduler

◆ scheduleTableLegend

const char* scheduleTableLegend = " i: issue\n x: resource booked"	static

◆ ShufflerRegistry

◆ ViewMISchedCutoff

cl::opt< unsigned > ViewMISchedCutoff("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff")) ( "view-misched-cutoff" , cl::Hidden , cl::desc("Hide nodes with more predecessor/successor than cutoff") )	static