MipsSEISelLowering.cpp Source File (original) (raw)

36#include "llvm/IR/IntrinsicsMips.h"

43#include

44#include

45#include

46#include

47#include

49using namespace llvm;

51#define DEBUG_TYPE "mips-isel"

58 cl::desc("Expand double precision loads and "

59 "stores to their single precision "

60 "counterparts"));

79 }

80 }

81 }

86 for (const auto &VecTy : VecTys) {

98 }

102

106 }

107 }

108

111

113 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);

114 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);

115 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);

116 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);

120

121

158

160 }

161

164

165

169 else

171 }

172 }

173

178

183

191 }

192

195

202 } else {

205 }

206

208

212

216 }

217

221 }

222

224

225

231

232

233

240

241

242

246

250

255

257

258

263

268 }

269

271

272

278

279

280

287

288

289

293 }

294

296}

297

302}

303

306 if (VT == MVT::Untyped)

307 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;

308

310}

311

312

316

317

320

328

350

351 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {

356 }

357

364}

365

366

370

371

374

381

382 if (Ty != MVT::v8f16) {

394

402 }

403}

404

408

409 EVT ResTy = Op->getValueType(0);

411

412

413

414

417 Op->getOperand(2));

418}

419

423

425

426

427

428

431 return true;

433 return false;

434 }

435

436 switch (SVT) {

437 case MVT::i64:

438 case MVT::i32:

441 return true;

442 default:

443 return false;

444 }

445}

446

449 switch(Op.getOpcode()) {

450 case ISD::LOAD: return lowerLOAD(Op, DAG);

459 DAG);

468 }

469

471}

472

473

474

475

476

477

478

479

483 if (!Subtarget.hasMSA())

485

486 SDValue Op0 = N->getOperand(0);

487 SDValue Op1 = N->getOperand(1);

488 unsigned Op0Opcode = Op0->getOpcode();

489

490

491

492

493

496 ConstantSDNode *Mask = dyn_cast(Op1);

497

498 if (!Mask)

500

501 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();

502

503 if (Log2IfPositive <= 0)

504 return SDValue();

505

507 EVT ExtendTy = cast(Op0Op2)->getVT();

508 unsigned ExtendTySize = ExtendTy.getSizeInBits();

509 unsigned Log2 = Log2IfPositive;

510

512 Log2 == ExtendTySize) {

517 }

518 }

519

521}

522

523

524

525

526

527

528

529

530

531

534

536 return false;

537

538 APInt SplatValue, SplatUndef;

539 unsigned SplatBitSize;

540 bool HasAnyUndefs;

541

542 if ( Node ->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,

543 8, !IsLittleEndian))

544 return false;

545

546 Imm = SplatValue;

547

548 return true;

549}

550

551

553

554

556 N = N->getOperand(0);

557

559

560 if (!BVN)

561 return false;

562

563 APInt SplatValue, SplatUndef;

564 unsigned SplatBitSize;

565 bool HasAnyUndefs;

566

567

568

569 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))

571

572 return false;

573}

574

575

578 return false;

579

581 return N->getOperand(1) == OfNode;

582

584 return N->getOperand(0) == OfNode;

585

586 return false;

587}

588

589

590

591

592

593

594

598 if (!Subtarget.hasMSA())

600

601 EVT Ty = N->getValueType(0);

602

605

606 SDValue Op0 = N->getOperand(0);

607 SDValue Op1 = N->getOperand(1);

608

614 bool IsLittleEndian = !Subtarget.isLittle();

615

617 bool IsConstantMask = false;

618 APInt Mask, InvMask;

619

620

621

622

623

624 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {

625 Cond = Op0Op0;

626 IfSet = Op0Op1;

627

628 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&

629 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

630 IfClr = Op1Op1;

631 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&

632 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

633 IfClr = Op1Op0;

634

635 IsConstantMask = true;

636 }

637

638

639

640

641 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {

642 Cond = Op0Op1;

643 IfSet = Op0Op0;

644

645 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&

646 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

647 IfClr = Op1Op1;

648 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&

649 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

650 IfClr = Op1Op0;

651

652 IsConstantMask = true;

653 }

654

655

656

657

660 Cond = Op1Op0;

661 IfSet = Op1Op1;

662 IfClr = Op0Op1;

664 Cond = Op1Op0;

665 IfSet = Op1Op1;

666 IfClr = Op0Op0;

668 Cond = Op1Op1;

669 IfSet = Op1Op0;

670 IfClr = Op0Op1;

672 Cond = Op1Op1;

673 IfSet = Op1Op0;

674 IfClr = Op0Op0;

676 Cond = Op0Op0;

677 IfSet = Op0Op1;

678 IfClr = Op1Op1;

680 Cond = Op0Op0;

681 IfSet = Op0Op1;

682 IfClr = Op1Op0;

684 Cond = Op0Op1;

685 IfSet = Op0Op0;

686 IfClr = Op1Op1;

688 Cond = Op0Op1;

689 IfSet = Op0Op0;

690 IfClr = Op1Op0;

691 }

692 }

693

694

697

699

700

701 if (IsConstantMask) {

702 if (Mask.isAllOnes())

703 return IfSet;

704 else if (Mask == 0)

705 return IfClr;

706 }

707

708

710 }

711

713}

714

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

744

746 unsigned Steps = 0;

747 unsigned BitWidth = C.getBitWidth();

748

749 while (!WorkStack.empty()) {

751

752 if (Val == 0 || Val == 1)

753 continue;

754

756 return false;

757

759 ++Steps;

760 continue;

761 }

762

766 if ((Val - Floor).ule(Ceil - Val)) {

768 WorkStack.push_back(Val - Floor);

769 } else {

772 }

773

774 ++Steps;

775 }

776

777

778

779

780

784 Steps *= (VT.getSizeInBits() != RegisterSize) * 3;

785 if (Steps > 27)

786 return false;

787

788 return true;

789}

790

793

794 if (C == 0)

796

797

798 if (C == 1)

799 return X;

800

801

802 if (C.isPowerOf2())

805

806 unsigned BitWidth = C.getBitWidth();

810

811

812

813

814 if ((C - Floor).ule(Ceil - C)) {

818 }

819

820

821

825}

826

831 EVT VT = N->getValueType(0);

832

833 if (ConstantSDNode *C = dyn_cast(N->getOperand(1)))

835 C->getAPIntValue(), VT, DAG, Subtarget))

838 DAG);

839

841}

842

846

847 APInt SplatValue, SplatUndef;

848 unsigned SplatBitSize;

849 bool HasAnyUndefs;

851 BuildVectorSDNode *BV = dyn_cast(N->getOperand(1));

852

853 if (!Subtarget.hasDSP())

855

856 if (!BV ||

857 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,

858 EltSize, !Subtarget.isLittle()) ||

859 (SplatBitSize != EltSize) ||

862

864 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),

866}

867

871 EVT Ty = N->getValueType(0);

872

873 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))

875

877}

878

879

880

881

882

883

884

885

886

887

888

889

890

894 EVT Ty = N->getValueType(0);

895

896 if (Subtarget.hasMSA()) {

897 SDValue Op0 = N->getOperand(0);

898 SDValue Op1 = N->getOperand(1);

899

900

901

902

903

906 ConstantSDNode *ShAmount = dyn_cast(Op1);

907

908 if (!ShAmount)

910

914

915 EVT ExtendTy = cast(Op0Op0->getOperand(2))->getVT();

917

918 if (TotalBits == 32 ||

920 TotalBits <= 32)) {

926 }

927 }

928 }

929

930 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))

932

934}

935

936

940 EVT Ty = N->getValueType(0);

941

942 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))

944

946}

947

949 bool IsV216 = (Ty == MVT::v2i16);

950

951 switch (CC) {

962 default: return false;

963 }

964}

965

967 EVT Ty = N->getValueType(0);

968

969 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))

971

972 if ( isLegalDSPCondCode (Ty, cast(N->getOperand(2))->get()))

974

976 N->getOperand(1), N->getOperand(2));

977}

978

980 EVT Ty = N->getValueType(0);

981

982 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {

983 SDValue SetCC = N->getOperand(0);

984

987

990 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));

991 }

992

994}

995

998 EVT Ty = N->getValueType(0);

999

1001

1002

1003

1004 SDValue Op0 = N->getOperand(0);

1005 SDValue Op1 = N->getOperand(1);

1007

1009 NotOp = Op1;

1011 NotOp = Op0;

1012 else

1014

1018 }

1019

1021}

1022

1027

1028 switch (N->getOpcode()) {

1031 break;

1034 break;

1039 break;

1048 break;

1051 break;

1052 }

1053

1056 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";

1058 return Val;

1059 }

1060

1062}

1063

1067 switch (MI.getOpcode()) {

1068 default:

1070 case Mips::BPOSGE32_PSEUDO:

1071 return emitBPOSGE32(MI, BB);

1072 case Mips::SNZ_B_PSEUDO:

1073 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);

1074 case Mips::SNZ_H_PSEUDO:

1075 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);

1076 case Mips::SNZ_W_PSEUDO:

1077 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);

1078 case Mips::SNZ_D_PSEUDO:

1079 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);

1080 case Mips::SNZ_V_PSEUDO:

1081 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);

1082 case Mips::SZ_B_PSEUDO:

1083 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);

1084 case Mips::SZ_H_PSEUDO:

1085 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);

1086 case Mips::SZ_W_PSEUDO:

1087 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);

1088 case Mips::SZ_D_PSEUDO:

1089 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);

1090 case Mips::SZ_V_PSEUDO:

1091 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);

1092 case Mips::COPY_FW_PSEUDO:

1093 return emitCOPY_FW(MI, BB);

1094 case Mips::COPY_FD_PSEUDO:

1095 return emitCOPY_FD(MI, BB);

1096 case Mips::INSERT_FW_PSEUDO:

1097 return emitINSERT_FW(MI, BB);

1098 case Mips::INSERT_FD_PSEUDO:

1099 return emitINSERT_FD(MI, BB);

1100 case Mips::INSERT_B_VIDX_PSEUDO:

1101 case Mips::INSERT_B_VIDX64_PSEUDO:

1102 return emitINSERT_DF_VIDX(MI, BB, 1, false);

1103 case Mips::INSERT_H_VIDX_PSEUDO:

1104 case Mips::INSERT_H_VIDX64_PSEUDO:

1105 return emitINSERT_DF_VIDX(MI, BB, 2, false);

1106 case Mips::INSERT_W_VIDX_PSEUDO:

1107 case Mips::INSERT_W_VIDX64_PSEUDO:

1108 return emitINSERT_DF_VIDX(MI, BB, 4, false);

1109 case Mips::INSERT_D_VIDX_PSEUDO:

1110 case Mips::INSERT_D_VIDX64_PSEUDO:

1111 return emitINSERT_DF_VIDX(MI, BB, 8, false);

1112 case Mips::INSERT_FW_VIDX_PSEUDO:

1113 case Mips::INSERT_FW_VIDX64_PSEUDO:

1114 return emitINSERT_DF_VIDX(MI, BB, 4, true);

1115 case Mips::INSERT_FD_VIDX_PSEUDO:

1116 case Mips::INSERT_FD_VIDX64_PSEUDO:

1117 return emitINSERT_DF_VIDX(MI, BB, 8, true);

1118 case Mips::FILL_FW_PSEUDO:

1119 return emitFILL_FW(MI, BB);

1120 case Mips::FILL_FD_PSEUDO:

1121 return emitFILL_FD(MI, BB);

1122 case Mips::FEXP2_W_1_PSEUDO:

1123 return emitFEXP2_W_1(MI, BB);

1124 case Mips::FEXP2_D_1_PSEUDO:

1125 return emitFEXP2_D_1(MI, BB);

1126 case Mips::ST_F16:

1127 return emitST_F16_PSEUDO(MI, BB);

1128 case Mips::LD_F16:

1129 return emitLD_F16_PSEUDO(MI, BB);

1130 case Mips::MSA_FP_EXTEND_W_PSEUDO:

1131 return emitFPEXTEND_PSEUDO(MI, BB, false);

1132 case Mips::MSA_FP_ROUND_W_PSEUDO:

1133 return emitFPROUND_PSEUDO(MI, BB, false);

1134 case Mips::MSA_FP_EXTEND_D_PSEUDO:

1135 return emitFPEXTEND_PSEUDO(MI, BB, true);

1136 case Mips::MSA_FP_ROUND_D_PSEUDO:

1137 return emitFPROUND_PSEUDO(MI, BB, true);

1138 }

1139}

1140

1141bool MipsSETargetLowering::isEligibleForTailCallOptimization(

1142 const CCState &CCInfo, unsigned NextStackOffset,

1145 return false;

1146

1147

1149 return false;

1150

1151

1153 return false;

1154

1155

1156

1158}

1159

1160void MipsSETargetLowering::

1162 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,

1163 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,

1164 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,

1168 InternalLinkage, IsCallReloc, CLI, Callee,

1169 Chain);

1170}

1171

1174

1177

1178

1181 EVT PtrVT = Ptr.getValueType();

1182

1183

1186

1187

1192

1195

1197 SDValue Ops[2] = {BP, Hi.getValue(1)};

1199}

1200

1203

1206

1207

1210 EVT PtrVT = Ptr.getValueType();

1215

1218

1219

1222

1223

1228}

1229

1233 MVT Src = Op.getOperand(0).getValueType().getSimpleVT();

1234 MVT Dest = Op.getValueType().getSimpleVT();

1235

1236

1237 if (Src == MVT::i64 && Dest == MVT::f64) {

1239 std::tie(Lo, Hi) =

1240 DAG.SplitScalar(Op.getOperand(0), DL, MVT::i32, MVT::i32);

1242 }

1243

1244

1245 if (Src == MVT::f64 && Dest == MVT::i64) {

1246

1247

1258 }

1259

1260

1262}

1263

1264SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,

1265 bool HasLo, bool HasHi,

1267

1269

1270 EVT Ty = Op.getOperand(0).getValueType();

1273 Op.getOperand(0), Op.getOperand(1));

1275

1276 if (HasLo)

1278 if (HasHi)

1280

1281 if (!HasLo || !HasHi)

1282 return HasLo ? Lo : Hi;

1283

1286}

1287

1290 std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32);

1292}

1293

1298}

1299

1300

1301

1302

1303

1304

1305

1306

1307

1308

1309

1310

1311

1314 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;

1316 unsigned OpNo = 0;

1317

1318

1319 if (HasChainIn)

1321

1322

1324

1325

1326 SDValue Opnd = Op->getOperand(++OpNo), In64;

1327

1330 else

1332

1333

1336

1337

1338 if (In64.getNode())

1340

1341

1343

1344 for (EVT Ty : Op->values())

1345 ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty);

1346

1347

1349 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;

1350

1351 if (!HasChainIn)

1352 return Out;

1353

1357}

1358

1359

1362 SDValue Vec = Op->getOperand(1);

1364 EVT ResTy = Op->getValueType(0);

1366

1369

1370 return Result;

1371}

1372

1374 EVT ResVecTy = Op->getValueType(0);

1375 EVT ViaVecTy = ResVecTy;

1378

1379

1380

1381

1382 SDValue LaneA = Op->getOperand(OpNr);

1384

1385 if (ResVecTy == MVT::v2i64) {

1386

1387

1388 if (isa(LaneA))

1390

1391

1392

1393

1394 else

1395 LaneB = LaneA;

1396 ViaVecTy = MVT::v4i32;

1397 if(BigEndian)

1399 } else

1400 LaneB = LaneA;

1401

1402 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,

1403 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };

1404

1407

1408 if (ViaVecTy != ResVecTy) {

1412 }

1413

1414 return Result;

1415}

1416

1418 bool IsSigned = false) {

1419 auto *CImm = cast(Op->getOperand(ImmOp));

1421 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),

1422 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),

1423 SDLoc(Op), Op->getValueType(0));

1424}

1425

1428 EVT ViaVecTy = VecTy;

1429 SDValue SplatValueA = SplatValue;

1430 SDValue SplatValueB = SplatValue;

1432

1433 if (VecTy == MVT::v2i64) {

1434

1435 ViaVecTy = MVT::v4i32;

1436

1441 }

1442

1443

1444

1445 if (BigEndian)

1446 std::swap(SplatValueA, SplatValueB);

1447

1448 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1449 SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1450 SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1451 SplatValueA, SplatValueB, SplatValueA, SplatValueB };

1452

1455

1456 if (VecTy != ViaVecTy)

1458

1459 return Result;

1460}

1461

1463 unsigned Opc, SDValue Imm,

1464 bool BigEndian) {

1465 EVT VecTy = Op->getValueType(0);

1468

1469

1470

1471 if (VecTy == MVT::v2i64) {

1472 if (ConstantSDNode *CImm = dyn_cast(Imm)) {

1473 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();

1474

1476 MVT::i32);

1478

1479 if (BigEndian)

1480 std::swap(BitImmLoOp, BitImmHiOp);

1481

1485 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));

1486 }

1487 }

1488

1489 if (!Exp2Imm.getNode()) {

1490

1491

1492

1493

1494 if (VecTy == MVT::v2i64)

1496

1498

1500 Exp2Imm);

1501 }

1502

1503 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);

1504}

1505

1508 EVT ResTy = Op->getValueType(0);

1509 SDValue Vec = Op->getOperand(2);

1511 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;

1513 DL, ResEltTy);

1515

1517}

1518

1520 EVT ResTy = Op->getValueType(0);

1524

1526 DAG.getNOT(DL, Bit, ResTy));

1527}

1528

1531 EVT ResTy = Op->getValueType(0);

1533 << Op->getConstantOperandAPInt(2);

1535

1537}

1538

1539SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,

1542 unsigned Intrinsic = Op->getConstantOperandVal(0);

1543 switch (Intrinsic) {

1544 default:

1546 case Intrinsic::mips_shilo:

1548 case Intrinsic::mips_dpau_h_qbl:

1550 case Intrinsic::mips_dpau_h_qbr:

1552 case Intrinsic::mips_dpsu_h_qbl:

1554 case Intrinsic::mips_dpsu_h_qbr:

1556 case Intrinsic::mips_dpa_w_ph:

1558 case Intrinsic::mips_dps_w_ph:

1560 case Intrinsic::mips_dpax_w_ph:

1562 case Intrinsic::mips_dpsx_w_ph:

1564 case Intrinsic::mips_mulsa_w_ph:

1566 case Intrinsic::mips_mult:

1568 case Intrinsic::mips_multu:

1570 case Intrinsic::mips_madd:

1572 case Intrinsic::mips_maddu:

1574 case Intrinsic::mips_msub:

1576 case Intrinsic::mips_msubu:

1578 case Intrinsic::mips_addv_b:

1579 case Intrinsic::mips_addv_h:

1580 case Intrinsic::mips_addv_w:

1581 case Intrinsic::mips_addv_d:

1583 Op->getOperand(2));

1584 case Intrinsic::mips_addvi_b:

1585 case Intrinsic::mips_addvi_h:

1586 case Intrinsic::mips_addvi_w:

1587 case Intrinsic::mips_addvi_d:

1590 case Intrinsic::mips_and_v:

1592 Op->getOperand(2));

1593 case Intrinsic::mips_andi_b:

1596 case Intrinsic::mips_bclr_b:

1597 case Intrinsic::mips_bclr_h:

1598 case Intrinsic::mips_bclr_w:

1599 case Intrinsic::mips_bclr_d:

1601 case Intrinsic::mips_bclri_b:

1602 case Intrinsic::mips_bclri_h:

1603 case Intrinsic::mips_bclri_w:

1604 case Intrinsic::mips_bclri_d:

1606 case Intrinsic::mips_binsli_b:

1607 case Intrinsic::mips_binsli_h:

1608 case Intrinsic::mips_binsli_w:

1609 case Intrinsic::mips_binsli_d: {

1610

1611 EVT VecTy = Op->getValueType(0);

1613 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())

1616 Op->getConstantOperandVal(3) + 1);

1619 Op->getOperand(2), Op->getOperand(1));

1620 }

1621 case Intrinsic::mips_binsri_b:

1622 case Intrinsic::mips_binsri_h:

1623 case Intrinsic::mips_binsri_w:

1624 case Intrinsic::mips_binsri_d: {

1625

1626 EVT VecTy = Op->getValueType(0);

1628 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())

1631 Op->getConstantOperandVal(3) + 1);

1634 Op->getOperand(2), Op->getOperand(1));

1635 }

1636 case Intrinsic::mips_bmnz_v:

1638 Op->getOperand(2), Op->getOperand(1));

1639 case Intrinsic::mips_bmnzi_b:

1642 Op->getOperand(1));

1643 case Intrinsic::mips_bmz_v:

1645 Op->getOperand(1), Op->getOperand(2));

1646 case Intrinsic::mips_bmzi_b:

1649 Op->getOperand(2));

1650 case Intrinsic::mips_bneg_b:

1651 case Intrinsic::mips_bneg_h:

1652 case Intrinsic::mips_bneg_w:

1653 case Intrinsic::mips_bneg_d: {

1654 EVT VecTy = Op->getValueType(0);

1656

1660 }

1661 case Intrinsic::mips_bnegi_b:

1662 case Intrinsic::mips_bnegi_h:

1663 case Intrinsic::mips_bnegi_w:

1664 case Intrinsic::mips_bnegi_d:

1667 case Intrinsic::mips_bnz_b:

1668 case Intrinsic::mips_bnz_h:

1669 case Intrinsic::mips_bnz_w:

1670 case Intrinsic::mips_bnz_d:

1672 Op->getOperand(1));

1673 case Intrinsic::mips_bnz_v:

1675 Op->getOperand(1));

1676 case Intrinsic::mips_bsel_v:

1677

1679 Op->getOperand(1), Op->getOperand(3),

1680 Op->getOperand(2));

1681 case Intrinsic::mips_bseli_b:

1682

1685 Op->getOperand(2));

1686 case Intrinsic::mips_bset_b:

1687 case Intrinsic::mips_bset_h:

1688 case Intrinsic::mips_bset_w:

1689 case Intrinsic::mips_bset_d: {

1690 EVT VecTy = Op->getValueType(0);

1692

1696 }

1697 case Intrinsic::mips_bseti_b:

1698 case Intrinsic::mips_bseti_h:

1699 case Intrinsic::mips_bseti_w:

1700 case Intrinsic::mips_bseti_d:

1703 case Intrinsic::mips_bz_b:

1704 case Intrinsic::mips_bz_h:

1705 case Intrinsic::mips_bz_w:

1706 case Intrinsic::mips_bz_d:

1708 Op->getOperand(1));

1709 case Intrinsic::mips_bz_v:

1711 Op->getOperand(1));

1712 case Intrinsic::mips_ceq_b:

1713 case Intrinsic::mips_ceq_h:

1714 case Intrinsic::mips_ceq_w:

1715 case Intrinsic::mips_ceq_d:

1716 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1718 case Intrinsic::mips_ceqi_b:

1719 case Intrinsic::mips_ceqi_h:

1720 case Intrinsic::mips_ceqi_w:

1721 case Intrinsic::mips_ceqi_d:

1722 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1724 case Intrinsic::mips_cle_s_b:

1725 case Intrinsic::mips_cle_s_h:

1726 case Intrinsic::mips_cle_s_w:

1727 case Intrinsic::mips_cle_s_d:

1728 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1730 case Intrinsic::mips_clei_s_b:

1731 case Intrinsic::mips_clei_s_h:

1732 case Intrinsic::mips_clei_s_w:

1733 case Intrinsic::mips_clei_s_d:

1734 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1736 case Intrinsic::mips_cle_u_b:

1737 case Intrinsic::mips_cle_u_h:

1738 case Intrinsic::mips_cle_u_w:

1739 case Intrinsic::mips_cle_u_d:

1740 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1742 case Intrinsic::mips_clei_u_b:

1743 case Intrinsic::mips_clei_u_h:

1744 case Intrinsic::mips_clei_u_w:

1745 case Intrinsic::mips_clei_u_d:

1746 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1748 case Intrinsic::mips_clt_s_b:

1749 case Intrinsic::mips_clt_s_h:

1750 case Intrinsic::mips_clt_s_w:

1751 case Intrinsic::mips_clt_s_d:

1752 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1754 case Intrinsic::mips_clti_s_b:

1755 case Intrinsic::mips_clti_s_h:

1756 case Intrinsic::mips_clti_s_w:

1757 case Intrinsic::mips_clti_s_d:

1758 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1760 case Intrinsic::mips_clt_u_b:

1761 case Intrinsic::mips_clt_u_h:

1762 case Intrinsic::mips_clt_u_w:

1763 case Intrinsic::mips_clt_u_d:

1764 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1766 case Intrinsic::mips_clti_u_b:

1767 case Intrinsic::mips_clti_u_h:

1768 case Intrinsic::mips_clti_u_w:

1769 case Intrinsic::mips_clti_u_d:

1770 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1772 case Intrinsic::mips_copy_s_b:

1773 case Intrinsic::mips_copy_s_h:

1774 case Intrinsic::mips_copy_s_w:

1776 case Intrinsic::mips_copy_s_d:

1778

1780 else {

1781

1782

1784 Op->getValueType(0), Op->getOperand(1),

1785 Op->getOperand(2));

1786 }

1787 case Intrinsic::mips_copy_u_b:

1788 case Intrinsic::mips_copy_u_h:

1789 case Intrinsic::mips_copy_u_w:

1791 case Intrinsic::mips_copy_u_d:

1793

1795 else {

1796

1797

1798

1799

1800

1802 Op->getValueType(0), Op->getOperand(1),

1803 Op->getOperand(2));

1804 }

1805 case Intrinsic::mips_div_s_b:

1806 case Intrinsic::mips_div_s_h:

1807 case Intrinsic::mips_div_s_w:

1808 case Intrinsic::mips_div_s_d:

1810 Op->getOperand(2));

1811 case Intrinsic::mips_div_u_b:

1812 case Intrinsic::mips_div_u_h:

1813 case Intrinsic::mips_div_u_w:

1814 case Intrinsic::mips_div_u_d:

1816 Op->getOperand(2));

1817 case Intrinsic::mips_fadd_w:

1818 case Intrinsic::mips_fadd_d:

1819

1821 Op->getOperand(2));

1822

1823 case Intrinsic::mips_fceq_w:

1824 case Intrinsic::mips_fceq_d:

1825 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1827 case Intrinsic::mips_fcle_w:

1828 case Intrinsic::mips_fcle_d:

1829 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1831 case Intrinsic::mips_fclt_w:

1832 case Intrinsic::mips_fclt_d:

1833 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1835 case Intrinsic::mips_fcne_w:

1836 case Intrinsic::mips_fcne_d:

1837 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1839 case Intrinsic::mips_fcor_w:

1840 case Intrinsic::mips_fcor_d:

1841 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1843 case Intrinsic::mips_fcueq_w:

1844 case Intrinsic::mips_fcueq_d:

1845 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1847 case Intrinsic::mips_fcule_w:

1848 case Intrinsic::mips_fcule_d:

1849 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1851 case Intrinsic::mips_fcult_w:

1852 case Intrinsic::mips_fcult_d:

1853 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1855 case Intrinsic::mips_fcun_w:

1856 case Intrinsic::mips_fcun_d:

1857 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1859 case Intrinsic::mips_fcune_w:

1860 case Intrinsic::mips_fcune_d:

1861 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1863 case Intrinsic::mips_fdiv_w:

1864 case Intrinsic::mips_fdiv_d:

1865

1867 Op->getOperand(2));

1868 case Intrinsic::mips_ffint_u_w:

1869 case Intrinsic::mips_ffint_u_d:

1871 Op->getOperand(1));

1872 case Intrinsic::mips_ffint_s_w:

1873 case Intrinsic::mips_ffint_s_d:

1875 Op->getOperand(1));

1876 case Intrinsic::mips_fill_b:

1877 case Intrinsic::mips_fill_h:

1878 case Intrinsic::mips_fill_w:

1879 case Intrinsic::mips_fill_d: {

1880 EVT ResTy = Op->getValueType(0);

1882 Op->getOperand(1));

1883

1884

1885

1887 }

1888 case Intrinsic::mips_fexp2_w:

1889 case Intrinsic::mips_fexp2_d: {

1890

1891 EVT ResTy = Op->getValueType(0);

1895 }

1896 case Intrinsic::mips_flog2_w:

1897 case Intrinsic::mips_flog2_d:

1899 case Intrinsic::mips_fmadd_w:

1900 case Intrinsic::mips_fmadd_d:

1902 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

1903 case Intrinsic::mips_fmul_w:

1904 case Intrinsic::mips_fmul_d:

1905

1907 Op->getOperand(2));

1908 case Intrinsic::mips_fmsub_w:

1909 case Intrinsic::mips_fmsub_d: {

1910

1912 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

1913 }

1914 case Intrinsic::mips_frint_w:

1915 case Intrinsic::mips_frint_d:

1917 case Intrinsic::mips_fsqrt_w:

1918 case Intrinsic::mips_fsqrt_d:

1920 case Intrinsic::mips_fsub_w:

1921 case Intrinsic::mips_fsub_d:

1922

1924 Op->getOperand(2));

1925 case Intrinsic::mips_ftrunc_u_w:

1926 case Intrinsic::mips_ftrunc_u_d:

1928 Op->getOperand(1));

1929 case Intrinsic::mips_ftrunc_s_w:

1930 case Intrinsic::mips_ftrunc_s_d:

1932 Op->getOperand(1));

1933 case Intrinsic::mips_ilvev_b:

1934 case Intrinsic::mips_ilvev_h:

1935 case Intrinsic::mips_ilvev_w:

1936 case Intrinsic::mips_ilvev_d:

1938 Op->getOperand(1), Op->getOperand(2));

1939 case Intrinsic::mips_ilvl_b:

1940 case Intrinsic::mips_ilvl_h:

1941 case Intrinsic::mips_ilvl_w:

1942 case Intrinsic::mips_ilvl_d:

1944 Op->getOperand(1), Op->getOperand(2));

1945 case Intrinsic::mips_ilvod_b:

1946 case Intrinsic::mips_ilvod_h:

1947 case Intrinsic::mips_ilvod_w:

1948 case Intrinsic::mips_ilvod_d:

1950 Op->getOperand(1), Op->getOperand(2));

1951 case Intrinsic::mips_ilvr_b:

1952 case Intrinsic::mips_ilvr_h:

1953 case Intrinsic::mips_ilvr_w:

1954 case Intrinsic::mips_ilvr_d:

1956 Op->getOperand(1), Op->getOperand(2));

1957 case Intrinsic::mips_insert_b:

1958 case Intrinsic::mips_insert_h:

1959 case Intrinsic::mips_insert_w:

1960 case Intrinsic::mips_insert_d:

1962 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));

1963 case Intrinsic::mips_insve_b:

1964 case Intrinsic::mips_insve_h:

1965 case Intrinsic::mips_insve_w:

1966 case Intrinsic::mips_insve_d: {

1967

1968 int64_t Max;

1969 switch (Intrinsic) {

1970 case Intrinsic::mips_insve_b: Max = 15; break;

1971 case Intrinsic::mips_insve_h: Max = 7; break;

1972 case Intrinsic::mips_insve_w: Max = 3; break;

1973 case Intrinsic::mips_insve_d: Max = 1; break;

1975 }

1976 int64_t Value = cast(Op->getOperand(2))->getSExtValue();

1977 if (Value < 0 || Value > Max)

1980 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),

1982 }

1983 case Intrinsic::mips_ldi_b:

1984 case Intrinsic::mips_ldi_h:

1985 case Intrinsic::mips_ldi_w:

1986 case Intrinsic::mips_ldi_d:

1988 case Intrinsic::mips_lsa:

1989 case Intrinsic::mips_dlsa: {

1990 EVT ResTy = Op->getValueType(0);

1993 Op->getOperand(2), Op->getOperand(3)));

1994 }

1995 case Intrinsic::mips_maddv_b:

1996 case Intrinsic::mips_maddv_h:

1997 case Intrinsic::mips_maddv_w:

1998 case Intrinsic::mips_maddv_d: {

1999 EVT ResTy = Op->getValueType(0);

2002 Op->getOperand(2), Op->getOperand(3)));

2003 }

2004 case Intrinsic::mips_max_s_b:

2005 case Intrinsic::mips_max_s_h:

2006 case Intrinsic::mips_max_s_w:

2007 case Intrinsic::mips_max_s_d:

2009 Op->getOperand(1), Op->getOperand(2));

2010 case Intrinsic::mips_max_u_b:

2011 case Intrinsic::mips_max_u_h:

2012 case Intrinsic::mips_max_u_w:

2013 case Intrinsic::mips_max_u_d:

2015 Op->getOperand(1), Op->getOperand(2));

2016 case Intrinsic::mips_maxi_s_b:

2017 case Intrinsic::mips_maxi_s_h:

2018 case Intrinsic::mips_maxi_s_w:

2019 case Intrinsic::mips_maxi_s_d:

2022 case Intrinsic::mips_maxi_u_b:

2023 case Intrinsic::mips_maxi_u_h:

2024 case Intrinsic::mips_maxi_u_w:

2025 case Intrinsic::mips_maxi_u_d:

2028 case Intrinsic::mips_min_s_b:

2029 case Intrinsic::mips_min_s_h:

2030 case Intrinsic::mips_min_s_w:

2031 case Intrinsic::mips_min_s_d:

2033 Op->getOperand(1), Op->getOperand(2));

2034 case Intrinsic::mips_min_u_b:

2035 case Intrinsic::mips_min_u_h:

2036 case Intrinsic::mips_min_u_w:

2037 case Intrinsic::mips_min_u_d:

2039 Op->getOperand(1), Op->getOperand(2));

2040 case Intrinsic::mips_mini_s_b:

2041 case Intrinsic::mips_mini_s_h:

2042 case Intrinsic::mips_mini_s_w:

2043 case Intrinsic::mips_mini_s_d:

2046 case Intrinsic::mips_mini_u_b:

2047 case Intrinsic::mips_mini_u_h:

2048 case Intrinsic::mips_mini_u_w:

2049 case Intrinsic::mips_mini_u_d:

2052 case Intrinsic::mips_mod_s_b:

2053 case Intrinsic::mips_mod_s_h:

2054 case Intrinsic::mips_mod_s_w:

2055 case Intrinsic::mips_mod_s_d:

2057 Op->getOperand(2));

2058 case Intrinsic::mips_mod_u_b:

2059 case Intrinsic::mips_mod_u_h:

2060 case Intrinsic::mips_mod_u_w:

2061 case Intrinsic::mips_mod_u_d:

2063 Op->getOperand(2));

2064 case Intrinsic::mips_mulv_b:

2065 case Intrinsic::mips_mulv_h:

2066 case Intrinsic::mips_mulv_w:

2067 case Intrinsic::mips_mulv_d:

2069 Op->getOperand(2));

2070 case Intrinsic::mips_msubv_b:

2071 case Intrinsic::mips_msubv_h:

2072 case Intrinsic::mips_msubv_w:

2073 case Intrinsic::mips_msubv_d: {

2074 EVT ResTy = Op->getValueType(0);

2077 Op->getOperand(2), Op->getOperand(3)));

2078 }

2079 case Intrinsic::mips_nlzc_b:

2080 case Intrinsic::mips_nlzc_h:

2081 case Intrinsic::mips_nlzc_w:

2082 case Intrinsic::mips_nlzc_d:

2084 case Intrinsic::mips_nor_v: {

2086 Op->getOperand(1), Op->getOperand(2));

2088 }

2089 case Intrinsic::mips_nori_b: {

2091 Op->getOperand(1),

2094 }

2095 case Intrinsic::mips_or_v:

2097 Op->getOperand(2));

2098 case Intrinsic::mips_ori_b:

2101 case Intrinsic::mips_pckev_b:

2102 case Intrinsic::mips_pckev_h:

2103 case Intrinsic::mips_pckev_w:

2104 case Intrinsic::mips_pckev_d:

2106 Op->getOperand(1), Op->getOperand(2));

2107 case Intrinsic::mips_pckod_b:

2108 case Intrinsic::mips_pckod_h:

2109 case Intrinsic::mips_pckod_w:

2110 case Intrinsic::mips_pckod_d:

2112 Op->getOperand(1), Op->getOperand(2));

2113 case Intrinsic::mips_pcnt_b:

2114 case Intrinsic::mips_pcnt_h:

2115 case Intrinsic::mips_pcnt_w:

2116 case Intrinsic::mips_pcnt_d:

2118 case Intrinsic::mips_sat_s_b:

2119 case Intrinsic::mips_sat_s_h:

2120 case Intrinsic::mips_sat_s_w:

2121 case Intrinsic::mips_sat_s_d:

2122 case Intrinsic::mips_sat_u_b:

2123 case Intrinsic::mips_sat_u_h:

2124 case Intrinsic::mips_sat_u_w:

2125 case Intrinsic::mips_sat_u_d: {

2126

2127 int64_t Max;

2128 switch (Intrinsic) {

2129 case Intrinsic::mips_sat_s_b:

2130 case Intrinsic::mips_sat_u_b: Max = 7; break;

2131 case Intrinsic::mips_sat_s_h:

2132 case Intrinsic::mips_sat_u_h: Max = 15; break;

2133 case Intrinsic::mips_sat_s_w:

2134 case Intrinsic::mips_sat_u_w: Max = 31; break;

2135 case Intrinsic::mips_sat_s_d:

2136 case Intrinsic::mips_sat_u_d: Max = 63; break;

2138 }

2139 int64_t Value = cast(Op->getOperand(2))->getSExtValue();

2140 if (Value < 0 || Value > Max)

2143 }

2144 case Intrinsic::mips_shf_b:

2145 case Intrinsic::mips_shf_h:

2146 case Intrinsic::mips_shf_w: {

2147 int64_t Value = cast(Op->getOperand(2))->getSExtValue();

2148 if (Value < 0 || Value > 255)

2151 Op->getOperand(2), Op->getOperand(1));

2152 }

2153 case Intrinsic::mips_sldi_b:

2154 case Intrinsic::mips_sldi_h:

2155 case Intrinsic::mips_sldi_w:

2156 case Intrinsic::mips_sldi_d: {

2157

2158 int64_t Max;

2159 switch (Intrinsic) {

2160 case Intrinsic::mips_sldi_b: Max = 15; break;

2161 case Intrinsic::mips_sldi_h: Max = 7; break;

2162 case Intrinsic::mips_sldi_w: Max = 3; break;

2163 case Intrinsic::mips_sldi_d: Max = 1; break;

2165 }

2166 int64_t Value = cast(Op->getOperand(3))->getSExtValue();

2167 if (Value < 0 || Value > Max)

2170 }

2171 case Intrinsic::mips_sll_b:

2172 case Intrinsic::mips_sll_h:

2173 case Intrinsic::mips_sll_w:

2174 case Intrinsic::mips_sll_d:

2177 case Intrinsic::mips_slli_b:

2178 case Intrinsic::mips_slli_h:

2179 case Intrinsic::mips_slli_w:

2180 case Intrinsic::mips_slli_d:

2183 case Intrinsic::mips_splat_b:

2184 case Intrinsic::mips_splat_h:

2185 case Intrinsic::mips_splat_w:

2186 case Intrinsic::mips_splat_d:

2187

2188

2189

2190

2193 Op->getOperand(1));

2194 case Intrinsic::mips_splati_b:

2195 case Intrinsic::mips_splati_h:

2196 case Intrinsic::mips_splati_w:

2197 case Intrinsic::mips_splati_d:

2200 Op->getOperand(1));

2201 case Intrinsic::mips_sra_b:

2202 case Intrinsic::mips_sra_h:

2203 case Intrinsic::mips_sra_w:

2204 case Intrinsic::mips_sra_d:

2207 case Intrinsic::mips_srai_b:

2208 case Intrinsic::mips_srai_h:

2209 case Intrinsic::mips_srai_w:

2210 case Intrinsic::mips_srai_d:

2213 case Intrinsic::mips_srari_b:

2214 case Intrinsic::mips_srari_h:

2215 case Intrinsic::mips_srari_w:

2216 case Intrinsic::mips_srari_d: {

2217

2218 int64_t Max;

2219 switch (Intrinsic) {

2220 case Intrinsic::mips_srari_b: Max = 7; break;

2221 case Intrinsic::mips_srari_h: Max = 15; break;

2222 case Intrinsic::mips_srari_w: Max = 31; break;

2223 case Intrinsic::mips_srari_d: Max = 63; break;

2225 }

2226 int64_t Value = cast(Op->getOperand(2))->getSExtValue();

2227 if (Value < 0 || Value > Max)

2230 }

2231 case Intrinsic::mips_srl_b:

2232 case Intrinsic::mips_srl_h:

2233 case Intrinsic::mips_srl_w:

2234 case Intrinsic::mips_srl_d:

2237 case Intrinsic::mips_srli_b:

2238 case Intrinsic::mips_srli_h:

2239 case Intrinsic::mips_srli_w:

2240 case Intrinsic::mips_srli_d:

2243 case Intrinsic::mips_srlri_b:

2244 case Intrinsic::mips_srlri_h:

2245 case Intrinsic::mips_srlri_w:

2246 case Intrinsic::mips_srlri_d: {

2247

2248 int64_t Max;

2249 switch (Intrinsic) {

2250 case Intrinsic::mips_srlri_b: Max = 7; break;

2251 case Intrinsic::mips_srlri_h: Max = 15; break;

2252 case Intrinsic::mips_srlri_w: Max = 31; break;

2253 case Intrinsic::mips_srlri_d: Max = 63; break;

2255 }

2256 int64_t Value = cast(Op->getOperand(2))->getSExtValue();

2257 if (Value < 0 || Value > Max)

2260 }

2261 case Intrinsic::mips_subv_b:

2262 case Intrinsic::mips_subv_h:

2263 case Intrinsic::mips_subv_w:

2264 case Intrinsic::mips_subv_d:

2266 Op->getOperand(2));

2267 case Intrinsic::mips_subvi_b:

2268 case Intrinsic::mips_subvi_h:

2269 case Intrinsic::mips_subvi_w:

2270 case Intrinsic::mips_subvi_d:

2273 case Intrinsic::mips_vshf_b:

2274 case Intrinsic::mips_vshf_h:

2275 case Intrinsic::mips_vshf_w:

2276 case Intrinsic::mips_vshf_d:

2278 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

2279 case Intrinsic::mips_xor_v:

2281 Op->getOperand(2));

2282 case Intrinsic::mips_xori_b:

2285 case Intrinsic::thread_pointer: {

2288 }

2289 }

2290}

2291

2295 SDValue ChainIn = Op->getOperand(0);

2298 EVT ResTy = Op->getValueType(0);

2299 EVT PtrTy = Address->getValueType(0);

2300

2301

2302

2303

2306

2310}

2311

2312SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,

2314 unsigned Intr = Op->getConstantOperandVal(1);

2315 switch (Intr) {

2316 default:

2318 case Intrinsic::mips_extp:

2320 case Intrinsic::mips_extpdp:

2322 case Intrinsic::mips_extr_w:

2324 case Intrinsic::mips_extr_r_w:

2326 case Intrinsic::mips_extr_rs_w:

2328 case Intrinsic::mips_extr_s_h:

2330 case Intrinsic::mips_mthlip:

2332 case Intrinsic::mips_mulsaq_s_w_ph:

2334 case Intrinsic::mips_maq_s_w_phl:

2336 case Intrinsic::mips_maq_s_w_phr:

2338 case Intrinsic::mips_maq_sa_w_phl:

2340 case Intrinsic::mips_maq_sa_w_phr:

2342 case Intrinsic::mips_dpaq_s_w_ph:

2344 case Intrinsic::mips_dpsq_s_w_ph:

2346 case Intrinsic::mips_dpaq_sa_l_w:

2348 case Intrinsic::mips_dpsq_sa_l_w:

2350 case Intrinsic::mips_dpaqx_s_w_ph:

2352 case Intrinsic::mips_dpaqx_sa_w_ph:

2354 case Intrinsic::mips_dpsqx_s_w_ph:

2356 case Intrinsic::mips_dpsqx_sa_w_ph:

2358 case Intrinsic::mips_ld_b:

2359 case Intrinsic::mips_ld_h:

2360 case Intrinsic::mips_ld_w:

2361 case Intrinsic::mips_ld_d:

2363 }

2364}

2365

2369 SDValue ChainIn = Op->getOperand(0);

2373 EVT PtrTy = Address->getValueType(0);

2374

2375

2376

2377

2380

2382

2385}

2386

2387SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,

2389 unsigned Intr = Op->getConstantOperandVal(1);

2390 switch (Intr) {

2391 default:

2393 case Intrinsic::mips_st_b:

2394 case Intrinsic::mips_st_h:

2395 case Intrinsic::mips_st_w:

2396 case Intrinsic::mips_st_d:

2398 }

2399}

2400

2401

2402

2403

2404

2405

2406

2407

2408SDValue MipsSETargetLowering::

2411 EVT ResTy = Op->getValueType(0);

2412 SDValue Op0 = Op->getOperand(0);

2414

2417

2419 SDValue Op1 = Op->getOperand(1);

2423 }

2424

2425 return Op;

2426}

2427

2429 if (Op->isUndef())

2430 return true;

2431 if (isa(Op))

2432 return true;

2433 if (isa(Op))

2434 return true;

2435 return false;

2436}

2437

2441 return true;

2442 return false;

2443}

2444

2445

2446

2447

2448

2449

2450

2451

2452

2453

2454

2455

2456

2457

2461 EVT ResTy = Op->getValueType(0);

2463 APInt SplatValue, SplatUndef;

2464 unsigned SplatBitSize;

2465 bool HasAnyUndefs;

2466

2469

2470 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,

2471 HasAnyUndefs, 8,

2473

2474 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&

2475 SplatBitSize != 64)

2477

2478

2479

2480

2481 if (ResTy.isInteger() && !HasAnyUndefs)

2482 return Op;

2483

2484 EVT ViaVecTy;

2485

2486 switch (SplatBitSize) {

2487 default:

2489 case 8:

2490 ViaVecTy = MVT::v16i8;

2491 break;

2492 case 16:

2493 ViaVecTy = MVT::v8i16;

2494 break;

2495 case 32:

2496 ViaVecTy = MVT::v4i32;

2497 break;

2498 case 64:

2499

2501 }

2502

2503

2505

2506

2507 if (ViaVecTy != ResTy)

2509

2511 } else if (DAG.isSplatValue(Op, false))

2512 return Op;

2514

2515

2516

2517 EVT ResTy = Node->getValueType(0);

2518

2520

2523 for (unsigned i = 0; i < NumElts; ++i) {

2525 Node->getOperand(i),

2527 }

2529 }

2530

2532}

2533

2534

2535

2536

2537

2538

2539

2540

2541

2542

2543

2544

2545

2546

2547

2548

2549

2550

2551

2555 int SHFIndices[4] = { -1, -1, -1, -1 };

2556

2557 if (Indices.size() < 4)

2559

2560 for (unsigned i = 0; i < 4; ++i) {

2561 for (unsigned j = i; j < Indices.size(); j += 4) {

2562 int Idx = Indices[j];

2563

2564

2565

2566 if (Idx != -1) {

2567 Idx -= 4 * (j / 4);

2568 if (Idx < 0 || Idx >= 4)

2570 }

2571

2572

2573

2574 if (SHFIndices[i] == -1)

2575 SHFIndices[i] = Idx;

2576

2577

2578

2579 if (!(Idx == -1 || Idx == SHFIndices[i]))

2581 }

2582 }

2583

2584

2585 APInt Imm(32, 0);

2586 for (int i = 3; i >= 0; --i) {

2587 int Idx = SHFIndices[i];

2588

2589 if (Idx == -1)

2590 Idx = 0;

2591

2592 Imm <<= 2;

2593 Imm |= Idx & 0x3;

2594 }

2595

2599 Op->getOperand(0));

2600}

2601

2602

2603

2604template

2605static bool

2607 unsigned CheckStride,

2609 ValType ExpectedIndex, unsigned ExpectedIndexStride) {

2610 auto &I = Begin;

2611

2612 while (I != End) {

2613 if (*I != -1 && *I != ExpectedIndex)

2614 return false;

2615 ExpectedIndex += ExpectedIndexStride;

2616

2617

2618

2619 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)

2620 ;

2621 }

2622 return true;

2623}

2624

2625

2626

2627

2628

2629

2630

2631

2632

2637

2638 int SplatIndex = -1;

2639 for (const auto &V : Indices) {

2640 if (V != -1) {

2641 SplatIndex = V;

2642 break;

2643 }

2644 }

2645

2646 return fitsRegularPattern(Indices.begin(), 1, Indices.end(), SplatIndex,

2647 0);

2648}

2649

2650

2651

2652

2653

2654

2655

2656

2657

2658

2659

2660

2661

2662

2663

2664

2669

2672 const auto &Begin = Indices.begin();

2673 const auto &End = Indices.end();

2674

2675

2676

2677 if (fitsRegularPattern(Begin, 2, End, 0, 2))

2678 Wt = Op->getOperand(0);

2679 else if (fitsRegularPattern(Begin, 2, End, Indices.size(), 2))

2680 Wt = Op->getOperand(1);

2681 else

2683

2684

2685

2686 if (fitsRegularPattern(Begin + 1, 2, End, 0, 2))

2687 Ws = Op->getOperand(0);

2688 else if (fitsRegularPattern(Begin + 1, 2, End, Indices.size(), 2))

2689 Ws = Op->getOperand(1);

2690 else

2692

2694}

2695

2696

2697

2698

2699

2700

2701

2702

2703

2704

2705

2706

2707

2708

2709

2710

2715

2718 const auto &Begin = Indices.begin();

2719 const auto &End = Indices.end();

2720

2721

2722

2723 if (fitsRegularPattern(Begin, 2, End, 1, 2))

2724 Wt = Op->getOperand(0);

2725 else if (fitsRegularPattern(Begin, 2, End, Indices.size() + 1, 2))

2726 Wt = Op->getOperand(1);

2727 else

2729

2730

2731

2732 if (fitsRegularPattern(Begin + 1, 2, End, 1, 2))

2733 Ws = Op->getOperand(0);

2734 else if (fitsRegularPattern(Begin + 1, 2, End, Indices.size() + 1, 2))

2735 Ws = Op->getOperand(1);

2736 else

2738

2740}

2741

2742

2743

2744

2745

2746

2747

2748

2749

2750

2751

2752

2753

2754

2755

2756

2757

2762

2765 const auto &Begin = Indices.begin();

2766 const auto &End = Indices.end();

2767

2768

2769

2770 if (fitsRegularPattern(Begin, 2, End, 0, 1))

2771 Wt = Op->getOperand(0);

2772 else if (fitsRegularPattern(Begin, 2, End, Indices.size(), 1))

2773 Wt = Op->getOperand(1);

2774 else

2776

2777

2778

2779 if (fitsRegularPattern(Begin + 1, 2, End, 0, 1))

2780 Ws = Op->getOperand(0);

2781 else if (fitsRegularPattern(Begin + 1, 2, End, Indices.size(), 1))

2782 Ws = Op->getOperand(1);

2783 else

2785

2787}

2788

2789

2790

2791

2792

2793

2794

2795

2796

2797

2798

2799

2800

2801

2802

2803

2804

2809

2810 unsigned HalfSize = Indices.size() / 2;

2813 const auto &Begin = Indices.begin();

2814 const auto &End = Indices.end();

2815

2816

2817

2818 if (fitsRegularPattern(Begin, 2, End, HalfSize, 1))

2819 Wt = Op->getOperand(0);

2820 else if (fitsRegularPattern(Begin, 2, End, Indices.size() + HalfSize, 1))

2821 Wt = Op->getOperand(1);

2822 else

2824

2825

2826

2827 if (fitsRegularPattern(Begin + 1, 2, End, HalfSize, 1))

2828 Ws = Op->getOperand(0);

2829 else if (fitsRegularPattern(Begin + 1, 2, End, Indices.size() + HalfSize,

2830 1))

2831 Ws = Op->getOperand(1);

2832 else

2834

2836}

2837

2838

2839

2840

2841

2842

2843

2844

2845

2846

2847

2848

2849

2850

2851

2852

2857

2860 const auto &Begin = Indices.begin();

2861 const auto &Mid = Indices.begin() + Indices.size() / 2;

2862 const auto &End = Indices.end();

2863

2864 if (fitsRegularPattern(Begin, 1, Mid, 0, 2))

2865 Wt = Op->getOperand(0);

2866 else if (fitsRegularPattern(Begin, 1, Mid, Indices.size(), 2))

2867 Wt = Op->getOperand(1);

2868 else

2870

2871 if (fitsRegularPattern(Mid, 1, End, 0, 2))

2872 Ws = Op->getOperand(0);

2873 else if (fitsRegularPattern(Mid, 1, End, Indices.size(), 2))

2874 Ws = Op->getOperand(1);

2875 else

2877

2879}

2880

2881

2882

2883

2884

2885

2886

2887

2888

2889

2890

2891

2892

2893

2894

2895

2900

2903 const auto &Begin = Indices.begin();

2904 const auto &Mid = Indices.begin() + Indices.size() / 2;

2905 const auto &End = Indices.end();

2906

2907 if (fitsRegularPattern(Begin, 1, Mid, 1, 2))

2908 Wt = Op->getOperand(0);

2909 else if (fitsRegularPattern(Begin, 1, Mid, Indices.size() + 1, 2))

2910 Wt = Op->getOperand(1);

2911 else

2913

2914 if (fitsRegularPattern(Mid, 1, End, 1, 2))

2915 Ws = Op->getOperand(0);

2916 else if (fitsRegularPattern(Mid, 1, End, Indices.size() + 1, 2))

2917 Ws = Op->getOperand(1);

2918 else

2920

2922}

2923

2924

2925

2926

2927

2928

2929

2930

2931

2940 bool Using1stVec = false;

2941 bool Using2ndVec = false;

2944

2945 for (int i = 0; i < ResTyNumElts; ++i) {

2946

2947 int Idx = Indices[i];

2948

2949 if (0 <= Idx && Idx < ResTyNumElts)

2950 Using1stVec = true;

2951 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)

2952 Using2ndVec = true;

2953 }

2954

2955 for (int Idx : Indices)

2957

2959

2960 if (Using1stVec && Using2ndVec) {

2961 Op0 = Op->getOperand(0);

2962 Op1 = Op->getOperand(1);

2963 } else if (Using1stVec)

2964 Op0 = Op1 = Op->getOperand(0);

2965 else if (Using2ndVec)

2966 Op0 = Op1 = Op->getOperand(1);

2967 else

2968 llvm_unreachable("shuffle vector mask references neither vector operand?");

2969

2970

2971

2972

2973

2974

2975

2976

2978}

2979

2980

2981

2982SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,

2985 EVT ResTy = Op->getValueType(0);

2986

2989

2992

2993 for (int i = 0; i < ResTyNumElts; ++i)

2995

2996

2997

3016}

3017

3021

3022

3023

3024

3025

3026

3027

3028

3029

3030

3031

3032

3033

3044 F->insert(It, FBB);

3045 F->insert(It, TBB);

3046 F->insert(It, Sink);

3047

3048

3050 BB->end());

3051 Sink->transferSuccessorsAndUpdatePHIs(BB);

3052

3053

3058

3059

3061

3063

3064

3066 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)

3069

3070

3074

3075

3077 MI.getOperand(0).getReg())

3082

3083 MI.eraseFromParent();

3084 return Sink;

3085}

3086

3089

3090

3091

3092

3093

3094

3095

3096

3097

3098

3099

3100

3101

3102

3113 F->insert(It, FBB);

3114 F->insert(It, TBB);

3115 F->insert(It, Sink);

3116

3117

3119 BB->end());

3120 Sink->transferSuccessorsAndUpdatePHIs(BB);

3121

3122

3127

3128

3130 .addReg(MI.getOperand(1).getReg())

3132

3133

3135 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)

3138

3139

3143

3144

3146 MI.getOperand(0).getReg())

3151

3152 MI.eraseFromParent();

3153 return Sink;

3154}

3155

3156

3157

3158

3159

3160

3161

3162

3163

3164

3165

3172 Register Fd = MI.getOperand(0).getReg();

3173 Register Ws = MI.getOperand(1).getReg();

3174 unsigned Lane = MI.getOperand(2).getImm();

3175

3176 if (Lane == 0) {

3177 unsigned Wt = Ws;

3179

3180

3181 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);

3182

3184 }

3185

3187 } else {

3190 : &Mips::MSA128WEvensRegClass);

3191

3194 }

3195

3196 MI.eraseFromParent();

3197 return BB;

3198}

3199

3200

3201

3202

3203

3204

3205

3206

3207

3208

3209

3214

3217 Register Fd = MI.getOperand(0).getReg();

3218 Register Ws = MI.getOperand(1).getReg();

3219 unsigned Lane = MI.getOperand(2).getImm() * 2;

3221

3222 if (Lane == 0)

3224 else {

3225 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);

3226

3229 }

3230

3231 MI.eraseFromParent();

3232 return BB;

3233}

3234

3235

3236

3237

3238

3239

3240

3242MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,

3248 Register Wd_in = MI.getOperand(1).getReg();

3249 unsigned Lane = MI.getOperand(2).getImm();

3250 Register Fs = MI.getOperand(3).getReg();

3253 : &Mips::MSA128WEvensRegClass);

3254

3255 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)

3258 .addImm(Mips::sub_lo);

3264

3265 MI.eraseFromParent();

3266 return BB;

3267}

3268

3269

3270

3271

3272

3273

3274

3276MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,

3279

3284 Register Wd_in = MI.getOperand(1).getReg();

3285 unsigned Lane = MI.getOperand(2).getImm();

3286 Register Fs = MI.getOperand(3).getReg();

3287 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);

3288

3289 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)

3292 .addImm(Mips::sub_64);

3298

3299 MI.eraseFromParent();

3300 return BB;

3301}

3302

3303

3304

3305

3306

3307

3308

3309

3310

3311

3312

3313

3314

3315

3316

3317

3318

3319

3320

3321

3322

3325 bool IsFP) const {

3330 Register SrcVecReg = MI.getOperand(1).getReg();

3331 Register LaneReg = MI.getOperand(2).getReg();

3332 Register SrcValReg = MI.getOperand(3).getReg();

3333

3335

3337 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3340 unsigned EltLog2Size;

3341 unsigned InsertOp = 0;

3342 unsigned InsveOp = 0;

3343 switch (EltSizeInBytes) {

3344 default:

3346 case 1:

3347 EltLog2Size = 0;

3348 InsertOp = Mips::INSERT_B;

3349 InsveOp = Mips::INSVE_B;

3350 VecRC = &Mips::MSA128BRegClass;

3351 break;

3352 case 2:

3353 EltLog2Size = 1;

3354 InsertOp = Mips::INSERT_H;

3355 InsveOp = Mips::INSVE_H;

3356 VecRC = &Mips::MSA128HRegClass;

3357 break;

3358 case 4:

3359 EltLog2Size = 2;

3360 InsertOp = Mips::INSERT_W;

3361 InsveOp = Mips::INSVE_W;

3362 VecRC = &Mips::MSA128WRegClass;

3363 break;

3364 case 8:

3365 EltLog2Size = 3;

3366 InsertOp = Mips::INSERT_D;

3367 InsveOp = Mips::INSVE_D;

3368 VecRC = &Mips::MSA128DRegClass;

3369 break;

3370 }

3371

3372 if (IsFP) {

3374 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)

3377 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);

3378 SrcValReg = Wt;

3379 }

3380

3381

3382 if (EltSizeInBytes != 1) {

3383 Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);

3386 .addImm(EltLog2Size);

3387 LaneReg = LaneTmp1;

3388 }

3389

3390

3395 .addReg(LaneReg, 0, SubRegIdx);

3396

3398 if (IsFP) {

3399

3405 } else {

3406

3411 }

3412

3413

3414

3415

3416 Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);

3418 LaneTmp2)

3424 .addReg(LaneTmp2, 0, SubRegIdx);

3425

3426 MI.eraseFromParent();

3427 return BB;

3428}

3429

3430

3431

3432

3433

3434

3435

3436

3444 Register Fs = MI.getOperand(1).getReg();

3447 : &Mips::MSA128WEvensRegClass);

3450 : &Mips::MSA128WEvensRegClass);

3451

3452 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);

3453 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)

3456 .addImm(Mips::sub_lo);

3458

3459 MI.eraseFromParent();

3460 return BB;

3461}

3462

3463

3464

3465

3466

3467

3468

3469

3474

3479 Register Fs = MI.getOperand(1).getReg();

3480 Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);

3481 Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);

3482

3483 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);

3484 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)

3487 .addImm(Mips::sub_64);

3489

3490 MI.eraseFromParent();

3491 return BB;

3492}

3493

3494

3495

3496

3497

3498

3499

3500

3501

3502

3503

3504

3506MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,

3508

3512 Register Ws = MI.getOperand(0).getReg();

3513 Register Rt = MI.getOperand(1).getReg();

3516

3517

3518

3519

3521 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())

3523 : &Mips::GPR64RegClass);

3524 const bool UsingMips32 = RC == &Mips::GPR32RegClass;

3525 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);

3526

3528 if(!UsingMips32) {

3529 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);

3530 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)

3533 .addImm(Mips::sub_32);

3534 Rs = Tmp;

3535 }

3536 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))

3542

3543 MI.eraseFromParent();

3544 return BB;

3545}

3546

3547

3548

3549

3550

3551

3552

3553

3554

3555

3556

3557

3558

3559

3561MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,

3563

3568

3569

3570

3571

3573 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())

3575 : &Mips::GPR64RegClass);

3576

3577 const bool UsingMips32 = RC == &Mips::GPR32RegClass;

3579

3581 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);

3583 MIB.add(MO);

3584

3585 if(!UsingMips32) {

3586 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);

3587 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);

3588 Rt = Tmp;

3589 }

3590

3592

3593 MI.eraseFromParent();

3594 return BB;

3595}

3596

3597

3598

3599

3600

3601

3602

3603

3604

3605

3606

3607

3608

3609

3610

3611

3612

3613

3614

3615

3616

3617

3618

3619

3620

3621

3622

3623

3624

3625

3626

3627

3628

3629

3630

3631

3632

3633

3634

3635

3636

3637

3638

3639

3640

3641

3642

3643

3644

3645

3647MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,

3649 bool IsFGR64) const {

3650

3651

3652

3653

3655

3658

3662 Register Fs = MI.getOperand(1).getReg();

3663

3665 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);

3667 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3668 unsigned MFC1Opc = IsFGR64onMips64

3669 ? Mips::DMFC1

3670 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);

3671 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;

3672

3673

3677 unsigned WPHI = Wtemp;

3678

3679 if (IsFGR64onMips32) {

3682 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);

3683 Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);

3684 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)

3688 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)

3692 WPHI = Wtemp3;

3693 }

3694

3695 if (IsFGR64) {

3696 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);

3697 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)

3700 WPHI = Wtemp2;

3701 }

3702

3704

3705 MI.eraseFromParent();

3706 return BB;

3707}

3708

3709

3710

3711

3712

3713

3714

3715

3716

3717

3718

3719

3720

3721

3722

3723

3724

3725

3726

3727

3728

3729

3730

3731

3732

3733

3734

3735

3736

3737

3738

3739

3740

3741

3742

3743

3744

3745

3746

3747

3748

3749

3750

3752MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,

3754 bool IsFGR64) const {

3755

3756

3757

3758

3760

3763

3766 Register Fd = MI.getOperand(0).getReg();

3767 Register Ws = MI.getOperand(1).getReg();

3768

3771 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3772 unsigned MTC1Opc = IsFGR64onMips64

3773 ? Mips::DMTC1

3774 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);

3775 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;

3776

3777 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);

3779

3781 if (IsFGR64) {

3782 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);

3784 }

3785

3786

3788 Register FPRPHI = IsFGR64onMips32

3789 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)

3790 : Fd;

3793

3794 if (IsFGR64onMips32) {

3796 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)

3802 }

3803

3804 MI.eraseFromParent();

3805 return BB;

3806}

3807

3808

3809

3810

3811

3812

3813

3815MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,

3823

3824

3827

3828

3829 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())

3831 .addReg(MI.getOperand(1).getReg());

3832

3833 MI.eraseFromParent();

3834 return BB;

3835}

3836

3837

3838

3839

3840

3841

3842

3844MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,

3852

3853

3856

3857

3858 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())

3860 .addReg(MI.getOperand(1).getReg());

3861

3862 MI.eraseFromParent();

3863 return BB;

3864}

static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)

static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)

This file implements a class to represent arbitrary precision integral constant values and operations...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

const HexagonInstrInfo * TII

static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)

Determine whether a range fits a regular pattern of values.

static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)

static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG)

static bool isConstantOrUndef(const SDValue Op)

static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)

static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)

static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)

static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)

static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)

static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)

static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)

static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))

static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)

static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)

static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)

static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)

static bool isBitwiseInverse(SDValue N, SDValue OfNode)

static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, SelectionDAG &DAG)

static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)

static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)

static bool isVectorAllOnes(SDValue N)

static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)

static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)

static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)

static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)

static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)

static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)

static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)

static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))

static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static cl::opt< unsigned > MaxSteps("has-predecessor-max-steps", cl::Hidden, cl::init(8192), cl::desc("DAG combiner limit number of steps when searching DAG " "for predecessor nodes"))

This file defines the SmallVector class.

support::ulittle32_t & Wd

Class for arbitrary precision integers.

uint64_t getZExtValue() const

Get zero extended value.

APInt trunc(unsigned width) const

Truncate to new width.

bool isAllOnes() const

Determine if all bits are set. This is true for zero-width values.

unsigned getBitWidth() const

Return the number of bits in the APInt.

bool isNegative() const

Determine sign of this APInt.

unsigned logBase2() const

bool isPowerOf2() const

Check if this APInt's value is a power of two greater than zero.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)

Constructs an APInt value that has the top hiBitsSet bits set.

APInt lshr(unsigned shiftAmt) const

Logical right-shift function.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

LLVM Basic Block Representation.

A "pseudo-class" with methods for operating on BUILD_VECTORs.

bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const

Check if this is a constant splat, and if so, find the smallest element size that splats the vector.

CCState - This class holds information needed while lowering arguments and return values.

unsigned getInRegsParamsCount() const

uint64_t getZExtValue() const

This class represents an Operation in the Expression.

uint64_t getNumOperands() const

This class is used to represent ISD::LOAD nodes.

const SDValue & getBasePtr() const

const Triple & getTargetTriple() const

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

static auto fixedlen_vector_valuetypes()

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

Flags

Flags values. These may be or'd together.

Flags getFlags() const

Return the raw flags of the source value,.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

AAMDNodes getAAInfo() const

Returns the AA info that describes the dereference.

MachineMemOperand * getMemOperand() const

Return a MachineMemOperand object describing the memory reference performed by operation.

const SDValue & getChain() const

EVT getMemoryVT() const

Return the type of the in-memory value.

MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...

unsigned getIncomingArgSize() const

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)

Enable MSA support for the given floating-point type and Register class.

void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)

Enable MSA support for the given integer type and Register class.

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

const TargetRegisterClass * getRepRegClassFor(MVT VT) const override

Return the 'representative' register class for the specified value type.

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override

Determine if the target supports unaligned memory accesses.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

bool useSoftFloat() const

const MipsInstrInfo * getInstrInfo() const override

const MipsRegisterInfo * getRegisterInfo() const override

bool systemSupportsUnalignedAccess() const

Does the system support unaligned memory access.

bool isSingleFloat() const

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const

virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const

This function fills Ops, which is the list of operands that will later be used when a function call n...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

const MipsSubtarget & Subtarget

SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

unsigned getOpcode() const

Return the SelectionDAG opcode value for this node.

unsigned getNumOperands() const

Return the number of values used by this operation.

SDVTList getVTList() const

const SDValue & getOperand(unsigned Num) const

void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const

Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...

EVT getValueType(unsigned ResNo) const

Return the type of a specified result.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

EVT getValueType() const

Return the ValueType of the referenced return value.

const SDValue & getOperand(unsigned i) const

uint64_t getScalarValueSizeInBits() const

unsigned getOpcode() const

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const TargetSubtargetInfo & getSubtarget() const

SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)

Create a MERGE_VALUES node from the given operands.

SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...

SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)

Create a bitwise NOT operation as (XOR Val, -1).

const TargetLowering & getTargetLoweringInfo() const

SDValue getUNDEF(EVT VT)

Return an UNDEF node. UNDEF does not have a useful SDLoc.

SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)

Return an ISD::BUILD_VECTOR node.

bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const

Test whether V has a splatted value for all the demanded elements.

const DataLayout & getDataLayout() const

SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

SDValue getValueType(EVT)

SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)

LLVMContext * getContext() const

std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)

Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.

This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

typename SuperClass::const_iterator const_iterator

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

This class is used to represent ISD::STORE nodes.

const SDValue & getBasePtr() const

const SDValue & getValue() const

TargetInstrInfo - Interface to description of machine instruction set.

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const

Return the 'representative' register class for the specified value type.

void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)

Indicate that the specified condition code is or isn't supported on the target and indicate what to d...

void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)

Targets should invoke this method for each target independent node that they want to provide a custom...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

bool isLittleEndian() const

Tests whether the target triple is little endian.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

@ ADD

Simple integer binary arithmetic operators.

@ LOAD

LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...

@ FMA

FMA - Perform a * b + c with no intermediate rounding step.

@ INTRINSIC_VOID

OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ FADD

Simple binary floating point operators.

@ ATOMIC_FENCE

OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ BITCAST

BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...

@ BUILD_PAIR

BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ SIGN_EXTEND

Conversion operators.

@ FSINCOS

FSINCOS - Compute both fsin and fcos as a single operation.

@ FNEG

Perform various unary floating-point operations inspired by libm.

@ BR_CC

BR_CC - Conditional branch.

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ UNDEF

UNDEF - An undefined node.

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ FMINNUM

FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ FP_EXTEND

X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.

@ VSELECT

Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...

@ FMINIMUM

FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ TargetConstant

TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ INTRINSIC_WO_CHAIN

RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ BRCOND

BRCOND - Conditional branch.

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ INTRINSIC_W_CHAIN

RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...

@ BUILD_VECTOR

BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

bool isBuildVectorAllOnes(const SDNode *N)

Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

DWARFExpression::Operation Op

constexpr unsigned BitWidth

const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

unsigned Log2(Align A)

Returns the log2 of the alignment.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

EVT changeVectorElementTypeToInteger() const

Return a vector with the same number of elements as this vector, but with the element type converted ...

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

uint64_t getScalarSizeInBits() const

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

bool is128BitVector() const

Return true if this is a 128-bit vector type.

bool isVector() const

Return true if this is a vector value type.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool isInteger() const

Return true if this is an integer or a vector integer type.

This class contains a discriminated union of information about pointers in memory operands,...