MipsSEISelLowering.cpp Source File (original) (raw)

37#include "llvm/IR/IntrinsicsMips.h"

44#include

45#include

46#include

47#include

48#include

49#include

51using namespace llvm;

53#define DEBUG_TYPE "mips-isel"

60 cl::desc("Expand double precision loads and "

61 "stores to their single precision "

62 "counterparts"));

73 case MVT::v2i1:

75 break;

77 case MVT::v2i8:

79 case MVT::v2i16:

80 case MVT::v4i8:

82 case MVT::v2i32:

83 case MVT::v4i16:

84 case MVT::v8i8:

86 break;

92 case MVT::v2f32:

93 case MVT::v3f32:

96 default:

97 break;

98 }

99 }

101}

102

106

108

111

113

120 }

121 }

122 }

123

126

127 for (const auto &VecTy : VecTys) {

129

130

133

139 }

140

143

147 }

148 }

149

152

154 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);

155 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);

156 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);

157 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);

161

162

199

201 }

202

205

206

207 if ( Subtarget .isSingleFloat()) {

210 else

212 }

213

218 }

219 }

220

221

222

229 }

230

235

240

248 }

249

252

259 } else {

262 }

263

265

269

273 }

274

278 }

279

281

282

288

289

290

297

298

299

303

307

308 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");

312

314

315

320

325 }

326

328

329

335

336

337

344

345

346

350 }

351

353}

354

360

363 if (VT == MVT::Untyped)

364 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;

365

367}

368

369

373

374

377

385

407

408 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {

413 }

414

421}

422

423

427

428

431

438

439 if (Ty != MVT::v8f16) {

451

459 }

460}

461

465

466 EVT ResTy = Op->getValueType(0);

468

469

470

471

472 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));

473 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),

474 Op->getOperand(2));

475}

476

480

481 if (Subtarget.systemSupportsUnalignedAccess()) {

482

483

484

485

488 return true;

489 } else if (Subtarget.hasMips32r6()) {

490 return false;

491 }

492

493 switch (SVT) {

494 case MVT::i64:

495 case MVT::i32:

498 return true;

499 default:

500 return false;

501 }

502}

503

506 switch(Op.getOpcode()) {

507 case ISD::LOAD: return lowerLOAD(Op, DAG);

508 case ISD::STORE: return lowerSTORE(Op, DAG);

509 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);

510 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);

511 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);

512 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);

513 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);

514 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);

515 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,

516 DAG);

524 case ISD::BITCAST: return lowerBITCAST(Op, DAG);

525 }

526

528}

529

530

531

532

533

534

535

536

540 if (!Subtarget.hasMSA())

542

543 SDValue Op0 = N->getOperand(0);

544 SDValue Op1 = N->getOperand(1);

545 unsigned Op0Opcode = Op0->getOpcode();

546

547

548

549

550

551 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||

552 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {

554

555 if (!Mask)

557

558 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();

559

560 if (Log2IfPositive <= 0)

561 return SDValue();

562

565 unsigned ExtendTySize = ExtendTy.getSizeInBits();

566 unsigned Log2 = Log2IfPositive;

567

568 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||

569 Log2 == ExtendTySize) {

571 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),

574 }

575 }

576

578}

579

580

581

582

583

584

585

586

587

588

591

593 return false;

594

595 APInt SplatValue, SplatUndef;

596 unsigned SplatBitSize;

597 bool HasAnyUndefs;

598

599 if ( Node ->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,

600 8, !IsLittleEndian))

601 return false;

602

603 Imm = SplatValue;

604

605 return true;

606}

607

608

610

611

612 if (N->getOpcode() == ISD::BITCAST)

613 N = N->getOperand(0);

614

616

617 if (!BVN)

618 return false;

619

620 APInt SplatValue, SplatUndef;

621 unsigned SplatBitSize;

622 bool HasAnyUndefs;

623

624

625

626 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))

628

629 return false;

630}

631

632

635 return false;

636

638 return N->getOperand(1) == OfNode;

639

641 return N->getOperand(0) == OfNode;

642

643 return false;

644}

645

646

647

648

649

650

651

655 if (!Subtarget.hasMSA())

657

658 EVT Ty = N->getValueType(0);

659

660 if (!Ty.is128BitVector())

662

663 SDValue Op0 = N->getOperand(0);

664 SDValue Op1 = N->getOperand(1);

665

671 bool IsLittleEndian = !Subtarget.isLittle();

672

674 bool IsConstantMask = false;

675 APInt Mask, InvMask;

676

677

678

679

680

681 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {

682 Cond = Op0Op0;

683 IfSet = Op0Op1;

684

685 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&

686 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

687 IfClr = Op1Op1;

688 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&

689 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

690 IfClr = Op1Op0;

691

692 IsConstantMask = true;

693 }

694

695

696

697

698 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {

699 Cond = Op0Op1;

700 IfSet = Op0Op0;

701

702 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&

703 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

704 IfClr = Op1Op1;

705 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&

706 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)

707 IfClr = Op1Op0;

708

709 IsConstantMask = true;

710 }

711

712

713

714

717 Cond = Op1Op0;

718 IfSet = Op1Op1;

719 IfClr = Op0Op1;

721 Cond = Op1Op0;

722 IfSet = Op1Op1;

723 IfClr = Op0Op0;

725 Cond = Op1Op1;

726 IfSet = Op1Op0;

727 IfClr = Op0Op1;

729 Cond = Op1Op1;

730 IfSet = Op1Op0;

731 IfClr = Op0Op0;

733 Cond = Op0Op0;

734 IfSet = Op0Op1;

735 IfClr = Op1Op1;

737 Cond = Op0Op0;

738 IfSet = Op0Op1;

739 IfClr = Op1Op0;

741 Cond = Op0Op1;

742 IfSet = Op0Op0;

743 IfClr = Op1Op1;

745 Cond = Op0Op1;

746 IfSet = Op0Op0;

747 IfClr = Op1Op0;

748 }

749 }

750

751

754

756

757

758 if (IsConstantMask) {

759 if (Mask.isAllOnes())

760 return IfSet;

761 else if (Mask == 0)

762 return IfClr;

763 }

764

765

767 }

768

770}

771

775

776

777

778

779

780

781

782

783

784

785

786

787

788

789

790

791

792

793

794

795

796

797

798

799

801

803 unsigned Steps = 0;

804 unsigned BitWidth = C.getBitWidth();

805

806 while (!WorkStack.empty()) {

808

809 if (Val == 0 || Val == 1)

810 continue;

811

813 return false;

814

816 ++Steps;

817 continue;

818 }

819

823 if ((Val - Floor).ule(Ceil - Val)) {

825 WorkStack.push_back(Val - Floor);

826 } else {

829 }

830

831 ++Steps;

832 }

833

834

835

836

837

841 Steps *= (VT.getSizeInBits() != RegisterSize) * 3;

842 if (Steps > 27)

843 return false;

844

845 return true;

846}

847

850

851 if (C == 0)

853

854

855 if (C == 1)

856 return X;

857

858

859 if (C.isPowerOf2())

862

863 unsigned BitWidth = C.getBitWidth();

867

868

869

870

871 if ((C - Floor).ule(Ceil - C)) {

875 }

876

877

878

882}

883

888 EVT VT = N->getValueType(0);

889

892 C->getAPIntValue(), VT, DAG, Subtarget))

895 DAG);

896

898}

899

903

904 APInt SplatValue, SplatUndef;

905 unsigned SplatBitSize;

906 bool HasAnyUndefs;

907 unsigned EltSize = Ty.getScalarSizeInBits();

909

910 if (!Subtarget.hasDSP())

912

913 if (!BV ||

914 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,

915 EltSize, !Subtarget.isLittle()) ||

916 (SplatBitSize != EltSize) ||

919

921 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),

923}

924

928 EVT Ty = N->getValueType(0);

929

930 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))

932

934}

935

936

937

938

939

940

941

942

943

944

945

946

947

951 EVT Ty = N->getValueType(0);

952

953 if (Subtarget.hasMSA()) {

954 SDValue Op0 = N->getOperand(0);

955 SDValue Op1 = N->getOperand(1);

956

957

958

959

960

964

965 if (!ShAmount)

967

968 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&

969 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)

971

974

975 if (TotalBits == 32 ||

976 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&

977 TotalBits <= 32)) {

980 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),

983 }

984 }

985 }

986

987 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))

989

991}

992

993

997 EVT Ty = N->getValueType(0);

998

999 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))

1001

1003}

1004

1006 bool IsV216 = (Ty == MVT::v2i16);

1007

1008 switch (CC) {

1019 default: return false;

1020 }

1021}

1022

1024 EVT Ty = N->getValueType(0);

1025

1026 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))

1028

1031

1032 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),

1033 N->getOperand(1), N->getOperand(2));

1034}

1035

1037 EVT Ty = N->getValueType(0);

1038

1039 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {

1040 SDValue SetCC = N->getOperand(0);

1041

1042 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)

1044

1045 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,

1047 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));

1048 }

1049

1051}

1052

1055 EVT Ty = N->getValueType(0);

1056

1057 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {

1058

1059

1060

1061 SDValue Op0 = N->getOperand(0);

1062 SDValue Op1 = N->getOperand(1);

1064

1066 NotOp = Op1;

1068 NotOp = Op0;

1069 else

1071

1075 }

1076

1078}

1079

1084

1085 switch (N->getOpcode()) {

1088 break;

1091 break;

1096 break;

1105 break;

1108 break;

1109 }

1110

1113 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n";

1115 return Val;

1116 }

1117

1119}

1120

1124 switch (MI.getOpcode()) {

1125 default:

1127 case Mips::BPOSGE32_PSEUDO:

1128 return emitBPOSGE32(MI, BB);

1129 case Mips::SNZ_B_PSEUDO:

1130 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);

1131 case Mips::SNZ_H_PSEUDO:

1132 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);

1133 case Mips::SNZ_W_PSEUDO:

1134 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);

1135 case Mips::SNZ_D_PSEUDO:

1136 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);

1137 case Mips::SNZ_V_PSEUDO:

1138 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);

1139 case Mips::SZ_B_PSEUDO:

1140 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);

1141 case Mips::SZ_H_PSEUDO:

1142 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);

1143 case Mips::SZ_W_PSEUDO:

1144 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);

1145 case Mips::SZ_D_PSEUDO:

1146 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);

1147 case Mips::SZ_V_PSEUDO:

1148 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);

1149 case Mips::COPY_FW_PSEUDO:

1150 return emitCOPY_FW(MI, BB);

1151 case Mips::COPY_FD_PSEUDO:

1152 return emitCOPY_FD(MI, BB);

1153 case Mips::INSERT_FW_PSEUDO:

1154 return emitINSERT_FW(MI, BB);

1155 case Mips::INSERT_FD_PSEUDO:

1156 return emitINSERT_FD(MI, BB);

1157 case Mips::INSERT_B_VIDX_PSEUDO:

1158 case Mips::INSERT_B_VIDX64_PSEUDO:

1159 return emitINSERT_DF_VIDX(MI, BB, 1, false);

1160 case Mips::INSERT_H_VIDX_PSEUDO:

1161 case Mips::INSERT_H_VIDX64_PSEUDO:

1162 return emitINSERT_DF_VIDX(MI, BB, 2, false);

1163 case Mips::INSERT_W_VIDX_PSEUDO:

1164 case Mips::INSERT_W_VIDX64_PSEUDO:

1165 return emitINSERT_DF_VIDX(MI, BB, 4, false);

1166 case Mips::INSERT_D_VIDX_PSEUDO:

1167 case Mips::INSERT_D_VIDX64_PSEUDO:

1168 return emitINSERT_DF_VIDX(MI, BB, 8, false);

1169 case Mips::INSERT_FW_VIDX_PSEUDO:

1170 case Mips::INSERT_FW_VIDX64_PSEUDO:

1171 return emitINSERT_DF_VIDX(MI, BB, 4, true);

1172 case Mips::INSERT_FD_VIDX_PSEUDO:

1173 case Mips::INSERT_FD_VIDX64_PSEUDO:

1174 return emitINSERT_DF_VIDX(MI, BB, 8, true);

1175 case Mips::FILL_FW_PSEUDO:

1176 return emitFILL_FW(MI, BB);

1177 case Mips::FILL_FD_PSEUDO:

1178 return emitFILL_FD(MI, BB);

1179 case Mips::FEXP2_W_1_PSEUDO:

1180 return emitFEXP2_W_1(MI, BB);

1181 case Mips::FEXP2_D_1_PSEUDO:

1182 return emitFEXP2_D_1(MI, BB);

1183 case Mips::ST_F16:

1184 return emitST_F16_PSEUDO(MI, BB);

1185 case Mips::LD_F16:

1186 return emitLD_F16_PSEUDO(MI, BB);

1187 case Mips::MSA_FP_EXTEND_W_PSEUDO:

1188 return emitFPEXTEND_PSEUDO(MI, BB, false);

1189 case Mips::MSA_FP_ROUND_W_PSEUDO:

1190 return emitFPROUND_PSEUDO(MI, BB, false);

1191 case Mips::MSA_FP_EXTEND_D_PSEUDO:

1192 return emitFPEXTEND_PSEUDO(MI, BB, true);

1193 case Mips::MSA_FP_ROUND_D_PSEUDO:

1194 return emitFPROUND_PSEUDO(MI, BB, true);

1195 }

1196}

1197

1198bool MipsSETargetLowering::isEligibleForTailCallOptimization(

1199 const CCState &CCInfo, unsigned NextStackOffset,

1202 return false;

1203

1204

1206 return false;

1207

1208

1210 return false;

1211

1212

1213

1215}

1216

1217void MipsSETargetLowering::

1219 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,

1220 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,

1221 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,

1223 Ops.push_back(Callee);

1225 InternalLinkage, IsCallReloc, CLI, Callee,

1226 Chain);

1227}

1228

1231

1234

1235

1236 SDLoc DL(Op);

1239

1240

1241 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),

1243

1244

1247 MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),

1249

1252

1256}

1257

1260

1263

1264

1265 SDLoc DL(Op);

1272

1275

1276

1277 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlign(),

1279

1280

1282 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),

1285}

1286

1289 SDLoc DL(Op);

1290 MVT Src = Op.getOperand(0).getValueType().getSimpleVT();

1291 MVT Dest = Op.getValueType().getSimpleVT();

1292

1293

1294 if (Src == MVT::i64 && Dest == MVT::f64) {

1296 std::tie(Lo, Hi) =

1297 DAG.SplitScalar(Op.getOperand(0), DL, MVT::i32, MVT::i32);

1298 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);

1299 }

1300

1301

1302 if (Src == MVT::f64 && Dest == MVT::i64) {

1303

1304

1309 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),

1312 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),

1315 }

1316

1317

1319}

1320

1321SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,

1322 bool HasLo, bool HasHi,

1324

1326

1327 EVT Ty = Op.getOperand(0).getValueType();

1328 SDLoc DL(Op);

1330 Op.getOperand(0), Op.getOperand(1));

1332

1333 if (HasLo)

1334 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);

1335 if (HasHi)

1336 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);

1337

1338 if (!HasLo || !HasHi)

1339 return HasLo ? Lo : Hi;

1340

1343}

1344

1347 std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32);

1348 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);

1349}

1350

1356

1357

1358

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1371 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;

1373 unsigned OpNo = 0;

1374

1375

1376 if (HasChainIn)

1377 Ops.push_back(Op->getOperand(OpNo++));

1378

1379

1381

1382

1383 SDValue Opnd = Op->getOperand(++OpNo), In64;

1384

1387 else

1388 Ops.push_back(Opnd);

1389

1390

1391 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)

1392 Ops.push_back(Op->getOperand(OpNo));

1393

1394

1395 if (In64.getNode())

1396 Ops.push_back(In64);

1397

1398

1400

1401 for (EVT Ty : Op->values())

1402 ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty);

1403

1404

1406 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;

1407

1408 if (!HasChainIn)

1409 return Out;

1410

1414}

1415

1416

1419 SDValue Vec = Op->getOperand(1);

1420 SDValue Idx = Op->getOperand(2);

1421 EVT ResTy = Op->getValueType(0);

1423

1426

1427 return Result;

1428}

1429

1431 EVT ResVecTy = Op->getValueType(0);

1432 EVT ViaVecTy = ResVecTy;

1435

1436

1437

1438

1439 SDValue LaneA = Op->getOperand(OpNr);

1441

1442 if (ResVecTy == MVT::v2i64) {

1443

1444

1447

1448

1449

1450

1451 else

1452 LaneB = LaneA;

1453 ViaVecTy = MVT::v4i32;

1454 if(BigEndian)

1456 } else

1457 LaneB = LaneA;

1458

1459 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,

1460 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };

1461

1464

1465 if (ViaVecTy != ResVecTy) {

1467 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,

1469 }

1470

1471 return Result;

1472}

1473

1475 bool IsSigned = false) {

1478 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),

1479 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),

1480 SDLoc(Op), Op->getValueType(0));

1481}

1482

1485 EVT ViaVecTy = VecTy;

1486 SDValue SplatValueA = SplatValue;

1487 SDValue SplatValueB = SplatValue;

1489

1490 if (VecTy == MVT::v2i64) {

1491

1492 ViaVecTy = MVT::v4i32;

1493

1498 }

1499

1500

1501

1502 if (BigEndian)

1503 std::swap(SplatValueA, SplatValueB);

1504

1505 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1506 SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1507 SplatValueA, SplatValueB, SplatValueA, SplatValueB,

1508 SplatValueA, SplatValueB, SplatValueA, SplatValueB };

1509

1512

1513 if (VecTy != ViaVecTy)

1514 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);

1515

1516 return Result;

1517}

1518

1521 bool BigEndian) {

1522 EVT VecTy = Op->getValueType(0);

1525

1526

1527

1528 if (VecTy == MVT::v2i64) {

1530 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();

1531

1533 MVT::i32);

1535

1536 if (BigEndian)

1537 std::swap(BitImmLoOp, BitImmHiOp);

1538

1540 ISD::BITCAST, DL, MVT::v2i64,

1542 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));

1543 }

1544 }

1545

1546 if (!Exp2Imm.getNode()) {

1547

1548

1549

1550

1551 if (VecTy == MVT::v2i64)

1553

1555

1557 Exp2Imm);

1558 }

1559

1560 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);

1561}

1562

1565 EVT ResTy = Op->getValueType(0);

1566 SDValue Vec = Op->getOperand(2);

1568 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;

1570 DL, ResEltTy);

1572

1574}

1575

1577 EVT ResTy = Op->getValueType(0);

1581

1583 DAG.getNOT(DL, Bit, ResTy));

1584}

1585

1588 EVT ResTy = Op->getValueType(0);

1590 << Op->getConstantOperandAPInt(2);

1592

1594}

1595

1596SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,

1598 SDLoc DL(Op);

1599 unsigned Intrinsic = Op->getConstantOperandVal(0);

1600 switch (Intrinsic) {

1601 default:

1603 case Intrinsic::mips_shilo:

1605 case Intrinsic::mips_dpau_h_qbl:

1607 case Intrinsic::mips_dpau_h_qbr:

1609 case Intrinsic::mips_dpsu_h_qbl:

1611 case Intrinsic::mips_dpsu_h_qbr:

1613 case Intrinsic::mips_dpa_w_ph:

1615 case Intrinsic::mips_dps_w_ph:

1617 case Intrinsic::mips_dpax_w_ph:

1619 case Intrinsic::mips_dpsx_w_ph:

1621 case Intrinsic::mips_mulsa_w_ph:

1623 case Intrinsic::mips_mult:

1625 case Intrinsic::mips_multu:

1627 case Intrinsic::mips_madd:

1629 case Intrinsic::mips_maddu:

1631 case Intrinsic::mips_msub:

1633 case Intrinsic::mips_msubu:

1635 case Intrinsic::mips_addv_b:

1636 case Intrinsic::mips_addv_h:

1637 case Intrinsic::mips_addv_w:

1638 case Intrinsic::mips_addv_d:

1640 Op->getOperand(2));

1641 case Intrinsic::mips_addvi_b:

1642 case Intrinsic::mips_addvi_h:

1643 case Intrinsic::mips_addvi_w:

1644 case Intrinsic::mips_addvi_d:

1647 case Intrinsic::mips_and_v:

1649 Op->getOperand(2));

1650 case Intrinsic::mips_andi_b:

1653 case Intrinsic::mips_bclr_b:

1654 case Intrinsic::mips_bclr_h:

1655 case Intrinsic::mips_bclr_w:

1656 case Intrinsic::mips_bclr_d:

1658 case Intrinsic::mips_bclri_b:

1659 case Intrinsic::mips_bclri_h:

1660 case Intrinsic::mips_bclri_w:

1661 case Intrinsic::mips_bclri_d:

1663 case Intrinsic::mips_binsli_b:

1664 case Intrinsic::mips_binsli_h:

1665 case Intrinsic::mips_binsli_w:

1666 case Intrinsic::mips_binsli_d: {

1667

1668 EVT VecTy = Op->getValueType(0);

1670 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())

1673 Op->getConstantOperandVal(3) + 1);

1676 Op->getOperand(2), Op->getOperand(1));

1677 }

1678 case Intrinsic::mips_binsri_b:

1679 case Intrinsic::mips_binsri_h:

1680 case Intrinsic::mips_binsri_w:

1681 case Intrinsic::mips_binsri_d: {

1682

1683 EVT VecTy = Op->getValueType(0);

1685 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())

1688 Op->getConstantOperandVal(3) + 1);

1691 Op->getOperand(2), Op->getOperand(1));

1692 }

1693 case Intrinsic::mips_bmnz_v:

1695 Op->getOperand(2), Op->getOperand(1));

1696 case Intrinsic::mips_bmnzi_b:

1699 Op->getOperand(1));

1700 case Intrinsic::mips_bmz_v:

1702 Op->getOperand(1), Op->getOperand(2));

1703 case Intrinsic::mips_bmzi_b:

1706 Op->getOperand(2));

1707 case Intrinsic::mips_bneg_b:

1708 case Intrinsic::mips_bneg_h:

1709 case Intrinsic::mips_bneg_w:

1710 case Intrinsic::mips_bneg_d: {

1711 EVT VecTy = Op->getValueType(0);

1713

1717 }

1718 case Intrinsic::mips_bnegi_b:

1719 case Intrinsic::mips_bnegi_h:

1720 case Intrinsic::mips_bnegi_w:

1721 case Intrinsic::mips_bnegi_d:

1724 case Intrinsic::mips_bnz_b:

1725 case Intrinsic::mips_bnz_h:

1726 case Intrinsic::mips_bnz_w:

1727 case Intrinsic::mips_bnz_d:

1728 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),

1729 Op->getOperand(1));

1730 case Intrinsic::mips_bnz_v:

1731 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),

1732 Op->getOperand(1));

1733 case Intrinsic::mips_bsel_v:

1734

1736 Op->getOperand(1), Op->getOperand(3),

1737 Op->getOperand(2));

1738 case Intrinsic::mips_bseli_b:

1739

1742 Op->getOperand(2));

1743 case Intrinsic::mips_bset_b:

1744 case Intrinsic::mips_bset_h:

1745 case Intrinsic::mips_bset_w:

1746 case Intrinsic::mips_bset_d: {

1747 EVT VecTy = Op->getValueType(0);

1749

1753 }

1754 case Intrinsic::mips_bseti_b:

1755 case Intrinsic::mips_bseti_h:

1756 case Intrinsic::mips_bseti_w:

1757 case Intrinsic::mips_bseti_d:

1760 case Intrinsic::mips_bz_b:

1761 case Intrinsic::mips_bz_h:

1762 case Intrinsic::mips_bz_w:

1763 case Intrinsic::mips_bz_d:

1764 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),

1765 Op->getOperand(1));

1766 case Intrinsic::mips_bz_v:

1767 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),

1768 Op->getOperand(1));

1769 case Intrinsic::mips_ceq_b:

1770 case Intrinsic::mips_ceq_h:

1771 case Intrinsic::mips_ceq_w:

1772 case Intrinsic::mips_ceq_d:

1773 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1775 case Intrinsic::mips_ceqi_b:

1776 case Intrinsic::mips_ceqi_h:

1777 case Intrinsic::mips_ceqi_w:

1778 case Intrinsic::mips_ceqi_d:

1779 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1781 case Intrinsic::mips_cle_s_b:

1782 case Intrinsic::mips_cle_s_h:

1783 case Intrinsic::mips_cle_s_w:

1784 case Intrinsic::mips_cle_s_d:

1785 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1787 case Intrinsic::mips_clei_s_b:

1788 case Intrinsic::mips_clei_s_h:

1789 case Intrinsic::mips_clei_s_w:

1790 case Intrinsic::mips_clei_s_d:

1791 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1793 case Intrinsic::mips_cle_u_b:

1794 case Intrinsic::mips_cle_u_h:

1795 case Intrinsic::mips_cle_u_w:

1796 case Intrinsic::mips_cle_u_d:

1797 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1799 case Intrinsic::mips_clei_u_b:

1800 case Intrinsic::mips_clei_u_h:

1801 case Intrinsic::mips_clei_u_w:

1802 case Intrinsic::mips_clei_u_d:

1803 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1805 case Intrinsic::mips_clt_s_b:

1806 case Intrinsic::mips_clt_s_h:

1807 case Intrinsic::mips_clt_s_w:

1808 case Intrinsic::mips_clt_s_d:

1809 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1811 case Intrinsic::mips_clti_s_b:

1812 case Intrinsic::mips_clti_s_h:

1813 case Intrinsic::mips_clti_s_w:

1814 case Intrinsic::mips_clti_s_d:

1815 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1817 case Intrinsic::mips_clt_u_b:

1818 case Intrinsic::mips_clt_u_h:

1819 case Intrinsic::mips_clt_u_w:

1820 case Intrinsic::mips_clt_u_d:

1821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1823 case Intrinsic::mips_clti_u_b:

1824 case Intrinsic::mips_clti_u_h:

1825 case Intrinsic::mips_clti_u_w:

1826 case Intrinsic::mips_clti_u_d:

1827 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1829 case Intrinsic::mips_copy_s_b:

1830 case Intrinsic::mips_copy_s_h:

1831 case Intrinsic::mips_copy_s_w:

1833 case Intrinsic::mips_copy_s_d:

1835

1837 else {

1838

1839

1841 Op->getValueType(0), Op->getOperand(1),

1842 Op->getOperand(2));

1843 }

1844 case Intrinsic::mips_copy_u_b:

1845 case Intrinsic::mips_copy_u_h:

1846 case Intrinsic::mips_copy_u_w:

1848 case Intrinsic::mips_copy_u_d:

1850

1852 else {

1853

1854

1855

1856

1857

1859 Op->getValueType(0), Op->getOperand(1),

1860 Op->getOperand(2));

1861 }

1862 case Intrinsic::mips_div_s_b:

1863 case Intrinsic::mips_div_s_h:

1864 case Intrinsic::mips_div_s_w:

1865 case Intrinsic::mips_div_s_d:

1867 Op->getOperand(2));

1868 case Intrinsic::mips_div_u_b:

1869 case Intrinsic::mips_div_u_h:

1870 case Intrinsic::mips_div_u_w:

1871 case Intrinsic::mips_div_u_d:

1873 Op->getOperand(2));

1874 case Intrinsic::mips_fadd_w:

1875 case Intrinsic::mips_fadd_d:

1876

1878 Op->getOperand(2));

1879

1880 case Intrinsic::mips_fceq_w:

1881 case Intrinsic::mips_fceq_d:

1882 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1884 case Intrinsic::mips_fcle_w:

1885 case Intrinsic::mips_fcle_d:

1886 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1888 case Intrinsic::mips_fclt_w:

1889 case Intrinsic::mips_fclt_d:

1890 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1892 case Intrinsic::mips_fcne_w:

1893 case Intrinsic::mips_fcne_d:

1894 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1896 case Intrinsic::mips_fcor_w:

1897 case Intrinsic::mips_fcor_d:

1898 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1900 case Intrinsic::mips_fcueq_w:

1901 case Intrinsic::mips_fcueq_d:

1902 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1904 case Intrinsic::mips_fcule_w:

1905 case Intrinsic::mips_fcule_d:

1906 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1908 case Intrinsic::mips_fcult_w:

1909 case Intrinsic::mips_fcult_d:

1910 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1912 case Intrinsic::mips_fcun_w:

1913 case Intrinsic::mips_fcun_d:

1914 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1916 case Intrinsic::mips_fcune_w:

1917 case Intrinsic::mips_fcune_d:

1918 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),

1920 case Intrinsic::mips_fdiv_w:

1921 case Intrinsic::mips_fdiv_d:

1922

1924 Op->getOperand(2));

1925 case Intrinsic::mips_ffint_u_w:

1926 case Intrinsic::mips_ffint_u_d:

1928 Op->getOperand(1));

1929 case Intrinsic::mips_ffint_s_w:

1930 case Intrinsic::mips_ffint_s_d:

1932 Op->getOperand(1));

1933 case Intrinsic::mips_fill_b:

1934 case Intrinsic::mips_fill_h:

1935 case Intrinsic::mips_fill_w:

1936 case Intrinsic::mips_fill_d: {

1937 EVT ResTy = Op->getValueType(0);

1939 Op->getOperand(1));

1940

1941

1942

1944 }

1945 case Intrinsic::mips_fexp2_w:

1946 case Intrinsic::mips_fexp2_d: {

1947

1948 EVT ResTy = Op->getValueType(0);

1951 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));

1952 }

1953 case Intrinsic::mips_flog2_w:

1954 case Intrinsic::mips_flog2_d:

1955 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));

1956 case Intrinsic::mips_fmadd_w:

1957 case Intrinsic::mips_fmadd_d:

1959 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

1960 case Intrinsic::mips_fmul_w:

1961 case Intrinsic::mips_fmul_d:

1962

1964 Op->getOperand(2));

1965 case Intrinsic::mips_fmsub_w:

1966 case Intrinsic::mips_fmsub_d: {

1967

1968 return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),

1969 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

1970 }

1971 case Intrinsic::mips_frint_w:

1972 case Intrinsic::mips_frint_d:

1973 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));

1974 case Intrinsic::mips_fsqrt_w:

1975 case Intrinsic::mips_fsqrt_d:

1976 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));

1977 case Intrinsic::mips_fsub_w:

1978 case Intrinsic::mips_fsub_d:

1979

1981 Op->getOperand(2));

1982 case Intrinsic::mips_ftrunc_u_w:

1983 case Intrinsic::mips_ftrunc_u_d:

1985 Op->getOperand(1));

1986 case Intrinsic::mips_ftrunc_s_w:

1987 case Intrinsic::mips_ftrunc_s_d:

1989 Op->getOperand(1));

1990 case Intrinsic::mips_ilvev_b:

1991 case Intrinsic::mips_ilvev_h:

1992 case Intrinsic::mips_ilvev_w:

1993 case Intrinsic::mips_ilvev_d:

1994 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),

1995 Op->getOperand(1), Op->getOperand(2));

1996 case Intrinsic::mips_ilvl_b:

1997 case Intrinsic::mips_ilvl_h:

1998 case Intrinsic::mips_ilvl_w:

1999 case Intrinsic::mips_ilvl_d:

2000 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),

2001 Op->getOperand(1), Op->getOperand(2));

2002 case Intrinsic::mips_ilvod_b:

2003 case Intrinsic::mips_ilvod_h:

2004 case Intrinsic::mips_ilvod_w:

2005 case Intrinsic::mips_ilvod_d:

2006 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),

2007 Op->getOperand(1), Op->getOperand(2));

2008 case Intrinsic::mips_ilvr_b:

2009 case Intrinsic::mips_ilvr_h:

2010 case Intrinsic::mips_ilvr_w:

2011 case Intrinsic::mips_ilvr_d:

2012 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),

2013 Op->getOperand(1), Op->getOperand(2));

2014 case Intrinsic::mips_insert_b:

2015 case Intrinsic::mips_insert_h:

2016 case Intrinsic::mips_insert_w:

2017 case Intrinsic::mips_insert_d:

2019 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));

2020 case Intrinsic::mips_insve_b:

2021 case Intrinsic::mips_insve_h:

2022 case Intrinsic::mips_insve_w:

2023 case Intrinsic::mips_insve_d: {

2024

2025 int64_t Max;

2026 switch (Intrinsic) {

2027 case Intrinsic::mips_insve_b: Max = 15; break;

2028 case Intrinsic::mips_insve_h: Max = 7; break;

2029 case Intrinsic::mips_insve_w: Max = 3; break;

2030 case Intrinsic::mips_insve_d: Max = 1; break;

2032 }

2036 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),

2037 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),

2039 }

2040 case Intrinsic::mips_ldi_b:

2041 case Intrinsic::mips_ldi_h:

2042 case Intrinsic::mips_ldi_w:

2043 case Intrinsic::mips_ldi_d:

2045 case Intrinsic::mips_lsa:

2046 case Intrinsic::mips_dlsa: {

2047 EVT ResTy = Op->getValueType(0);

2050 Op->getOperand(2), Op->getOperand(3)));

2051 }

2052 case Intrinsic::mips_maddv_b:

2053 case Intrinsic::mips_maddv_h:

2054 case Intrinsic::mips_maddv_w:

2055 case Intrinsic::mips_maddv_d: {

2056 EVT ResTy = Op->getValueType(0);

2059 Op->getOperand(2), Op->getOperand(3)));

2060 }

2061 case Intrinsic::mips_max_s_b:

2062 case Intrinsic::mips_max_s_h:

2063 case Intrinsic::mips_max_s_w:

2064 case Intrinsic::mips_max_s_d:

2066 Op->getOperand(1), Op->getOperand(2));

2067 case Intrinsic::mips_max_u_b:

2068 case Intrinsic::mips_max_u_h:

2069 case Intrinsic::mips_max_u_w:

2070 case Intrinsic::mips_max_u_d:

2072 Op->getOperand(1), Op->getOperand(2));

2073 case Intrinsic::mips_maxi_s_b:

2074 case Intrinsic::mips_maxi_s_h:

2075 case Intrinsic::mips_maxi_s_w:

2076 case Intrinsic::mips_maxi_s_d:

2079 case Intrinsic::mips_maxi_u_b:

2080 case Intrinsic::mips_maxi_u_h:

2081 case Intrinsic::mips_maxi_u_w:

2082 case Intrinsic::mips_maxi_u_d:

2085 case Intrinsic::mips_min_s_b:

2086 case Intrinsic::mips_min_s_h:

2087 case Intrinsic::mips_min_s_w:

2088 case Intrinsic::mips_min_s_d:

2090 Op->getOperand(1), Op->getOperand(2));

2091 case Intrinsic::mips_min_u_b:

2092 case Intrinsic::mips_min_u_h:

2093 case Intrinsic::mips_min_u_w:

2094 case Intrinsic::mips_min_u_d:

2096 Op->getOperand(1), Op->getOperand(2));

2097 case Intrinsic::mips_mini_s_b:

2098 case Intrinsic::mips_mini_s_h:

2099 case Intrinsic::mips_mini_s_w:

2100 case Intrinsic::mips_mini_s_d:

2103 case Intrinsic::mips_mini_u_b:

2104 case Intrinsic::mips_mini_u_h:

2105 case Intrinsic::mips_mini_u_w:

2106 case Intrinsic::mips_mini_u_d:

2109 case Intrinsic::mips_mod_s_b:

2110 case Intrinsic::mips_mod_s_h:

2111 case Intrinsic::mips_mod_s_w:

2112 case Intrinsic::mips_mod_s_d:

2114 Op->getOperand(2));

2115 case Intrinsic::mips_mod_u_b:

2116 case Intrinsic::mips_mod_u_h:

2117 case Intrinsic::mips_mod_u_w:

2118 case Intrinsic::mips_mod_u_d:

2120 Op->getOperand(2));

2121 case Intrinsic::mips_mulv_b:

2122 case Intrinsic::mips_mulv_h:

2123 case Intrinsic::mips_mulv_w:

2124 case Intrinsic::mips_mulv_d:

2126 Op->getOperand(2));

2127 case Intrinsic::mips_msubv_b:

2128 case Intrinsic::mips_msubv_h:

2129 case Intrinsic::mips_msubv_w:

2130 case Intrinsic::mips_msubv_d: {

2131 EVT ResTy = Op->getValueType(0);

2134 Op->getOperand(2), Op->getOperand(3)));

2135 }

2136 case Intrinsic::mips_nlzc_b:

2137 case Intrinsic::mips_nlzc_h:

2138 case Intrinsic::mips_nlzc_w:

2139 case Intrinsic::mips_nlzc_d:

2141 case Intrinsic::mips_nor_v: {

2143 Op->getOperand(1), Op->getOperand(2));

2145 }

2146 case Intrinsic::mips_nori_b: {

2148 Op->getOperand(1),

2151 }

2152 case Intrinsic::mips_or_v:

2154 Op->getOperand(2));

2155 case Intrinsic::mips_ori_b:

2158 case Intrinsic::mips_pckev_b:

2159 case Intrinsic::mips_pckev_h:

2160 case Intrinsic::mips_pckev_w:

2161 case Intrinsic::mips_pckev_d:

2162 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),

2163 Op->getOperand(1), Op->getOperand(2));

2164 case Intrinsic::mips_pckod_b:

2165 case Intrinsic::mips_pckod_h:

2166 case Intrinsic::mips_pckod_w:

2167 case Intrinsic::mips_pckod_d:

2168 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),

2169 Op->getOperand(1), Op->getOperand(2));

2170 case Intrinsic::mips_pcnt_b:

2171 case Intrinsic::mips_pcnt_h:

2172 case Intrinsic::mips_pcnt_w:

2173 case Intrinsic::mips_pcnt_d:

2175 case Intrinsic::mips_sat_s_b:

2176 case Intrinsic::mips_sat_s_h:

2177 case Intrinsic::mips_sat_s_w:

2178 case Intrinsic::mips_sat_s_d:

2179 case Intrinsic::mips_sat_u_b:

2180 case Intrinsic::mips_sat_u_h:

2181 case Intrinsic::mips_sat_u_w:

2182 case Intrinsic::mips_sat_u_d: {

2183

2184 int64_t Max;

2185 switch (Intrinsic) {

2186 case Intrinsic::mips_sat_s_b:

2187 case Intrinsic::mips_sat_u_b: Max = 7; break;

2188 case Intrinsic::mips_sat_s_h:

2189 case Intrinsic::mips_sat_u_h: Max = 15; break;

2190 case Intrinsic::mips_sat_s_w:

2191 case Intrinsic::mips_sat_u_w: Max = 31; break;

2192 case Intrinsic::mips_sat_s_d:

2193 case Intrinsic::mips_sat_u_d: Max = 63; break;

2195 }

2200 }

2201 case Intrinsic::mips_shf_b:

2202 case Intrinsic::mips_shf_h:

2203 case Intrinsic::mips_shf_w: {

2207 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),

2208 Op->getOperand(2), Op->getOperand(1));

2209 }

2210 case Intrinsic::mips_sldi_b:

2211 case Intrinsic::mips_sldi_h:

2212 case Intrinsic::mips_sldi_w:

2213 case Intrinsic::mips_sldi_d: {

2214

2215 int64_t Max;

2216 switch (Intrinsic) {

2217 case Intrinsic::mips_sldi_b: Max = 15; break;

2218 case Intrinsic::mips_sldi_h: Max = 7; break;

2219 case Intrinsic::mips_sldi_w: Max = 3; break;

2220 case Intrinsic::mips_sldi_d: Max = 1; break;

2222 }

2227 }

2228 case Intrinsic::mips_sll_b:

2229 case Intrinsic::mips_sll_h:

2230 case Intrinsic::mips_sll_w:

2231 case Intrinsic::mips_sll_d:

2234 case Intrinsic::mips_slli_b:

2235 case Intrinsic::mips_slli_h:

2236 case Intrinsic::mips_slli_w:

2237 case Intrinsic::mips_slli_d:

2240 case Intrinsic::mips_splat_b:

2241 case Intrinsic::mips_splat_h:

2242 case Intrinsic::mips_splat_w:

2243 case Intrinsic::mips_splat_d:

2244

2245

2246

2247

2248 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),

2250 Op->getOperand(1));

2251 case Intrinsic::mips_splati_b:

2252 case Intrinsic::mips_splati_h:

2253 case Intrinsic::mips_splati_w:

2254 case Intrinsic::mips_splati_d:

2255 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),

2257 Op->getOperand(1));

2258 case Intrinsic::mips_sra_b:

2259 case Intrinsic::mips_sra_h:

2260 case Intrinsic::mips_sra_w:

2261 case Intrinsic::mips_sra_d:

2264 case Intrinsic::mips_srai_b:

2265 case Intrinsic::mips_srai_h:

2266 case Intrinsic::mips_srai_w:

2267 case Intrinsic::mips_srai_d:

2270 case Intrinsic::mips_srari_b:

2271 case Intrinsic::mips_srari_h:

2272 case Intrinsic::mips_srari_w:

2273 case Intrinsic::mips_srari_d: {

2274

2275 int64_t Max;

2276 switch (Intrinsic) {

2277 case Intrinsic::mips_srari_b: Max = 7; break;

2278 case Intrinsic::mips_srari_h: Max = 15; break;

2279 case Intrinsic::mips_srari_w: Max = 31; break;

2280 case Intrinsic::mips_srari_d: Max = 63; break;

2282 }

2287 }

2288 case Intrinsic::mips_srl_b:

2289 case Intrinsic::mips_srl_h:

2290 case Intrinsic::mips_srl_w:

2291 case Intrinsic::mips_srl_d:

2294 case Intrinsic::mips_srli_b:

2295 case Intrinsic::mips_srli_h:

2296 case Intrinsic::mips_srli_w:

2297 case Intrinsic::mips_srli_d:

2300 case Intrinsic::mips_srlri_b:

2301 case Intrinsic::mips_srlri_h:

2302 case Intrinsic::mips_srlri_w:

2303 case Intrinsic::mips_srlri_d: {

2304

2305 int64_t Max;

2306 switch (Intrinsic) {

2307 case Intrinsic::mips_srlri_b: Max = 7; break;

2308 case Intrinsic::mips_srlri_h: Max = 15; break;

2309 case Intrinsic::mips_srlri_w: Max = 31; break;

2310 case Intrinsic::mips_srlri_d: Max = 63; break;

2312 }

2317 }

2318 case Intrinsic::mips_subv_b:

2319 case Intrinsic::mips_subv_h:

2320 case Intrinsic::mips_subv_w:

2321 case Intrinsic::mips_subv_d:

2323 Op->getOperand(2));

2324 case Intrinsic::mips_subvi_b:

2325 case Intrinsic::mips_subvi_h:

2326 case Intrinsic::mips_subvi_w:

2327 case Intrinsic::mips_subvi_d:

2330 case Intrinsic::mips_vshf_b:

2331 case Intrinsic::mips_vshf_h:

2332 case Intrinsic::mips_vshf_w:

2333 case Intrinsic::mips_vshf_d:

2334 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),

2335 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));

2336 case Intrinsic::mips_xor_v:

2338 Op->getOperand(2));

2339 case Intrinsic::mips_xori_b:

2342 case Intrinsic::thread_pointer: {

2344 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);

2345 }

2346 }

2347}

2348

2352 SDValue ChainIn = Op->getOperand(0);

2353 SDValue Address = Op->getOperand(2);

2355 EVT ResTy = Op->getValueType(0);

2356 EVT PtrTy = Address->getValueType(0);

2357

2358

2359

2360

2363

2367}

2368

2369SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,

2371 unsigned Intr = Op->getConstantOperandVal(1);

2372 switch (Intr) {

2373 default:

2375 case Intrinsic::mips_extp:

2377 case Intrinsic::mips_extpdp:

2379 case Intrinsic::mips_extr_w:

2381 case Intrinsic::mips_extr_r_w:

2383 case Intrinsic::mips_extr_rs_w:

2385 case Intrinsic::mips_extr_s_h:

2387 case Intrinsic::mips_mthlip:

2389 case Intrinsic::mips_mulsaq_s_w_ph:

2390 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);

2391 case Intrinsic::mips_maq_s_w_phl:

2393 case Intrinsic::mips_maq_s_w_phr:

2395 case Intrinsic::mips_maq_sa_w_phl:

2396 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);

2397 case Intrinsic::mips_maq_sa_w_phr:

2398 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);

2399 case Intrinsic::mips_dpaq_s_w_ph:

2401 case Intrinsic::mips_dpsq_s_w_ph:

2403 case Intrinsic::mips_dpaq_sa_l_w:

2405 case Intrinsic::mips_dpsq_sa_l_w:

2407 case Intrinsic::mips_dpaqx_s_w_ph:

2408 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);

2409 case Intrinsic::mips_dpaqx_sa_w_ph:

2410 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);

2411 case Intrinsic::mips_dpsqx_s_w_ph:

2412 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);

2413 case Intrinsic::mips_dpsqx_sa_w_ph:

2414 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);

2415 case Intrinsic::mips_ld_b:

2416 case Intrinsic::mips_ld_h:

2417 case Intrinsic::mips_ld_w:

2418 case Intrinsic::mips_ld_d:

2420 }

2421}

2422

2426 SDValue ChainIn = Op->getOperand(0);

2428 SDValue Address = Op->getOperand(3);

2430 EVT PtrTy = Address->getValueType(0);

2431

2432

2433

2434

2437

2439

2442}

2443

2444SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,

2446 unsigned Intr = Op->getConstantOperandVal(1);

2447 switch (Intr) {

2448 default:

2450 case Intrinsic::mips_st_b:

2451 case Intrinsic::mips_st_h:

2452 case Intrinsic::mips_st_w:

2453 case Intrinsic::mips_st_d:

2455 }

2456}

2457

2458

2459

2460

2461

2462

2463

2464

2465SDValue MipsSETargetLowering::

2467 SDLoc DL(Op);

2468 EVT ResTy = Op->getValueType(0);

2469 SDValue Op0 = Op->getOperand(0);

2471

2474

2476 SDValue Op1 = Op->getOperand(1);

2478 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,

2480 }

2481

2482 return Op;

2483}

2484

2486 if (Op->isUndef())

2487 return true;

2489 return true;

2491 return true;

2492 return false;

2493}

2494

2496 for (unsigned i = 0; i < Op->getNumOperands(); ++i)

2498 return true;

2499 return false;

2500}

2501

2502

2503

2504

2505

2506

2507

2508

2509

2510

2511

2512

2513

2514

2518 EVT ResTy = Op->getValueType(0);

2519 SDLoc DL(Op);

2520 APInt SplatValue, SplatUndef;

2521 unsigned SplatBitSize;

2522 bool HasAnyUndefs;

2523

2526

2527 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,

2528 HasAnyUndefs, 8,

2529 Subtarget .isLittle()) && SplatBitSize <= 64) {

2530

2531 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&

2532 SplatBitSize != 64)

2534

2535

2536

2537

2538 if (ResTy.isInteger() && !HasAnyUndefs)

2539 return Op;

2540

2541 EVT ViaVecTy;

2542

2543 switch (SplatBitSize) {

2544 default:

2546 case 8:

2547 ViaVecTy = MVT::v16i8;

2548 break;

2549 case 16:

2550 ViaVecTy = MVT::v8i16;

2551 break;

2552 case 32:

2553 ViaVecTy = MVT::v4i32;

2554 break;

2555 case 64:

2556

2558 }

2559

2560

2562

2563

2564 if (ViaVecTy != ResTy)

2565 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);

2566

2568 } else if (DAG.isSplatValue(Op, false))

2569 return Op;

2571

2572

2573

2574 EVT ResTy = Node->getValueType(0);

2575

2577

2580 for (unsigned i = 0; i < NumElts; ++i) {

2582 Node->getOperand(i),

2584 }

2586 }

2587

2589}

2590

2591

2592

2593

2594

2595

2596

2597

2598

2599

2600

2601

2602

2603

2604

2605

2606

2607

2608

2612 int SHFIndices[4] = { -1, -1, -1, -1 };

2613

2614 if (Indices.size() < 4)

2616

2617 for (unsigned i = 0; i < 4; ++i) {

2618 for (unsigned j = i; j < Indices.size(); j += 4) {

2619 int Idx = Indices[j];

2620

2621

2622

2623 if (Idx != -1) {

2624 Idx -= 4 * (j / 4);

2625 if (Idx < 0 || Idx >= 4)

2627 }

2628

2629

2630

2631 if (SHFIndices[i] == -1)

2632 SHFIndices[i] = Idx;

2633

2634

2635

2636 if (!(Idx == -1 || Idx == SHFIndices[i]))

2638 }

2639 }

2640

2641

2642 APInt Imm(32, 0);

2643 for (int i = 3; i >= 0; --i) {

2644 int Idx = SHFIndices[i];

2645

2646 if (Idx == -1)

2647 Idx = 0;

2648

2649 Imm <<= 2;

2650 Imm |= Idx & 0x3;

2651 }

2652

2654 return DAG.getNode(MipsISD::SHF, DL, ResTy,

2656 Op->getOperand(0));

2657}

2658

2659

2660

2661template

2662static bool

2664 unsigned CheckStride,

2666 ValType ExpectedIndex, unsigned ExpectedIndexStride) {

2667 auto &I = Begin;

2668

2669 while (I != End) {

2670 if (*I != -1 && *I != ExpectedIndex)

2671 return false;

2672 ExpectedIndex += ExpectedIndexStride;

2673

2674

2675

2676 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)

2677 ;

2678 }

2679 return true;

2680}

2681

2682

2683

2684

2685

2686

2687

2688

2689

2694

2695 int SplatIndex = -1;

2696 for (const auto &V : Indices) {

2697 if (V != -1) {

2698 SplatIndex = V;

2699 break;

2700 }

2701 }

2702

2704 0);

2705}

2706

2707

2708

2709

2710

2711

2712

2713

2714

2715

2716

2717

2718

2719

2720

2721

2726

2729 const auto &Begin = Indices.begin();

2730 const auto &End = Indices.end();

2731

2732

2733

2735 Wt = Op->getOperand(0);

2737 Wt = Op->getOperand(1);

2738 else

2740

2741

2742

2744 Ws = Op->getOperand(0);

2746 Ws = Op->getOperand(1);

2747 else

2749

2750 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);

2751}

2752

2753

2754

2755

2756

2757

2758

2759

2760

2761

2762

2763

2764

2765

2766

2767

2772

2775 const auto &Begin = Indices.begin();

2776 const auto &End = Indices.end();

2777

2778

2779

2781 Wt = Op->getOperand(0);

2783 Wt = Op->getOperand(1);

2784 else

2786

2787

2788

2790 Ws = Op->getOperand(0);

2792 Ws = Op->getOperand(1);

2793 else

2795

2796 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Ws, Wt);

2797}

2798

2799

2800

2801

2802

2803

2804

2805

2806

2807

2808

2809

2810

2811

2812

2813

2814

2819

2822 const auto &Begin = Indices.begin();

2823 const auto &End = Indices.end();

2824

2825

2826

2828 Wt = Op->getOperand(0);

2830 Wt = Op->getOperand(1);

2831 else

2833

2834

2835

2837 Ws = Op->getOperand(0);

2839 Ws = Op->getOperand(1);

2840 else

2842

2843 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);

2844}

2845

2846

2847

2848

2849

2850

2851

2852

2853

2854

2855

2856

2857

2858

2859

2860

2861

2866

2867 unsigned HalfSize = Indices.size() / 2;

2870 const auto &Begin = Indices.begin();

2871 const auto &End = Indices.end();

2872

2873

2874

2876 Wt = Op->getOperand(0);

2878 Wt = Op->getOperand(1);

2879 else

2881

2882

2883

2885 Ws = Op->getOperand(0);

2887 1))

2888 Ws = Op->getOperand(1);

2889 else

2891

2892 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);

2893}

2894

2895

2896

2897

2898

2899

2900

2901

2902

2903

2904

2905

2906

2907

2908

2909

2914

2917 const auto &Begin = Indices.begin();

2918 const auto &Mid = Indices.begin() + Indices.size() / 2;

2919 const auto &End = Indices.end();

2920

2922 Wt = Op->getOperand(0);

2924 Wt = Op->getOperand(1);

2925 else

2927

2929 Ws = Op->getOperand(0);

2931 Ws = Op->getOperand(1);

2932 else

2934

2935 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);

2936}

2937

2938

2939

2940

2941

2942

2943

2944

2945

2946

2947

2948

2949

2950

2951

2952

2957

2960 const auto &Begin = Indices.begin();

2961 const auto &Mid = Indices.begin() + Indices.size() / 2;

2962 const auto &End = Indices.end();

2963

2965 Wt = Op->getOperand(0);

2967 Wt = Op->getOperand(1);

2968 else

2970

2972 Ws = Op->getOperand(0);

2974 Ws = Op->getOperand(1);

2975 else

2977

2978 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);

2979}

2980

2981

2982

2983

2984

2985

2986

2987

2988

2989

2990

2991

2992

2993

2996 const bool isSPLATI,

3003 bool Using1stVec = false;

3004 bool Using2ndVec = false;

3007

3008 assert(Indices[0] >= 0 &&

3009 "shuffle mask starts with an UNDEF, which is not expected");

3010

3011 for (int i = 0; i < ResTyNumElts; ++i) {

3012

3013 int Idx = Indices[i];

3014

3015 if (0 <= Idx && Idx < ResTyNumElts)

3016 Using1stVec = true;

3017 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)

3018 Using2ndVec = true;

3019 }

3020 int LastValidIndex = 0;

3021 for (size_t i = 0; i < Indices.size(); i++) {

3022 int Idx = Indices[i];

3023 if (Idx < 0) {

3024

3025 Idx = isSPLATI ? Indices[0] : LastValidIndex;

3026 } else {

3027 LastValidIndex = Idx;

3028 }

3030 }

3031

3033

3034 if (Using1stVec && Using2ndVec) {

3035 Op0 = Op->getOperand(0);

3036 Op1 = Op->getOperand(1);

3037 } else if (Using1stVec)

3038 Op0 = Op1 = Op->getOperand(0);

3039 else if (Using2ndVec)

3040 Op0 = Op1 = Op->getOperand(1);

3041 else

3042 llvm_unreachable("shuffle vector mask references neither vector operand?");

3043

3044

3045

3046

3047

3048

3049

3050

3051 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);

3052}

3053

3054

3055

3056SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,

3059 EVT ResTy = Op->getValueType(0);

3060

3063

3065 SmallVector<int, 16> Indices;

3066

3067 for (int i = 0; i < ResTyNumElts; ++i)

3069

3070

3071

3090}

3091

3095

3096

3097

3098

3099

3100

3101

3102

3103

3104

3105

3106

3107

3109 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3110 const TargetRegisterClass *RC = &Mips::GPR32RegClass;

3114 MachineFunction *F = BB->getParent();

3116 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);

3117 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);

3118 F->insert(It, FBB);

3119 F->insert(It, TBB);

3120 F->insert(It, Sink);

3121

3122

3124 BB->end());

3125 Sink->transferSuccessorsAndUpdatePHIs(BB);

3126

3127

3132

3133

3135

3137

3138

3143

3144

3148

3149

3151 MI.getOperand(0).getReg())

3156

3157 MI.eraseFromParent();

3158 return Sink;

3159}

3160

3163

3164

3165

3166

3167

3168

3169

3170

3171

3172

3173

3174

3175

3176

3178 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3179 const TargetRegisterClass *RC = &Mips::GPR32RegClass;

3183 MachineFunction *F = BB->getParent();

3184 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);

3185 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);

3186 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);

3187 F->insert(It, FBB);

3188 F->insert(It, TBB);

3189 F->insert(It, Sink);

3190

3191

3193 BB->end());

3194 Sink->transferSuccessorsAndUpdatePHIs(BB);

3195

3196

3201

3202

3204 .addReg(MI.getOperand(1).getReg())

3206

3207

3212

3213

3217

3218

3220 MI.getOperand(0).getReg())

3225

3226 MI.eraseFromParent();

3227 return Sink;

3228}

3229

3230

3231

3232

3233

3234

3235

3236

3237

3238

3239

3243 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3246 Register Fd = MI.getOperand(0).getReg();

3247 Register Ws = MI.getOperand(1).getReg();

3248 unsigned Lane = MI.getOperand(2).getImm();

3249

3250 if (Lane == 0) {

3251 unsigned Wt = Ws;

3253

3254

3256

3258 }

3259

3261 } else {

3263 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass

3264 : &Mips::MSA128WEvensRegClass);

3265

3268 }

3269

3270 MI.eraseFromParent();

3271 return BB;

3272}

3273

3274

3275

3276

3277

3278

3279

3280

3281

3282

3283

3288

3289 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3291 Register Fd = MI.getOperand(0).getReg();

3292 Register Ws = MI.getOperand(1).getReg();

3293 unsigned Lane = MI.getOperand(2).getImm() * 2;

3295

3296 if (Lane == 0)

3298 else {

3300

3303 }

3304

3305 MI.eraseFromParent();

3306 return BB;

3307}

3308

3309

3310

3311

3312

3313

3314

3316MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,

3318 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3321 Register Wd = MI.getOperand(0).getReg();

3322 Register Wd_in = MI.getOperand(1).getReg();

3323 unsigned Lane = MI.getOperand(2).getImm();

3324 Register Fs = MI.getOperand(3).getReg();

3326 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass

3327 : &Mips::MSA128WEvensRegClass);

3328

3332 .addImm(Mips::sub_lo);

3338

3339 MI.eraseFromParent();

3340 return BB;

3341}

3342

3343

3344

3345

3346

3347

3348

3350MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,

3353

3354 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3357 Register Wd = MI.getOperand(0).getReg();

3358 Register Wd_in = MI.getOperand(1).getReg();

3359 unsigned Lane = MI.getOperand(2).getImm();

3360 Register Fs = MI.getOperand(3).getReg();

3362

3366 .addImm(Mips::sub_64);

3372

3373 MI.eraseFromParent();

3374 return BB;

3375}

3376

3377

3378

3379

3380

3381

3382

3383

3384

3385

3386

3387

3388

3389

3390

3391

3392

3393

3394

3395

3396

3399 bool IsFP) const {

3400 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3403 Register Wd = MI.getOperand(0).getReg();

3404 Register SrcVecReg = MI.getOperand(1).getReg();

3405 Register LaneReg = MI.getOperand(2).getReg();

3406 Register SrcValReg = MI.getOperand(3).getReg();

3407

3408 const TargetRegisterClass *VecRC = nullptr;

3409

3410 const TargetRegisterClass *GPRRC =

3411 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3412 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;

3413 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;

3414 unsigned EltLog2Size;

3415 unsigned InsertOp = 0;

3416 unsigned InsveOp = 0;

3417 switch (EltSizeInBytes) {

3418 default:

3420 case 1:

3421 EltLog2Size = 0;

3422 InsertOp = Mips::INSERT_B;

3423 InsveOp = Mips::INSVE_B;

3424 VecRC = &Mips::MSA128BRegClass;

3425 break;

3426 case 2:

3427 EltLog2Size = 1;

3428 InsertOp = Mips::INSERT_H;

3429 InsveOp = Mips::INSVE_H;

3430 VecRC = &Mips::MSA128HRegClass;

3431 break;

3432 case 4:

3433 EltLog2Size = 2;

3434 InsertOp = Mips::INSERT_W;

3435 InsveOp = Mips::INSVE_W;

3436 VecRC = &Mips::MSA128WRegClass;

3437 break;

3438 case 8:

3439 EltLog2Size = 3;

3440 InsertOp = Mips::INSERT_D;

3441 InsveOp = Mips::INSVE_D;

3442 VecRC = &Mips::MSA128DRegClass;

3443 break;

3444 }

3445

3446 if (IsFP) {

3451 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);

3452 SrcValReg = Wt;

3453 }

3454

3455

3456 if (EltSizeInBytes != 1) {

3460 .addImm(EltLog2Size);

3461 LaneReg = LaneTmp1;

3462 }

3463

3464

3469 .addReg(LaneReg, 0, SubRegIdx);

3470

3472 if (IsFP) {

3473

3479 } else {

3480

3485 }

3486

3487

3488

3489

3492 LaneTmp2)

3493 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)

3498 .addReg(LaneTmp2, 0, SubRegIdx);

3499

3500 MI.eraseFromParent();

3501 return BB;

3502}

3503

3504

3505

3506

3507

3508

3509

3510

3514 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3517 Register Wd = MI.getOperand(0).getReg();

3518 Register Fs = MI.getOperand(1).getReg();

3520 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass

3521 : &Mips::MSA128WEvensRegClass);

3523 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass

3524 : &Mips::MSA128WEvensRegClass);

3525

3530 .addImm(Mips::sub_lo);

3532

3533 MI.eraseFromParent();

3534 return BB;

3535}

3536

3537

3538

3539

3540

3541

3542

3543

3548

3549 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3552 Register Wd = MI.getOperand(0).getReg();

3553 Register Fs = MI.getOperand(1).getReg();

3556

3561 .addImm(Mips::sub_64);

3563

3564 MI.eraseFromParent();

3565 return BB;

3566}

3567

3568

3569

3570

3571

3572

3573

3574

3575

3576

3577

3578

3580MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,

3582

3583 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3586 Register Ws = MI.getOperand(0).getReg();

3587 Register Rt = MI.getOperand(1).getReg();

3588 const MachineMemOperand &MMO = **MI.memoperands_begin();

3590

3591

3592

3593

3594 const TargetRegisterClass *RC =

3595 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())

3596 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass

3597 : &Mips::GPR64RegClass);

3598 const bool UsingMips32 = RC == &Mips::GPR32RegClass;

3600

3602 if(!UsingMips32) {

3607 .addImm(Mips::sub_32);

3608 Rs = Tmp;

3609 }

3610 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))

3616

3617 MI.eraseFromParent();

3618 return BB;

3619}

3620

3621

3622

3623

3624

3625

3626

3627

3628

3629

3630

3631

3632

3633

3635MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,

3637

3638 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3641 Register Wd = MI.getOperand(0).getReg();

3642

3643

3644

3645

3646 const TargetRegisterClass *RC =

3647 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())

3648 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass

3649 : &Mips::GPR64RegClass);

3650

3651 const bool UsingMips32 = RC == &Mips::GPR32RegClass;

3653

3654 MachineInstrBuilder MIB =

3655 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);

3657 MIB.add(MO);

3658

3659 if(!UsingMips32) {

3662 Rt = Tmp;

3663 }

3664

3666

3667 MI.eraseFromParent();

3668 return BB;

3669}

3670

3671

3672

3673

3674

3675

3676

3677

3678

3679

3680

3681

3682

3683

3684

3685

3686

3687

3688

3689

3690

3691

3692

3693

3694

3695

3696

3697

3698

3699

3700

3701

3702

3703

3704

3705

3706

3707

3708

3709

3710

3711

3712

3713

3714

3715

3716

3717

3718

3719

3721MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,

3723 bool IsFGR64) const {

3724

3725

3726

3727

3729

3730 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;

3731 bool IsFGR64onMips32 = Subtarget .hasMips64() && IsFGR64;

3732

3733 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3735 Register Wd = MI.getOperand(0).getReg();

3736 Register Fs = MI.getOperand(1).getReg();

3737

3740 const TargetRegisterClass *GPRRC =

3741 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3742 unsigned MFC1Opc = IsFGR64onMips64

3743 ? Mips::DMFC1

3744 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);

3745 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;

3746

3747

3751 unsigned WPHI = Wtemp;

3752

3753 if (IsFGR64onMips32) {

3766 WPHI = Wtemp3;

3767 }

3768

3769 if (IsFGR64) {

3774 WPHI = Wtemp2;

3775 }

3776

3778

3779 MI.eraseFromParent();

3780 return BB;

3781}

3782

3783

3784

3785

3786

3787

3788

3789

3790

3791

3792

3793

3794

3795

3796

3797

3798

3799

3800

3801

3802

3803

3804

3805

3806

3807

3808

3809

3810

3811

3812

3813

3814

3815

3816

3817

3818

3819

3820

3821

3822

3823

3824

3826MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,

3828 bool IsFGR64) const {

3829

3830

3831

3832

3834

3835 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;

3836 bool IsFGR64onMips32 = Subtarget .hasMips64() && IsFGR64;

3837

3838 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3840 Register Fd = MI.getOperand(0).getReg();

3841 Register Ws = MI.getOperand(1).getReg();

3842

3844 const TargetRegisterClass *GPRRC =

3845 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

3846 unsigned MTC1Opc = IsFGR64onMips64

3847 ? Mips::DMTC1

3848 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);

3849 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;

3850

3853

3855 if (IsFGR64) {

3858 }

3859

3860

3862 Register FPRPHI = IsFGR64onMips32

3864 : Fd;

3867

3868 if (IsFGR64onMips32) {

3876 }

3877

3878 MI.eraseFromParent();

3879 return BB;

3880}

3881

3882

3883

3884

3885

3886

3887

3889MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,

3891 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3893 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;

3897

3898

3901

3902

3903 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())

3905 .addReg(MI.getOperand(1).getReg());

3906

3907 MI.eraseFromParent();

3908 return BB;

3909}

3910

3911

3912

3913

3914

3915

3916

3918MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,

3920 const TargetInstrInfo *TII = Subtarget.getInstrInfo();

3922 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;

3926

3927

3930

3931

3932 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())

3934 .addReg(MI.getOperand(1).getReg());

3935

3936 MI.eraseFromParent();

3937 return BB;

3938}

static SDValue performSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)

If the operand is a bitwise AND with a constant RHS, and the shift has a constant RHS and is the only...

static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)

static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file implements a class to represent arbitrary precision integral constant values and operations...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)

Determine whether a range fits a regular pattern of values.

static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)

static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG)

Promote Memory to Register

static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)

Definition MipsSEISelLowering.cpp:1519

static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1586

static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:884

static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:1053

static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)

Definition MipsSEISelLowering.cpp:1369

static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:900

static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)

Definition MipsSEISelLowering.cpp:1417

static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))

static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2815

static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1483

static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1036

static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)

Definition MipsSEISelLowering.cpp:589

static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1345

static bool isBitwiseInverse(SDValue N, SDValue OfNode)

Definition MipsSEISelLowering.cpp:633

static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:2423

static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:948

static bool isVectorAllOnes(SDValue N)

Definition MipsSEISelLowering.cpp:609

static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2953

static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)

Definition MipsSEISelLowering.cpp:1005

static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1430

static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1576

static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2910

static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:848

static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)

Definition MipsSEISelLowering.cpp:1474

static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2768

static bool isConstantOrUndef(const SDValue Op)

Definition MipsSEISelLowering.cpp:2485

static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, const bool isSPLATI, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2994

static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2609

static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:1351

static bool shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:772

static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2722

static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2690

static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)

Definition MipsSEISelLowering.cpp:2495

static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)

Definition MipsSEISelLowering.cpp:2349

static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))

static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)

Definition MipsSEISelLowering.cpp:2862

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static cl::opt< unsigned > MaxSteps("has-predecessor-max-steps", cl::Hidden, cl::init(8192), cl::desc("DAG combiner limit number of steps when searching DAG " "for predecessor nodes"))

This file defines the SmallVector class.

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

uint64_t getZExtValue() const

Get zero extended value.

LLVM_ABI APInt trunc(unsigned width) const

Truncate to new width.

bool isAllOnes() const

Determine if all bits are set. This is true for zero-width values.

unsigned getBitWidth() const

Return the number of bits in the APInt.

bool isNegative() const

Determine sign of this APInt.

unsigned logBase2() const

bool isPowerOf2() const

Check if this APInt's value is a power of two greater than zero.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)

Constructs an APInt value that has the top hiBitsSet bits set.

APInt lshr(unsigned shiftAmt) const

Logical right-shift function.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

A "pseudo-class" with methods for operating on BUILD_VECTORs.

LLVM_ABI bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const

Check if this is a constant splat, and if so, find the smallest element size that splats the vector.

CCState - This class holds information needed while lowering arguments and return values.

unsigned getInRegsParamsCount() const

uint64_t getZExtValue() const

const SDValue & getBasePtr() const

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

const Triple & getTargetTriple() const

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

static auto fixedlen_vector_valuetypes()

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

MachineInstrBundleIterator< MachineInstr > iterator

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

BasicBlockListType::iterator iterator

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineInstr - Allocate a new MachineInstr.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

LocationSize getSize() const

Return the size in bytes of the memory reference.

Flags

Flags values. These may be or'd together.

Flags getFlags() const

Return the raw flags of the source value,.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

AAMDNodes getAAInfo() const

Returns the AA info that describes the dereference.

MachineMemOperand * getMemOperand() const

Return a MachineMemOperand object describing the memory reference performed by operation.

const SDValue & getChain() const

EVT getMemoryVT() const

Return the type of the in-memory value.

MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...

unsigned getIncomingArgSize() const

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

Definition MipsSEISelLowering.cpp:1081

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Return the preferred vector type legalization action.

Definition MipsSEISelLowering.cpp:68

void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)

Enable MSA support for the given floating-point type and Register class.

Definition MipsSEISelLowering.cpp:425

void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)

Enable MSA support for the given integer type and Register class.

Definition MipsSEISelLowering.cpp:371

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

Definition MipsSEISelLowering.cpp:1122

const TargetRegisterClass * getRepRegClassFor(MVT VT) const override

Return the 'representative' register class for the specified value type.

Definition MipsSEISelLowering.cpp:362

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override

Determine if the target supports unaligned memory accesses.

Definition MipsSEISelLowering.cpp:477

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

Definition MipsSEISelLowering.cpp:504

MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

Definition MipsSEISelLowering.cpp:103

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const

virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const

This function fills Ops, which is the list of operands that will later be used when a function call n...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

const MipsSubtarget & Subtarget

SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

unsigned getOpcode() const

Return the SelectionDAG opcode value for this node.

unsigned getNumOperands() const

Return the number of values used by this operation.

SDVTList getVTList() const

const SDValue & getOperand(unsigned Num) const

LLVM_ABI void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const

Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...

EVT getValueType(unsigned ResNo) const

Return the type of a specified result.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

const SDValue & getOperand(unsigned i) const

uint64_t getScalarValueSizeInBits() const

unsigned getOpcode() const

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const TargetSubtargetInfo & getSubtarget() const

LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)

Create a MERGE_VALUES node from the given operands.

SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...

LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

LLVM_ABI SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)

Create a bitwise NOT operation as (XOR Val, -1).

const TargetLowering & getTargetLoweringInfo() const

SDValue getUNDEF(EVT VT)

Return an UNDEF node. UNDEF does not have a useful SDLoc.

SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)

Return an ISD::BUILD_VECTOR node.

LLVM_ABI bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const

Test whether V has a splatted value for all the demanded elements.

const DataLayout & getDataLayout() const

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

LLVM_ABI SDValue getValueType(EVT)

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)

LLVMContext * getContext() const

LLVM_ABI std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)

Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

typename SuperClass::const_iterator const_iterator

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

const SDValue & getBasePtr() const

const SDValue & getValue() const

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const

Return the 'representative' register class for the specified value type.

void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)

Indicate that the specified condition code is or isn't supported on the target and indicate what to d...

void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)

Targets should invoke this method for each target independent node that they want to provide a custom...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

LLVM_ABI bool isLittleEndian() const

Tests whether the target triple is little endian.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

@ ADD

Simple integer binary arithmetic operators.

@ FMA

FMA - Perform a * b + c with no intermediate rounding step.

@ INTRINSIC_VOID

OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ FADD

Simple binary floating point operators.

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ BUILD_PAIR

BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.

@ STRICT_FSQRT

Constrained versions of libm-equivalent floating point intrinsics.

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ SIGN_EXTEND

Conversion operators.

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ UNDEF

UNDEF - An undefined node.

@ BasicBlock

Various leaf nodes.

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ VSELECT

Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ TargetConstant

TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ INTRINSIC_WO_CHAIN

RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

@ STRICT_FADD

Constrained versions of the binary floating point operators.

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ INTRINSIC_W_CHAIN

RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...

@ BUILD_VECTOR

BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

LLVM_ABI bool isBuildVectorAllOnes(const SDNode *N)

Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.

initializer< Ty > init(const Ty &Val)

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

FunctionAddr VTableAddr Value

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

constexpr unsigned BitWidth

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

Definition MipsSEISelLowering.cpp:356

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

unsigned Log2(Align A)

Returns the log2 of the alignment.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

EVT changeVectorElementTypeToInteger() const

Return a vector with the same number of elements as this vector, but with the element type converted ...

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

uint64_t getScalarSizeInBits() const

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

bool is128BitVector() const

Return true if this is a 128-bit vector type.

bool isVector() const

Return true if this is a vector value type.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool isInteger() const

Return true if this is an integer or a vector integer type.

This class contains a discriminated union of information about pointers in memory operands,...