LLVM: lib/Target/Mips/MipsSEISelLowering.cpp File Reference (original) (raw)

Go to the source code of this file.

Macros
#define DEBUG_TYPE "mips-isel"
Functions
static SDValue performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool isVSplat (SDValue N, APInt &Imm, bool IsLittleEndian)
static bool isVectorAllOnes (SDValue N)
static bool isBitwiseInverse (SDValue N, SDValue OfNode)
static SDValue performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool shouldTransformMulToShiftsAddsSubs (APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue genConstMult (SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
static SDValue performMULCombine (SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget)
static SDValue performDSPShiftCombine (unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSHLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performSRACombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static bool isLegalDSPCondCode (EVT Ty, ISD::CondCode CC)
static SDValue performSETCCCombine (SDNode *N, SelectionDAG &DAG)
static SDValue performVSELECTCombine (SDNode *N, SelectionDAG &DAG)
static SDValue performXORCombine (SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue initAccumulator (SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static SDValue extractLOHI (SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static SDValue lowerDSPIntr (SDValue Op, SelectionDAG &DAG, unsigned Opc)
static SDValue lowerMSACopyIntr (SDValue Op, SelectionDAG &DAG, unsigned Opc)
static SDValue lowerMSASplatZExt (SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue lowerMSASplatImm (SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue getBuildVectorSplat (EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
static SDValue lowerMSABinaryBitImmIntr (SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
static SDValue truncateVecElts (SDValue Op, SelectionDAG &DAG)
static SDValue lowerMSABitClear (SDValue Op, SelectionDAG &DAG)
static SDValue lowerMSABitClearImm (SDValue Op, SelectionDAG &DAG)
static SDValue lowerMSALoadIntr (SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue lowerMSAStoreIntr (SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static bool isConstantOrUndef (const SDValue Op)
static bool isConstantOrUndefBUILD_VECTOR (const BuildVectorSDNode *Op)
static SDValue lowerVECTOR_SHUFFLE_SHF (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
template
static bool fitsRegularPattern (typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
static bool isVECTOR_SHUFFLE_SPLATI (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_ILVEV (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_ILVOD (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_ILVR (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_ILVL (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_PCKEV (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_PCKOD (SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE_VSHF (SDValue Op, EVT ResTy, const SmallVector< int, 16 > &Indices, const bool isSPLATI, SelectionDAG &DAG)
Variables
static cl::opt< bool > UseMipsTailCalls ("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
static cl::opt< bool > NoDPLoadStore ("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts"))

◆ DEBUG_TYPE

#define DEBUG_TYPE "mips-isel"

◆ extractLOHI()

◆ fitsRegularPattern()

template

Determine whether a range fits a regular pattern of values.

This function accounts for the possibility of jumping over the End iterator.

Definition at line 2663 of file MipsSEISelLowering.cpp.

References I.

◆ genConstMult()

Definition at line 848 of file MipsSEISelLowering.cpp.

References llvm::ISD::ADD, llvm::BitWidth, llvm::CallingConv::C, DL, genConstMult(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::SHL, llvm::ISD::SUB, and X.

Referenced by genConstMult(), and performMULCombine().

◆ getBuildVectorSplat()

Definition at line 1483 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ISD::SRL, std::swap(), and llvm::ISD::TRUNCATE.

Referenced by lowerMSABinaryBitImmIntr(), and truncateVecElts().

◆ initAccumulator()

◆ isBitwiseInverse()

◆ isConstantOrUndef()

◆ isConstantOrUndefBUILD_VECTOR()

◆ isLegalDSPCondCode()

◆ isVECTOR_SHUFFLE_SPLATI()

◆ isVectorAllOnes()

◆ isVSplat()

◆ lowerDSPIntr()

Definition at line 1369 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, extractLOHI(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), initAccumulator(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), and llvm::ISD::TargetConstant.

◆ lowerMSABinaryBitImmIntr()

Definition at line 1519 of file MipsSEISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), getBuildVectorSplat(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::APInt::lshr(), Opc, llvm::ISD::SHL, std::swap(), llvm::APInt::trunc(), and llvm::ISD::ZERO_EXTEND.

◆ lowerMSABitClear()

◆ lowerMSABitClearImm()

◆ lowerMSACopyIntr()

◆ lowerMSALoadIntr()

◆ lowerMSASplatImm()

◆ lowerMSASplatZExt()

Definition at line 1430 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, llvm::ArrayRef(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::MCSubtargetInfo::getTargetTriple(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::Triple::isLittleEndian(), and std::swap().

◆ lowerMSAStoreIntr()

◆ lowerVECTOR_SHUFFLE_ILVEV()

◆ lowerVECTOR_SHUFFLE_ILVL()

◆ lowerVECTOR_SHUFFLE_ILVOD()

◆ lowerVECTOR_SHUFFLE_ILVR()

◆ lowerVECTOR_SHUFFLE_PCKEV()

◆ lowerVECTOR_SHUFFLE_PCKOD()

◆ lowerVECTOR_SHUFFLE_SHF()

◆ lowerVECTOR_SHUFFLE_VSHF()

Definition at line 2994 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::EVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm_unreachable, and llvm::SmallVectorTemplateCommon< T, typename >::size().

◆ performANDCombine()

Definition at line 537 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::cast(), llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getVTList(), llvm::MipsSubtarget::hasMSA(), llvm::Log2(), N, and SDValue().

◆ performDSPShiftCombine()

Definition at line 900 of file MipsSEISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getZExtValue(), llvm::MipsSubtarget::hasDSP(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::MipsSubtarget::isLittle(), N, Opc, and SDValue().

Referenced by performSHLCombine(), performSRACombine(), and performSRLCombine().

◆ performMULCombine()

◆ performORCombine()

Definition at line 652 of file MipsSEISelLowering.cpp.

References llvm::ISD::AND, assert(), Cond, llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MipsSubtarget::hasMSA(), isBitwiseInverse(), llvm::MipsSubtarget::isLittle(), isVSplat(), N, SDValue(), and llvm::ISD::VSELECT.

◆ performSETCCCombine()

◆ performSHLCombine()

◆ performSRACombine()

Definition at line 948 of file MipsSEISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::cast(), llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasDSPR2(), llvm::MipsSubtarget::hasMSA(), N, performDSPShiftCombine(), SDValue(), and llvm::ISD::SHL.

Referenced by llvm::MipsSETargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ performSRLCombine()

◆ performVSELECTCombine()

◆ performXORCombine()

◆ shouldTransformMulToShiftsAddsSubs()

Definition at line 772 of file MipsSEISelLowering.cpp.

References llvm::BitWidth, llvm::CallingConv::C, llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::SelectionDAG::getContext(), llvm::TargetLoweringBase::getRegisterType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MipsSubtarget::isABI_O32(), llvm::APInt::isNegative(), llvm::APInt::isPowerOf2(), llvm::APInt::logBase2(), MaxSteps, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by performMULCombine().

◆ truncateVecElts()

◆ NoDPLoadStore

cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts")) ( "mno-ldc1-sdc1" , cl::init(false) , cl::desc("Expand double precision loads and " "stores to their single precision " "counterparts") ) static

◆ UseMipsTailCalls

cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false)) ( "mips-tail-calls" , cl::Hidden , cl::desc("MIPS: permit tail calls.") , cl::init(false) ) static