LLVM: lib/Target/X86/X86ISelLoweringCall.cpp File Reference (original) (raw)
This file implements the lowering of LLVM calls to DAG nodes. More...
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| Macros | |
|---|---|
| #define | DEBUG_TYPE "x86-isel" |
| Functions | |
|---|---|
| STATISTIC (NumTailCalls, "Number of tail calls") | |
| static void | errorUnsupported (SelectionDAG &DAG, const SDLoc &dl, const char *Msg) |
| Call this when the user attempts to do something unsupported, like returning a double without SSE2 enabled on x86_64. | |
| static bool | shouldDisableRetRegFromCSR (CallingConv::ID CC) |
| Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the return registers. | |
| static bool | shouldDisableArgRegFromCSR (CallingConv::ID CC) |
| Returns true if a CC can dynamically exclude a register from the list of callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on the parameters. | |
| static std::pair< MVT, unsigned > | handleMaskRegisterForCallingConv (unsigned NumElts, CallingConv::ID CC, const X86Subtarget &Subtarget) |
| static void | getMaxByValAlign (Type *Ty, Align &MaxAlign) |
| Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. | |
| static bool | isBitAligned (Align Alignment, uint64_t SizeInBits) |
| static bool | hasStackGuardSlotTLS (const Triple &TargetTriple) |
| static Constant * | SegmentOffset (IRBuilderBase &IRB, int Offset, unsigned AddressSpace) |
| static SDValue | lowerMasksToReg (const SDValue &ValArg, const EVT &ValLoc, const SDLoc &DL, SelectionDAG &DAG) |
| Lowers masks values (v*i1) to the local register values. | |
| static void | Passv64i1ArgInRegs (const SDLoc &DL, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl< std::pair< Register, SDValue > > &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) |
| Breaks v64i1 value into two registers and adds the new node to the DAG. | |
| static SDValue | getv64i1Argument (CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &DL, const X86Subtarget &Subtarget, SDValue *InGlue=nullptr) |
| Reads two 32 bit registers and creates a 64 bit mask value. | |
| static SDValue | lowerRegToMasks (const SDValue &ValArg, const EVT &ValVT, const EVT &ValLoc, const SDLoc &DL, SelectionDAG &DAG) |
| The function will lower a register of various sizes (8/16/32/64) to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1) | |
| static SDValue | getPopFromX87Reg (SelectionDAG &DAG, SDValue Chain, const SDLoc &dl, Register Reg, EVT VT, SDValue Glue) |
| template<typename T> | |
| static bool | hasCalleePopSRet (const SmallVectorImpl< T > &Args, const X86Subtarget &Subtarget) |
| Determines whether Args, either a set of outgoing arguments to a call, or a set of incoming args of a call, contains an sret pointer that the callee pops. | |
| static SDValue | CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) |
| Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute. | |
| static bool | canGuaranteeTCO (CallingConv::ID CC) |
| Return true if the calling convention is one that we can guarantee TCO for. | |
| static bool | mayTailCallThisCC (CallingConv::ID CC) |
| Return true if we might ever do TCO for calls with this calling convention. | |
| static bool | shouldGuaranteeTCO (CallingConv::ID CC, bool GuaranteedTailCallOpt) |
| Return true if the function is being made into a tailcall target by changing its ABI. | |
| static ArrayRef< MCPhysReg > | get64BitArgumentGPRs (CallingConv::ID CallConv, const X86Subtarget &Subtarget) |
| static ArrayRef< MCPhysReg > | get64BitArgumentXMMs (MachineFunction &MF, CallingConv::ID CallConv, const X86Subtarget &Subtarget) |
| static bool | isSortedByValueNo (ArrayRef< CCValAssign > ArgLocs) |
| static SDValue | EmitTailCallStoreRetAddr (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &dl) |
| Emit a store of the return address if tail call optimization is performed and it is required (FPDiff!=0). | |
| static bool | MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const X86InstrInfo *TII, const CCValAssign &VA) |
| Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack. | |
| static bool | mayBeSRetTailCallCompatible (const TargetLowering::CallLoweringInfo &CLI, Register CallerSRetReg) |
This file implements the lowering of LLVM calls to DAG nodes.
Definition in file X86ISelLoweringCall.cpp.
◆ DEBUG_TYPE
#define DEBUG_TYPE "x86-isel"
◆ canGuaranteeTCO()
◆ CreateCopyOfByValArgument()
◆ EmitTailCallStoreRetAddr()
◆ errorUnsupported()
◆ get64BitArgumentGPRs()
◆ get64BitArgumentXMMs()
◆ getMaxByValAlign()
| void getMaxByValAlign ( Type * Ty, Align & MaxAlign ) | static |
|---|
◆ getPopFromX87Reg()
◆ getv64i1Argument()
Reads two 32 bit registers and creates a 64 bit mask value.
Parameters
| VA | The current 32 bit value that need to be assigned. | |
|---|---|---|
| NextVA | The next 32 bit value that need to be assigned. | |
| Root | The parent DAG node. | |
| [in,out] | InGlue | Represents SDvalue in the parent DAG node for glue purposes. In the case the DAG is already using physical register instead of virtual, we should glue our new SDValue to InGlue SDvalue. |
Returns
a new SDvalue of size 64bit.
Definition at line 1014 of file X86ISelLoweringCall.cpp.
References llvm::MachineFunction::addLiveIn(), assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocReg(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isRegLoc(), llvm::Lo, and Reg.
◆ handleMaskRegisterForCallingConv()
◆ hasCalleePopSRet()
◆ hasStackGuardSlotTLS()
◆ isBitAligned()
◆ isSortedByValueNo()
◆ lowerMasksToReg()
◆ lowerRegToMasks()
◆ MatchingStackOffset()
Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
Definition at line 2681 of file X86ISelLoweringCall.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertZext, llvm::cast(), llvm::ISD::CopyFromReg, llvm::dyn_cast(), llvm::ISD::FrameIndex, llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::FrameIndexSDNode::getIndex(), llvm::CCValAssign::getLocVT(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::MachineFrameInfo::isImmutableObjectIndex(), llvm::MachineFrameInfo::isObjectSExt(), llvm::MachineFrameInfo::isObjectZExt(), llvm::Register::isVirtual(), MRI, llvm::Offset, TII, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
◆ mayBeSRetTailCallCompatible()
◆ mayTailCallThisCC()
◆ Passv64i1ArgInRegs()
◆ SegmentOffset()
◆ shouldDisableArgRegFromCSR()
◆ shouldDisableRetRegFromCSR()
◆ shouldGuaranteeTCO()
◆ STATISTIC()
| STATISTIC | ( | NumTailCalls | , |
|---|---|---|---|
| "Number of tail calls" | ) |