LLVM: llvm::X86InstrInfo Class Reference (original) (raw)

#include "[Target/X86/X86InstrInfo.h](X86InstrInfo%5F8h%5Fsource.html)"

Definition at line 224 of file X86InstrInfo.h.

◆ accumulateInstrSeqToRootLatency()

When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency.

Parameters

Definition at line 690 of file X86InstrInfo.h.

◆ analyzeBranch()

◆ analyzeBranchPredicate()

Definition at line 4015 of file X86InstrInfo.cpp.

References assert(), Cond, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), llvm::drop_begin(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), llvm::MachineOperand::isIdenticalTo(), MBB, MI, llvm::reverse(), and TRI.

◆ analyzeCompare()

◆ areLoadsFromSameBasePtr()

◆ breakPartialRegDependency()

Definition at line 7168 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::get(), llvm::getX86SubSuperRegister(), llvm::X86II::hasNewDataDest(), llvm::RegState::ImplicitDefine, MI, Opc, TRI, and llvm::RegState::Undef.

◆ buildClearRegister()

Definition at line 10811 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), DL, llvm::get(), getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::getX86SubSuperRegister(), MBB, TRI, and llvm::RegState::Undef.

◆ buildOutlinedFrame()

◆ canInsertSelect()

◆ canMakeTailCallConditional()

Definition at line 3711 of file X86InstrInfo.cpp.

References assert(), llvm::TargetMachine::getCodeModel(), llvm::getImm(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getTCReturnAddrDelta(), llvm::MachineFunction::hasWinCFI(), llvm::CodeModel::Kernel, llvm::X86::LAST_VALID_COND, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by replaceBranchWithTailCall().

◆ classifyLEAReg()

Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.

This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.

Reference parameters are set to indicate how caller should add this operand to the LEA instruction.

Definition at line 1148 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::LiveRange::Segment::end, llvm::get(), llvm::SlotIndex::getBaseIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineFunction::getRegInfo(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), llvm::getX86SubSuperRegister(), llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::Register::isPhysical(), llvm::Register::isValid(), llvm::Register::isVirtual(), MI, Opc, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), SubReg, and llvm::RegState::Undef.

Referenced by convertToThreeAddress().

◆ commuteInstructionImpl()

Definition at line 2294 of file X86InstrInfo.cpp.

References llvm::MachineInstr::addOperand(), assert(), CASE_ND, llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::countr_zero(), llvm::MachineOperand::CreateImm(), FROM_TO_SIZE, llvm::get(), getCommutedVPERMV3Opcode(), llvm::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::getImm(), llvm::MachineInstr::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::X86::getSwappedVCMPImm(), llvm::X86::getSwappedVPCMPImm(), llvm::X86::getSwappedVPCOMImm(), isCommutableVPERMV3Instruction(), llvm_unreachable, MI, Opc, llvm::popcount(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and Size.

◆ convertToThreeAddress()

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.

When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

FIXME: Support these similar to ADD8ri/ADD16ri*.

Definition at line 1409 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), CASE_NF, classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::get(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::LiveVariables::getVarInfo(), hasLiveCondCodeDef(), I, llvm::isInt(), isTruncatedShiftCountForLEA(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, MBB, MI, Opc, llvm::LiveVariables::replaceKillInstruction(), and llvm::LiveIntervals::ReplaceMachineInstrInMaps().

◆ copyPhysReg()

Definition at line 4307 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), CopyToFromAsymmetricReg(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), isHReg(), LLVM_DEBUG, MBB, MI, Opc, llvm::report_fatal_error(), and TRI.

◆ decomposeMachineOperandsTargetFlags()

◆ describeLoadedValue()

Definition at line 10202 of file X86InstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::DIExpression::appendExt(), llvm::DIExpression::appendOffset(), assert(), contains(), llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), llvm::MDNode::get(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::isFI(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), MI, llvm::Offset, and TRI.

◆ expandPostRAPseudo()

Definition at line 6166 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandMOVSHP(), expandNOVLXLoad(), expandNOVLXStore(), expandSHXDROT(), expandXorFP(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::getRegState(), llvm::RegState::ImplicitDefine, MBB, MI, Opc, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), TRI, and llvm::RegState::Undef.

◆ findCommutedOpIndices()

Returns true iff the routine could find two commutable operands in the given machine instruction.

The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.

For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.

Definition at line 2807 of file X86InstrInfo.cpp.

References llvm::X86II::EncodingMask, llvm::X86II::EVEX, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::getFMA3Group(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), MI, and llvm::MCOI::TIED_TO.

◆ foldImmediate()

◆ foldMemoryOperandImpl() [1/3]

Fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).

If folding happens, it is likely that the referenced instruction has been changed.

Returns

true on success.

Definition at line 7618 of file X86InstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineOperand::CreateFI(), foldMemoryOperandImpl(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::X86::getNonNDVariant(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineOperand::getSubReg(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), MI, NoFusing, Opc, shouldPreventUndefRegUpdateMemFold(), Size, and SubReg.

Referenced by foldMemoryOperandImpl(), foldMemoryOperandImpl(), and foldMemoryOperandImpl().

◆ foldMemoryOperandImpl() [2/3]

Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Definition at line 8133 of file X86InstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, AbstractManglingParser< Derived, Alloc >::Ops, llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), llvm::CallingConv::C, llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), FOLD_BROADCAST, foldMemoryOperandImpl(), llvm::FixedVectorType::get(), llvm::get(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::Type::getFP128Ty(), llvm::MachineFunction::getFunction(), llvm::Type::getHalfTy(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::X86II::hasNewDataDest(), llvm::MachineInstr::hasOneMemOperand(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), I, isLoadFromStackSlot(), llvm::isMemInstrWithGOTPCREL(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::MachineOperand::isReg(), llvm::CodeModel::Large, llvm::MachineInstr::memoperands_begin(), MI, NoFusing, llvm::MachineInstr::operands_begin(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), shouldPreventUndefRegUpdateMemFold(), and X86EnableAPXForRelocation.

◆ foldMemoryOperandImpl() [3/3]

Definition at line 7488 of file X86InstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::X86::AddrDisp, llvm::X86::AddrNumOperands, foldMemoryOperandImpl(), fuseInst(), fuseTwoAddrInst(), llvm::MachineFunction::getFunction(), llvm::X86::getNonNDVariant(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasMinSize(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), I, llvm::Register::isPhysical(), llvm::lookupFoldTable(), llvm::lookupTwoAddrFoldTable(), MI, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTTPOFF, Opc, printFailMsgforFold(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), shouldPreventUndefRegUpdateMemFold(), Size, llvm::ArrayRef< T >::size(), llvm::TB_ALIGN_MASK, llvm::TB_ALIGN_SHIFT, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and TRI.

◆ genAlternativeCodeSequence()

◆ getAddrModeFromMemoryOp()

Definition at line 4555 of file X86InstrInfo.cpp.

References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and TRI.

Referenced by verifyInstruction().

◆ getConstValDefinedInReg()

◆ getExecutionDomain()

◆ getExecutionDomainCustom()

◆ getFMA3OpcodeToCommuteOperands()

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.

It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.

The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1

Definition at line 2085 of file X86InstrInfo.cpp.

References assert(), llvm::X86InstrFMA3Group::get132Opcode(), llvm::X86InstrFMA3Group::get213Opcode(), llvm::X86InstrFMA3Group::get231Opcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm_unreachable, MI, and Opc.

Referenced by commuteInstructionImpl().

◆ getFrameAdjustment()

Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g.

by pushes, or inside the callee).

Definition at line 260 of file X86InstrInfo.h.

References assert(), and I.

Referenced by getSPAdjust().

◆ getFrameIndexOperands()

◆ getGlobalBaseReg()

◆ getJumpTableIndex()

◆ getMachineCombinerPatterns()

◆ getMemOperandsWithOffsetWidth()

Definition at line 4680 of file X86InstrInfo.cpp.

References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::Offset, llvm::LocationSize::precise(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

◆ getNop()

◆ getOpcodeAfterMemoryUnfold()

◆ getOutliningCandidateInfo()

◆ getOutliningTypeImpl()

◆ getPartialRegUpdateClearance()

◆ getRegClass()

◆ getRegisterInfo()

◆ getSerializableDirectMachineOperandTargetFlags()

◆ getSPAdjust()

◆ getUndefRegClearance()

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads.

This catches the VCVTSI2SD family of instructions:

vcvtsi2sdq rax, undef xmm0, xmm14

We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:

vxorps undef xmm1, undef xmm1, xmm1

Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.

Definition at line 7159 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::Register::isPhysical(), MI, TRI, and UndefRegClearance.

◆ hasCommutePreference()

◆ hasHighOperandLatency()

◆ hasLiveCondCodeDef()

True if MI has a condition code def, e.g.

True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

EFLAGS, that is not marked dead.

Definition at line 999 of file X86InstrInfo.cpp.

References MI.

Referenced by convertToThreeAddress().

◆ hasLockPrefix()

◆ hasReassociableOperands()

◆ insertBranch()

Definition at line 4107 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, llvm::X86::COND_E_AND_NP, llvm::X86::COND_NE, llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP, llvm::X86::COND_P, llvm::Count, DL, llvm::get(), getFallThroughMBB(), llvm::getImm(), MBB, and TBB.

◆ insertNoop()

◆ insertOutlinedCall()

◆ insertSelect()

Definition at line 4202 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::X86::getCMovOpcode(), llvm::getImm(), I, MBB, MRI, Opc, and TRI.

◆ isAssociativeAndCommutative()

◆ isCoalescableExtInstr()

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.

That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Definition at line 111 of file X86InstrInfo.cpp.

References llvm_unreachable, and MI.

◆ isCopyInstrImpl()

◆ isDataInvariant()

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands.

Instructions are considered data invariant even if they set EFLAGS.

A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.

FIXME: This should become part of our instruction tables.

Definition at line 161 of file X86InstrInfo.cpp.

References isLEA(), isNOT(), and MI.

◆ isDataInvariantLoad()

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands.

For example, if the latency of the instruction is dependent on the particular bits set in any of the registers or any of the bits loaded from memory.

Instructions are considered data invariant even if they set EFLAGS.

A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.

FIXME: This should become part of our instruction tables.

Definition at line 228 of file X86InstrInfo.cpp.

References MI.

◆ isFunctionSafeToOutlineFrom()

◆ isHighLatencyDef()

◆ isLoadFromStackSlot() [1/2]

◆ isLoadFromStackSlot() [2/2]

◆ isLoadFromStackSlotPostFE()

◆ isReMaterializableImpl()

Definition at line 758 of file X86InstrInfo.cpp.

References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineFunction::getRegInfo(), llvm::TargetInstrInfo::isReMaterializableImpl(), llvm_unreachable, MI, MRI, regIsPICBase(), and ReMatPICStubLoad.

◆ isSafeToMoveRegClassDefs()

◆ isSchedulingBoundary()

◆ isStoreToStackSlot() [1/2]

◆ isStoreToStackSlot() [2/2]

◆ isStoreToStackSlotPostFE()

◆ isSubregFoldable()

Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).

Definition at line 488 of file X86InstrInfo.h.

◆ isUnconditionalTailCall()

◆ loadRegFromStackSlot()

Definition at line 4810 of file X86InstrInfo.cpp.

References llvm::addFrameReference(), assert(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachineFunction::getFrameInfo(), getLoadRegOpcode(), llvm::MachineFrameInfo::getObjectSize(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, Opc, and llvm::MachineInstrBuilder::setMIFlag().

◆ loadStoreTileReg()

Definition at line 4749 of file X86InstrInfo.cpp.

References llvm::addFrameReference(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrIndexReg, llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm_unreachable, MBB, MI, Opc, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setReg().

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

◆ optimizeCompareInstr()

Check if there exists an earlier instruction that operates on the same source operands and sets eflags in the same way as CMP and remove CMP if possible.

Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Definition at line 5286 of file X86InstrInfo.cpp.

References assert(), llvm::BitWidth, CASE_ND, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_S, llvm::MachineInstr::dropDebugNumber(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), findRedundantFlagInstr(), FROM_TO, llvm::get(), llvm::X86::getCondFromMI(), llvm::APInt::getMaxValue(), llvm::X86::getNFVariant(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), getSwappedCondition(), llvm::isAddMemInstrWithRelocation(), isDefConvertible(), llvm::Register::isPhysical(), isUseDefConvertible(), llvm_unreachable, llvm::make_range(), MBB, MI, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Sub, llvm::Successor, llvm::MachineBasicBlock::successors(), TRI, and X86EnableAPXForRelocation.

◆ preservesZeroValueInReg()

◆ reMaterialize()

Definition at line 961 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm_unreachable, llvm::MachineBasicBlock::LQR_Dead, MBB, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::substituteRegister(), and TRI.

◆ removeBranch()

◆ replaceBranchWithTailCall()

Definition at line 3755 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::CallingConv::C, canMakeTailCallConditional(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, llvm::get(), llvm::X86::getCondFromBranch(), llvm::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), I, llvm::RegState::Implicit, MBB, Opc, and llvm::SmallVectorTemplateCommon< T, typename >::size().

◆ reverseBranchCondition()

◆ setExecutionDomain()

◆ setExecutionDomainCustom()

◆ setFrameAdjustment()

Sets the stack pointer adjustment made inside the frame made up by this instruction.

Definition at line 269 of file X86InstrInfo.h.

References assert(), and I.

◆ setSpecialOperandAttr()

◆ shouldScheduleLoadsNear()

This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Definition at line 8970 of file X86InstrInfo.cpp.

References assert(), llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), and llvm::MVT::SimpleTy.

◆ storeRegToStackSlot()

Definition at line 4786 of file X86InstrInfo.cpp.

References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), getStoreRegOpcode(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, Opc, and llvm::MachineInstrBuilder::setMIFlag().

◆ unfoldMemoryOperand() [1/2]

Definition at line 8545 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::RegState::Define, DL, extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), getLoadRegOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), llvm::getUndefRegState(), I, llvm::RegState::Implicit, llvm::isAligned(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::RegState::Kill, llvm_unreachable, llvm::lookupUnfoldTable(), MI, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), llvm::TB_BCAST_MASK, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.

◆ unfoldMemoryOperand() [2/2]

Definition at line 8692 of file X86InstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::X86::AddrNumOperands, llvm::append_range(), llvm::cast(), extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), I, llvm::isAligned(), llvm::isNullConstant(), llvm_unreachable, llvm::lookupUnfoldTable(), N, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SelectionDAG::setNodeMemRefs(), llvm::TB_BCAST_MASK, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.

◆ useMachineCombiner()

◆ verifyInstruction()

The documentation for this class was generated from the following files:

• lib/Target/X86/X86InstrInfo.h
• lib/Target/X86/X86InstrInfo.cpp