LLVM: llvm::SIMachineFunctionInfo Class Reference (original) (raw)

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load. More...

#include "[Target/AMDGPU/SIMachineFunctionInfo.h](SIMachineFunctionInfo%5F8h%5Fsource.html)"

Public Member Functions
Register getVGPRForAGPRCopy () const
void setVGPRForAGPRCopy (Register NewVGPRForAGPRCopy)
bool isCalleeSavedReg (const MCPhysReg *CSRegs, MCPhysReg Reg) const
void setMaskForVGPRBlockOps (Register RegisterBlock, uint32_t Mask)
uint32_t getMaskForVGPRBlockOps (Register RegisterBlock) const
bool hasMaskForVGPRBlockOps (Register RegisterBlock) const
SIMachineFunctionInfo (const SIMachineFunctionInfo &MFI)=default
SIMachineFunctionInfo (const Function &F, const GCNSubtarget *STI)
MachineFunctionInfo * clone (BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool initializeBaseYamlFields (const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void reserveWWMRegister (Register Reg)
bool isWWMReg (Register Reg) const
void updateNonWWMRegMask (BitVector &RegMask)
BitVector getNonWWMRegMask () const
void clearNonWWMRegAllocMask ()
SIModeRegisterDefaults getMode () const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes (int FrameIndex) const
ArrayRef< Register > getSGPRSpillVGPRs () const
ArrayRef< Register > getSGPRSpillPhysVGPRs () const
const WWMSpillsMap & getWWMSpills () const
const ReservedRegSet & getWWMReservedRegs () const
bool isWWMReservedRegister (Register Reg) const
bool isWholeWaveFunction () const
ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills () const
GCNUserSGPRUsageInfo & getUserSGPRInfo ()
const GCNUserSGPRUsageInfo & getUserSGPRInfo () const
void addToPrologEpilogSGPRSpills (Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
bool hasPrologEpilogSGPRSpillEntry (Register Reg) const
Register getScratchSGPRCopyDstReg (Register Reg) const
void getAllScratchSGPRCopyDstRegs (SmallVectorImpl< Register > &Regs) const
bool checkIndexInPrologEpilogSGPRSpills (int FI) const
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo (Register Reg) const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes (int FrameIndex) const
void setFlag (Register Reg, uint8_t Flag)
bool checkFlag (Register Reg, uint8_t Flag) const
bool hasVRegFlags ()
void allocateWWMSpill (MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
void splitWWMSpillRegisters (MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs () const
Register getSGPRForEXECCopy () const
void setSGPRForEXECCopy (Register Reg)
ArrayRef< MCPhysReg > getVGPRSpillAGPRs () const
MCPhysReg getVGPRToAGPRSpill (int FrameIndex, unsigned Lane) const
void setVGPRToAGPRSpillDead (int FrameIndex)
void shiftWwmVGPRsToLowestRange (MachineFunction &MF, SmallVectorImpl< Register > &WWMVGPRs, BitVector &SavedVGPRs)
bool allocateSGPRSpillToVGPRLane (MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)
bool allocateVGPRSpillToAGPR (MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
bool removeDeadFrameIndices (MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
int getScavengeFI (MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
std::optional< int > getOptionalScavengeFI () const
unsigned getBytesInStackArgArea () const
void setBytesInStackArgArea (unsigned Bytes)
bool isDynamicVGPREnabled () const
unsigned getDynamicVGPRBlockSize () const
unsigned getScratchReservedForDynamicVGPRs () const
void setScratchReservedForDynamicVGPRs (unsigned SizeInBytes)
Register addPrivateSegmentBuffer (const SIRegisterInfo &TRI)
Register addDispatchPtr (const SIRegisterInfo &TRI)
Register addQueuePtr (const SIRegisterInfo &TRI)
Register addKernargSegmentPtr (const SIRegisterInfo &TRI)
Register addDispatchID (const SIRegisterInfo &TRI)
Register addFlatScratchInit (const SIRegisterInfo &TRI)
Register addPrivateSegmentSize (const SIRegisterInfo &TRI)
Register addImplicitBufferPtr (const SIRegisterInfo &TRI)
Register addLDSKernelId ()
SmallVectorImpl< MCRegister > * addPreloadedKernArg (const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
Register addReservedUserSGPR ()
Increment user SGPRs used for padding the argument list only.
Register addWorkGroupIDX ()
Register addWorkGroupIDY ()
Register addWorkGroupIDZ ()
Register addWorkGroupInfo ()
bool hasLDSKernelId () const
void setWorkItemIDX (ArgDescriptor Arg)
void setWorkItemIDY (ArgDescriptor Arg)
void setWorkItemIDZ (ArgDescriptor Arg)
Register addPrivateSegmentWaveByteOffset ()
void setPrivateSegmentWaveByteOffset (Register Reg)
bool hasWorkGroupIDX () const
bool hasWorkGroupIDY () const
bool hasWorkGroupIDZ () const
bool hasWorkGroupInfo () const
bool hasPrivateSegmentWaveByteOffset () const
bool hasWorkItemIDX () const
bool hasWorkItemIDY () const
bool hasWorkItemIDZ () const
bool hasImplicitArgPtr () const
AMDGPUFunctionArgInfo & getArgInfo ()
const AMDGPUFunctionArgInfo & getArgInfo () const
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue (AMDGPUFunctionArgInfo::PreloadedValue Value) const
MCRegister getPreloadedReg (AMDGPUFunctionArgInfo::PreloadedValue Value) const
unsigned getGITPtrHigh () const
Register getGITPtrLoReg (const MachineFunction &MF) const
uint32_t get32BitAddressHighBits () const
unsigned getNumUserSGPRs () const
unsigned getNumPreloadedSGPRs () const
unsigned getNumKernargPreloadedSGPRs () const
unsigned getNumWaveDispatchSGPRs () const
void setNumWaveDispatchSGPRs (unsigned Count)
unsigned getNumWaveDispatchVGPRs () const
void setNumWaveDispatchVGPRs (unsigned Count)
Register getPrivateSegmentWaveByteOffsetSystemSGPR () const
Register getScratchRSrcReg () const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
void setScratchRSrcReg (Register Reg)
Register getFrameOffsetReg () const
void setFrameOffsetReg (Register Reg)
void setStackPtrOffsetReg (Register Reg)
void setLongBranchReservedReg (Register Reg)
Register getStackPtrOffsetReg () const
Register getLongBranchReservedReg () const
Register getQueuePtrUserSGPR () const
Register getImplicitBufferPtrUserSGPR () const
bool hasSpilledSGPRs () const
void setHasSpilledSGPRs (bool Spill=true)
bool hasSpilledVGPRs () const
void setHasSpilledVGPRs (bool Spill=true)
bool hasNonSpillStackObjects () const
void setHasNonSpillStackObjects (bool StackObject=true)
bool isStackRealigned () const
void setIsStackRealigned (bool Realigned=true)
unsigned getNumSpilledSGPRs () const
unsigned getNumSpilledVGPRs () const
void addToSpilledSGPRs (unsigned num)
void addToSpilledVGPRs (unsigned num)
unsigned getPSInputAddr () const
unsigned getPSInputEnable () const
bool isPSInputAllocated (unsigned Index) const
void markPSInputAllocated (unsigned Index)
void markPSInputEnabled (unsigned Index)
bool returnsVoid () const
void setIfReturnsVoid (bool Value)
std::pair< unsigned, unsigned > getFlatWorkGroupSizes () const
unsigned getMinFlatWorkGroupSize () const
unsigned getMaxFlatWorkGroupSize () const
std::pair< unsigned, unsigned > getWavesPerEU () const
unsigned getMinWavesPerEU () const
unsigned getMaxWavesPerEU () const
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV (const AMDGPUTargetMachine &TM)
unsigned getOccupancy () const
unsigned getMinAllowedOccupancy () const
void limitOccupancy (const MachineFunction &MF)
void limitOccupancy (unsigned Limit)
void increaseOccupancy (const MachineFunction &MF, unsigned Limit)
unsigned getMaxMemoryClusterDWords () const
unsigned getMinNumAGPRs () const
bool selectAGPRFormMFMA (unsigned NumRegs) const
Return true if an MFMA that requires at least NumRegs should select to the AGPR form, instead of the VGPR form.
bool mayUseAGPRs (const Function &F) const
SmallVector< unsigned > getMaxNumWorkGroups () const
unsigned getMaxNumWorkGroupsX () const
unsigned getMaxNumWorkGroupsY () const
unsigned getMaxNumWorkGroupsZ () const
AMDGPU::ClusterDimsAttr getClusterDims () const
Public Member Functions inherited from llvm::AMDGPUMachineFunction
AMDGPUMachineFunction (const Function &F, const AMDGPUSubtarget &ST)
uint64_t getExplicitKernArgSize () const
Align getMaxKernArgAlign () const
uint32_t getLDSSize () const
uint32_t getGDSSize () const
void recordNumNamedBarriers (uint32_t GVAddr, unsigned BarCnt)
uint32_t getNumNamedBarriers () const
bool isEntryFunction () const
bool isModuleEntryFunction () const
bool isChainFunction () const
bool isBottomOfStack () const
bool hasNoSignedZerosFPMath () const
bool isMemoryBound () const
bool needsWaveLimiter () const
bool hasInitWholeWave () const
void setInitWholeWave ()
unsigned allocateLDSGlobal (const DataLayout &DL, const GlobalVariable &GV)
unsigned allocateLDSGlobal (const DataLayout &DL, const GlobalVariable &GV, Align Trailing)
Align getDynLDSAlign () const
void setDynLDSAlign (const Function &F, const GlobalVariable &GV)
void setUsesDynamicLDS (bool DynLDS)
bool isDynamicLDSUsed () const
Public Member Functions inherited from llvm::MachineFunctionInfo
virtual ~MachineFunctionInfo ()
Static Public Attributes
static bool MFMAVGPRForm = false
Friends
class GCNTargetMachine
Additional Inherited Members
Static Public Member Functions inherited from llvm::AMDGPUMachineFunction
static std::optional< uint32_t > getLDSKernelIdMetadata (const Function &F)
static std::optional< uint32_t > getLDSAbsoluteAddress (const GlobalValue &GV)
Static Public Member Functions inherited from llvm::MachineFunctionInfo
template<typename FuncInfoTy, typename SubtargetTy = TargetSubtargetInfo>
static FuncInfoTy * create (BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)
Factory function: default behavior is to call new using the supplied allocator.
template
static Ty * create (BumpPtrAllocator &Allocator, const Ty &MFI)
Protected Attributes inherited from llvm::AMDGPUMachineFunction
uint64_t ExplicitKernArgSize = 0
Align MaxKernArgAlign
uint32_t LDSSize = 0
Number of bytes in the LDS that are being used.
uint32_t GDSSize = 0
uint32_t StaticLDSSize = 0
Number of bytes in the LDS allocated statically.
uint32_t StaticGDSSize = 0
Align DynLDSAlign
Align for dynamic shared memory if any.
bool UsesDynamicLDS = false
uint32_t NumNamedBarriers = 0
bool IsEntryFunction = false
bool IsModuleEntryFunction = false
bool IsChainFunction = false
bool NoSignedZerosFPMath = false
bool MemoryBound = false
bool WaveLimiter = false
bool HasInitWholeWave = false

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load.

Definition at line 416 of file SIMachineFunctionInfo.h.

◆ SIMachineFunctionInfo() [2/2]

Definition at line 50 of file SIMachineFunctionInfo.cpp.

References A(), llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_PS, llvm::AMDGPUMachineFunction::AMDGPUMachineFunction(), assert(), llvm::StringRef::consumeInteger(), llvm::ArgDescriptor::createRegister(), llvm::DefaultMemoryClusterDWordsLimit, llvm::StringRef::empty(), F, llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo, llvm::AMDGPU::ClusterDimsAttr::get(), llvm::AMDGPU::getDynamicVGPRBlockSize(), llvm::AMDGPU::getInitialPSInputAddr(), llvm::AMDGPU::getIntegerPairAttribute(), llvm::AMDGPUMachineFunction::getLDSSize(), getTM(), llvm::AMDGPUSubtarget::GFX9, llvm::AMDGPU::isChainCC(), llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isGraphics(), llvm::AMDGPUMachineFunction::MaxKernArgAlign, and llvm::CallingConv::SPIR_KERNEL.

◆ addDispatchID()

◆ addDispatchPtr()

◆ addFlatScratchInit()

◆ addImplicitBufferPtr()

◆ addKernargSegmentPtr()

◆ addLDSKernelId()

Register SIMachineFunctionInfo::addLDSKernelId ( )

◆ addPreloadedKernArg()

◆ addPrivateSegmentBuffer()

◆ addPrivateSegmentSize()

◆ addPrivateSegmentWaveByteOffset()

Register llvm::SIMachineFunctionInfo::addPrivateSegmentWaveByteOffset ( ) inline

◆ addQueuePtr()

◆ addReservedUserSGPR()

Register llvm::SIMachineFunctionInfo::addReservedUserSGPR ( ) inline

◆ addToPrologEpilogSGPRSpills()

◆ addToSpilledSGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledSGPRs ( unsigned num) inline

◆ addToSpilledVGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledVGPRs ( unsigned num) inline

◆ addWorkGroupIDX()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDX ( ) inline

◆ addWorkGroupIDY()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDY ( ) inline

◆ addWorkGroupIDZ()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDZ ( ) inline

◆ addWorkGroupInfo()

Register llvm::SIMachineFunctionInfo::addWorkGroupInfo ( ) inline

◆ allocateSGPRSpillToVGPRLane()

bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane ( MachineFunction & MF,
int FI,
bool SpillToPhysVGPRLane = false,
bool IsPrologEpilog = false )

◆ allocateVGPRSpillToAGPR()

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.

Either AGPR is spilled to VGPR to vice versa. Returns true if a FI can be eliminated completely.

Definition at line 502 of file SIMachineFunctionInfo.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegisters(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineFrameInfo::isSpillSlotObjectIndex(), MRI, llvm::BitVector::push_back(), llvm::BitVector::resize(), llvm::BitVector::set(), llvm::BitVector::setBitsInMask(), Size, and TRI.

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ allocateWWMSpill()

◆ checkFlag()

◆ checkIndexInPrologEpilogSGPRSpills()

bool llvm::SIMachineFunctionInfo::checkIndexInPrologEpilogSGPRSpills ( int FI) const inline

◆ clearNonWWMRegAllocMask()

void llvm::SIMachineFunctionInfo::clearNonWWMRegAllocMask ( ) inline

◆ clone()

◆ get32BitAddressHighBits()

uint32_t llvm::SIMachineFunctionInfo::get32BitAddressHighBits ( ) const inline

◆ getAGPRSpillVGPRs()

ArrayRef< MCPhysReg > llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs ( ) const inline

◆ getAllScratchSGPRCopyDstRegs()

◆ getArgInfo() [1/2]

◆ getArgInfo() [2/2]

◆ getBytesInStackArgArea()

unsigned llvm::SIMachineFunctionInfo::getBytesInStackArgArea ( ) const inline

◆ getClusterDims()

◆ getDynamicVGPRBlockSize()

unsigned llvm::SIMachineFunctionInfo::getDynamicVGPRBlockSize ( ) const inline

◆ getFlatWorkGroupSizes()

std::pair< unsigned, unsigned > llvm::SIMachineFunctionInfo::getFlatWorkGroupSizes ( ) const inline

Returns

A pair of default/requested minimum/maximum flat work group sizes for this function.

Definition at line 1150 of file SIMachineFunctionInfo.h.

◆ getFrameOffsetReg()

Register llvm::SIMachineFunctionInfo::getFrameOffsetReg ( ) const inline

Definition at line 1038 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlotsImpl(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::SIFrameLowering::emitCSRSpillRestores(), llvm::SIFrameLowering::emitCSRSpillStores(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getFrameRegister(), llvm::SIRegisterInfo::getReservedRegs(), and llvm::SIRegisterInfo::spillSGPR().

◆ getGITPtrHigh()

unsigned llvm::SIMachineFunctionInfo::getGITPtrHigh ( ) const inline

◆ getGITPtrLoReg()

◆ getGWSPSV()

◆ getImplicitBufferPtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getImplicitBufferPtrUserSGPR ( ) const inline

◆ getLongBranchReservedReg()

Register llvm::SIMachineFunctionInfo::getLongBranchReservedReg ( ) const inline

◆ getMaskForVGPRBlockOps()

uint32_t llvm::SIMachineFunctionInfo::getMaskForVGPRBlockOps ( Register RegisterBlock) const inline

◆ getMaxFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMaxFlatWorkGroupSize ( ) const inline

◆ getMaxMemoryClusterDWords()

unsigned llvm::SIMachineFunctionInfo::getMaxMemoryClusterDWords ( ) const inline

◆ getMaxNumWorkGroups()

◆ getMaxNumWorkGroupsX()

unsigned llvm::SIMachineFunctionInfo::getMaxNumWorkGroupsX ( ) const inline

◆ getMaxNumWorkGroupsY()

unsigned llvm::SIMachineFunctionInfo::getMaxNumWorkGroupsY ( ) const inline

◆ getMaxNumWorkGroupsZ()

unsigned llvm::SIMachineFunctionInfo::getMaxNumWorkGroupsZ ( ) const inline

◆ getMaxWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMaxWavesPerEU ( ) const inline

◆ getMinAllowedOccupancy()

unsigned llvm::SIMachineFunctionInfo::getMinAllowedOccupancy ( ) const inline

◆ getMinFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMinFlatWorkGroupSize ( ) const inline

◆ getMinNumAGPRs()

unsigned llvm::SIMachineFunctionInfo::getMinNumAGPRs ( ) const inline

◆ getMinWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMinWavesPerEU ( ) const inline

◆ getMode()

◆ getNonWWMRegMask()

BitVector llvm::SIMachineFunctionInfo::getNonWWMRegMask ( ) const inline

◆ getNumKernargPreloadedSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumKernargPreloadedSGPRs ( ) const inline

◆ getNumPreloadedSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumPreloadedSGPRs ( ) const inline

◆ getNumSpilledSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledSGPRs ( ) const inline

◆ getNumSpilledVGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledVGPRs ( ) const inline

◆ getNumUserSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumUserSGPRs ( ) const inline

◆ getNumWaveDispatchSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumWaveDispatchSGPRs ( ) const inline

◆ getNumWaveDispatchVGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumWaveDispatchVGPRs ( ) const inline

◆ getOccupancy()

unsigned llvm::SIMachineFunctionInfo::getOccupancy ( ) const inline

◆ getOptionalScavengeFI()

std::optional< int > llvm::SIMachineFunctionInfo::getOptionalScavengeFI ( ) const inline

◆ getPreloadedReg()

◆ getPreloadedValue()

◆ getPrivateSegmentWaveByteOffsetSystemSGPR()

Register llvm::SIMachineFunctionInfo::getPrivateSegmentWaveByteOffsetSystemSGPR ( ) const inline

◆ getPrologEpilogSGPRSaveRestoreInfo()

◆ getPrologEpilogSGPRSpills()

ArrayRef< PrologEpilogSGPRSpill > llvm::SIMachineFunctionInfo::getPrologEpilogSGPRSpills ( ) const inline

◆ getPSInputAddr()

unsigned llvm::SIMachineFunctionInfo::getPSInputAddr ( ) const inline

◆ getPSInputEnable()

unsigned llvm::SIMachineFunctionInfo::getPSInputEnable ( ) const inline

◆ getQueuePtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getQueuePtrUserSGPR ( ) const inline

◆ getScavengeFI()

◆ getScratchReservedForDynamicVGPRs()

unsigned llvm::SIMachineFunctionInfo::getScratchReservedForDynamicVGPRs ( ) const inline

◆ getScratchRSrcReg()

Register llvm::SIMachineFunctionInfo::getScratchRSrcReg ( ) const inline

◆ getScratchSGPRCopyDstReg()

Register llvm::SIMachineFunctionInfo::getScratchSGPRCopyDstReg ( Register Reg) const inline

◆ getSGPRForEXECCopy()

Register llvm::SIMachineFunctionInfo::getSGPRForEXECCopy ( ) const inline

◆ getSGPRSpillPhysVGPRs()

ArrayRef< Register > llvm::SIMachineFunctionInfo::getSGPRSpillPhysVGPRs ( ) const inline

◆ getSGPRSpillToPhysicalVGPRLanes()

◆ getSGPRSpillToVirtualVGPRLanes()

◆ getSGPRSpillVGPRs()

ArrayRef< Register > llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs ( ) const inline

◆ getStackPtrOffsetReg()

Register llvm::SIMachineFunctionInfo::getStackPtrOffsetReg ( ) const inline

Definition at line 1058 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::eliminateCallFramePseudoInstr(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getFrameRegister(), llvm::SIRegisterInfo::getReservedRegs(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIFrameLowering::restoreCalleeSavedRegisters(), llvm::SIFrameLowering::spillCalleeSavedRegisters(), llvm::SIRegisterInfo::spillSGPR(), and llvm::SIInstrInfo::storeRegToStackSlot().

◆ getUserSGPRInfo() [1/2]

◆ getUserSGPRInfo() [2/2]

◆ getVGPRForAGPRCopy()

Register llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy ( ) const inline

◆ getVGPRSpillAGPRs()

ArrayRef< MCPhysReg > llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs ( ) const inline

◆ getVGPRToAGPRSpill()

MCPhysReg llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill ( int FrameIndex, unsigned Lane ) const inline

◆ getWavesPerEU()

std::pair< unsigned, unsigned > llvm::SIMachineFunctionInfo::getWavesPerEU ( ) const inline

◆ getWWMReservedRegs()

◆ getWWMSpills()

◆ hasImplicitArgPtr()

bool llvm::SIMachineFunctionInfo::hasImplicitArgPtr ( ) const inline

◆ hasLDSKernelId()

bool llvm::SIMachineFunctionInfo::hasLDSKernelId ( ) const inline

◆ hasMaskForVGPRBlockOps()

bool llvm::SIMachineFunctionInfo::hasMaskForVGPRBlockOps ( Register RegisterBlock) const inline

◆ hasNonSpillStackObjects()

bool llvm::SIMachineFunctionInfo::hasNonSpillStackObjects ( ) const inline

◆ hasPrivateSegmentWaveByteOffset()

bool llvm::SIMachineFunctionInfo::hasPrivateSegmentWaveByteOffset ( ) const inline

◆ hasPrologEpilogSGPRSpillEntry()

bool llvm::SIMachineFunctionInfo::hasPrologEpilogSGPRSpillEntry ( Register Reg) const inline

◆ hasSpilledSGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledSGPRs ( ) const inline

◆ hasSpilledVGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledVGPRs ( ) const inline

◆ hasVRegFlags()

bool llvm::SIMachineFunctionInfo::hasVRegFlags ( ) inline

◆ hasWorkGroupIDX()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDX ( ) const inline

◆ hasWorkGroupIDY()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDY ( ) const inline

◆ hasWorkGroupIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDZ ( ) const inline

◆ hasWorkGroupInfo()

bool llvm::SIMachineFunctionInfo::hasWorkGroupInfo ( ) const inline

◆ hasWorkItemIDX()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDX ( ) const inline

◆ hasWorkItemIDY()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDY ( ) const inline

◆ hasWorkItemIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDZ ( ) const inline

◆ increaseOccupancy()

◆ initializeBaseYamlFields()

Definition at line 792 of file SIMachineFunctionInfo.cpp.

References llvm::yaml::SIMachineFunctionInfo::BytesInStackArgArea, llvm::SourceMgr::DK_Error, llvm::AMDGPUMachineFunction::DynLDSAlign, llvm::yaml::SIMachineFunctionInfo::DynLDSAlign, llvm::AMDGPUMachineFunction::ExplicitKernArgSize, llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize, llvm::AMDGPUMachineFunction::GDSSize, llvm::yaml::SIMachineFunctionInfo::GDSSize, llvm::MemoryBuffer::getBufferIdentifier(), llvm::MachineFunction::getFrameInfo(), llvm::SourceMgr::getMainFileID(), llvm::SourceMgr::getMemoryBuffer(), llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs, llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs, llvm::yaml::SIMachineFunctionInfo::HighBitsOf32BitAddress, llvm::AMDGPUMachineFunction::IsEntryFunction, llvm::yaml::SIMachineFunctionInfo::IsEntryFunction, llvm::yaml::SIMachineFunctionInfo::IsWholeWaveFunction, llvm::AMDGPUMachineFunction::LDSSize, llvm::yaml::SIMachineFunctionInfo::LDSSize, llvm::AMDGPUMachineFunction::MaxKernArgAlign, llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign, llvm::yaml::SIMachineFunctionInfo::MaxMemoryClusterDWords, llvm::AMDGPUMachineFunction::MemoryBound, llvm::yaml::SIMachineFunctionInfo::MemoryBound, llvm::AMDGPUMachineFunction::NoSignedZerosFPMath, llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath, llvm::yaml::SIMachineFunctionInfo::NumKernargPreloadSGPRs, llvm::yaml::SIMachineFunctionInfo::NumWaveDispatchSGPRs, llvm::yaml::SIMachineFunctionInfo::NumWaveDispatchVGPRs, llvm::yaml::SIMachineFunctionInfo::Occupancy, llvm::yaml::SIMachineFunctionInfo::PSInputAddr, llvm::yaml::SIMachineFunctionInfo::PSInputEnable, llvm::yaml::SIMachineFunctionInfo::ReturnsVoid, llvm::yaml::SIMachineFunctionInfo::ScavengeFI, llvm::PerFunctionMIParsingState::SM, llvm::toString(), llvm::AMDGPUMachineFunction::WaveLimiter, and llvm::yaml::SIMachineFunctionInfo::WaveLimiter.

Referenced by llvm::GCNTargetMachine::parseMachineFunctionInfo().

◆ isCalleeSavedReg()

◆ isDynamicVGPREnabled()

bool llvm::SIMachineFunctionInfo::isDynamicVGPREnabled ( ) const inline

◆ isPSInputAllocated()

bool llvm::SIMachineFunctionInfo::isPSInputAllocated ( unsigned Index) const inline

◆ isStackRealigned()

bool llvm::SIMachineFunctionInfo::isStackRealigned ( ) const inline

◆ isWholeWaveFunction()

bool llvm::SIMachineFunctionInfo::isWholeWaveFunction ( ) const inline

◆ isWWMReg()

bool llvm::SIMachineFunctionInfo::isWWMReg ( Register Reg) const inline

◆ isWWMReservedRegister()

bool llvm::SIMachineFunctionInfo::isWWMReservedRegister ( Register Reg) const inline

◆ limitOccupancy() [1/2]

◆ limitOccupancy() [2/2]

void llvm::SIMachineFunctionInfo::limitOccupancy ( unsigned Limit) inline

◆ markPSInputAllocated()

void llvm::SIMachineFunctionInfo::markPSInputAllocated ( unsigned Index) inline

◆ markPSInputEnabled()

void llvm::SIMachineFunctionInfo::markPSInputEnabled ( unsigned Index) inline

◆ mayUseAGPRs()

◆ removeDeadFrameIndices()

If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.

Definition at line 568 of file SIMachineFunctionInfo.cpp.

References checkIndexInPrologEpilogSGPRSpills(), llvm::TargetStackID::Default, llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectIndexEnd(), llvm::MachineFrameInfo::getStackID(), I, llvm::make_early_inc_range(), llvm::MachineFrameInfo::RemoveStackObject(), llvm::MachineFrameInfo::setStackID(), and llvm::TargetStackID::SGPRSpill.

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ reserveWWMRegister()

void llvm::SIMachineFunctionInfo::reserveWWMRegister ( Register Reg) inline

◆ returnsVoid()

bool llvm::SIMachineFunctionInfo::returnsVoid ( ) const inline

◆ selectAGPRFormMFMA()

bool llvm::SIMachineFunctionInfo::selectAGPRFormMFMA ( unsigned NumRegs) const inline

◆ setBytesInStackArgArea()

void llvm::SIMachineFunctionInfo::setBytesInStackArgArea ( unsigned Bytes) inline

◆ setFlag()

◆ setFrameOffsetReg()

void llvm::SIMachineFunctionInfo::setFrameOffsetReg ( Register Reg) inline

◆ setHasNonSpillStackObjects()

void llvm::SIMachineFunctionInfo::setHasNonSpillStackObjects ( bool StackObject = true) inline

◆ setHasSpilledSGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledSGPRs ( bool Spill = true) inline

◆ setHasSpilledVGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledVGPRs ( bool Spill = true) inline

◆ setIfReturnsVoid()

void llvm::SIMachineFunctionInfo::setIfReturnsVoid ( bool Value) inline

◆ setIsStackRealigned()

void llvm::SIMachineFunctionInfo::setIsStackRealigned ( bool Realigned = true) inline

◆ setLongBranchReservedReg()

void llvm::SIMachineFunctionInfo::setLongBranchReservedReg ( Register Reg) inline

◆ setMaskForVGPRBlockOps()

void llvm::SIMachineFunctionInfo::setMaskForVGPRBlockOps ( Register RegisterBlock, uint32_t Mask ) inline

◆ setNumWaveDispatchSGPRs()

void llvm::SIMachineFunctionInfo::setNumWaveDispatchSGPRs ( unsigned Count) inline

◆ setNumWaveDispatchVGPRs()

void llvm::SIMachineFunctionInfo::setNumWaveDispatchVGPRs ( unsigned Count) inline

◆ setPrivateSegmentWaveByteOffset()

void llvm::SIMachineFunctionInfo::setPrivateSegmentWaveByteOffset ( Register Reg) inline

◆ setScratchReservedForDynamicVGPRs()

void llvm::SIMachineFunctionInfo::setScratchReservedForDynamicVGPRs ( unsigned SizeInBytes) inline

◆ setScratchRSrcReg()

void llvm::SIMachineFunctionInfo::setScratchRSrcReg ( Register Reg) inline

◆ setSGPRForEXECCopy()

void llvm::SIMachineFunctionInfo::setSGPRForEXECCopy ( Register Reg) inline

◆ setStackPtrOffsetReg()

void llvm::SIMachineFunctionInfo::setStackPtrOffsetReg ( Register Reg) inline

◆ setVGPRForAGPRCopy()

void llvm::SIMachineFunctionInfo::setVGPRForAGPRCopy ( Register NewVGPRForAGPRCopy) inline

◆ setVGPRToAGPRSpillDead()

void llvm::SIMachineFunctionInfo::setVGPRToAGPRSpillDead ( int FrameIndex) inline

◆ setWorkItemIDX()

void llvm::SIMachineFunctionInfo::setWorkItemIDX ( ArgDescriptor Arg) inline

◆ setWorkItemIDY()

void llvm::SIMachineFunctionInfo::setWorkItemIDY ( ArgDescriptor Arg) inline

◆ setWorkItemIDZ()

void llvm::SIMachineFunctionInfo::setWorkItemIDZ ( ArgDescriptor Arg) inline

◆ shiftWwmVGPRsToLowestRange()

◆ splitWWMSpillRegisters()

◆ updateNonWWMRegMask()

void llvm::SIMachineFunctionInfo::updateNonWWMRegMask ( BitVector & RegMask) inline

◆ GCNTargetMachine

◆ MFMAVGPRForm

bool SIMachineFunctionInfo::MFMAVGPRForm = false static

The documentation for this class was generated from the following files: