LLVM: llvm::SGPRSpillBuilder Struct Reference (original) (raw)

Public Member Functions
SGPRSpillBuilder (const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, int Index, RegScavenger *RS)
SGPRSpillBuilder (const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, Register Reg, bool IsKill, int Index, RegScavenger *RS)
PerVGPRData getPerVGPRData ()
void prepare ()
void restore ()
void readWriteTmpVGPR (unsigned Offset, bool IsLoad)
void setMI (MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI)
Public Attributes
Register SuperReg
MachineBasicBlock::iterator MI
ArrayRef< int16_t > SplitParts
unsigned NumSubRegs
bool IsKill
const DebugLoc & DL
Register TmpVGPR = AMDGPU::NoRegister
int TmpVGPRIndex = 0
bool TmpVGPRLive = false
Register SavedExecReg = AMDGPU::NoRegister
int Index
unsigned EltSize = 4
RegScavenger * RS
MachineBasicBlock * MBB
MachineFunction & MF
SIMachineFunctionInfo & MFI
const SIInstrInfo & TII
const SIRegisterInfo & TRI
bool IsWave32
Register ExecReg
unsigned MovOpc
unsigned NotOpc

Definition at line 78 of file SIRegisterInfo.cpp.

◆ SGPRSpillBuilder() [2/2]

Definition at line 124 of file SIRegisterInfo.cpp.

References assert(), DL, EltSize, ExecReg, getDebugLoc(), getParent(), if(), Index, IsKill, IsWave32, MBB, MF, MFI, MI, MovOpc, NotOpc, NumSubRegs, RS, SplitParts, SuperReg, TII, and TRI.

◆ getPerVGPRData()

PerVGPRData llvm::SGPRSpillBuilder::getPerVGPRData ( ) inline

◆ prepare()

void llvm::SGPRSpillBuilder::prepare ( ) inline

Definition at line 171 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, emitUnsupportedError(), ExecReg, getPerVGPRData(), I, llvm::RegState::ImplicitDefine, IsWave32, MBB, MF, MFI, MI, MovOpc, NotOpc, RS, SavedExecReg, SuperReg, TII, TmpVGPR, TmpVGPRIndex, TmpVGPRLive, TRI, and llvm::SGPRSpillBuilder::PerVGPRData::VGPRLanes.

Referenced by llvm::SIRegisterInfo::restoreSGPR(), llvm::SIRegisterInfo::spillEmergencySGPR(), and llvm::SIRegisterInfo::spillSGPR().

◆ readWriteTmpVGPR()

void llvm::SGPRSpillBuilder::readWriteTmpVGPR ( unsigned Offset, bool IsLoad ) inline

Definition at line 295 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, emitUnsupportedError(), ExecReg, llvm::MachineInstr::getOperand(), Index, MBB, MF, MI, NotOpc, llvm::Offset, RS, SavedExecReg, llvm::MachineOperand::setIsDead(), TII, and TRI.

Referenced by llvm::SIRegisterInfo::restoreSGPR(), and llvm::SIRegisterInfo::spillSGPR().

◆ restore()

void llvm::SGPRSpillBuilder::restore ( ) inline

Definition at line 254 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, ExecReg, I, llvm::RegState::ImplicitKill, llvm::RegState::Kill, MBB, MI, MovOpc, NotOpc, RS, SavedExecReg, TII, TmpVGPR, TmpVGPRIndex, TmpVGPRLive, and TRI.

Referenced by llvm::SIRegisterInfo::restoreSGPR(), llvm::SIRegisterInfo::spillEmergencySGPR(), and llvm::SIRegisterInfo::spillSGPR().

◆ setMI()

◆ DL

◆ EltSize

unsigned llvm::SGPRSpillBuilder::EltSize = 4

◆ ExecReg

Register llvm::SGPRSpillBuilder::ExecReg

◆ Index

int llvm::SGPRSpillBuilder::Index

◆ IsKill

bool llvm::SGPRSpillBuilder::IsKill

◆ IsWave32

bool llvm::SGPRSpillBuilder::IsWave32

◆ MBB

◆ MF

◆ MFI

◆ MI

◆ MovOpc

◆ NotOpc

◆ NumSubRegs

unsigned llvm::SGPRSpillBuilder::NumSubRegs

◆ RS

◆ SavedExecReg

Register llvm::SGPRSpillBuilder::SavedExecReg = AMDGPU::NoRegister

◆ SplitParts

ArrayRef<int16_t> llvm::SGPRSpillBuilder::SplitParts

◆ SuperReg

Register llvm::SGPRSpillBuilder::SuperReg

◆ TII

◆ TmpVGPR

Register llvm::SGPRSpillBuilder::TmpVGPR = AMDGPU::NoRegister

◆ TmpVGPRIndex

int llvm::SGPRSpillBuilder::TmpVGPRIndex = 0

◆ TmpVGPRLive

bool llvm::SGPRSpillBuilder::TmpVGPRLive = false

◆ TRI

The documentation for this struct was generated from the following file: