Future Generation Ultra Supercomputing 256 × 256 Bits Multiplier for Signed-Unsigned Number (original) (raw)
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Annals of Emerging Technologies in Computing (AETiC), 2019
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International Journal of Electronics Signals and Systems, 2012
Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed mu...
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