A Effect of Oxide Charge and Interface Traps on Drain Current Degradation of Vertical Silicon Tunneling Field Effect Transistors (original) (raw)

Effects of Source Doping Profile on Device Characteristics of Lateral and Vertical Tunnel Field-Effect Transistors

Chien Nguyen Dang

Journal of Science and Technology, 2015

View PDFchevron_right

Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors

Gerhard Klimeck

2010

View PDFchevron_right

Improved drain current characteristics of tunnel field effect transistor with heterodielectric stacked structure

Vimala Palanichamy

international journal of nano dimension, 2019

View PDFchevron_right

Vertical Tunnel Field-Effect Transistor

Jörg Schulze

IEEE Transactions on Electron Devices, 2004

View PDFchevron_right

Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance

Girish Wadhwa

Transactions on Electrical and Electronic Materials, 2019

View PDFchevron_right

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Ravinder Singh Sawhney

2021

View PDFchevron_right

Comparative Study of Silicon and Germanium Doping-less Tunnel Field Effect Transistors

IJSTE - International Journal of Science Technology and Engineering

View PDFchevron_right

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Andriy Hikavyy

Solid-State Electronics, 2013

View PDFchevron_right

Vertical Tunneling Based Tunnel Field Effect Transistor with Workfunction Engineered Hetero-Gate to Enhance DC Characteristics

Neha Paras

Journal of Nanoelectronics and Optoelectronics, 2019

View PDFchevron_right

Source engineered tunnel FET for enhanced device electrostatics with trap charges reliability

Sukeshni Tirkey

Microelectronic Engineering, 2018

View PDFchevron_right

Design and Analysis of Tunnel FET for Low Power High Performance Applications

Manisha Pattanaik

International Journal of Modern Education and Computer Science, 2018

View PDFchevron_right

Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

Dr. Shiromani B A L M U K U N D Rahi

View PDFchevron_right

Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Jawar Singh

2009 IEEE International Electron Devices Meeting (IEDM), 2009

View PDFchevron_right

Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)

Ranjan Mishra

International Journal of Innovative Technology and Exploring Engineering, 2019

View PDFchevron_right

A Perspective Review of Tunnel Field Effect Transistor with Steeper Switching Behavior and Low off Current (I OFF ) for Ultra Low Power Applications

Maria Jossy

2014

View PDFchevron_right

An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor

Girish Wadhwa

International Journal of Recent Technology and Engineering (IJRTE), 2019

View PDFchevron_right

Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

Taehyung Park

Japanese Journal of Applied Physics, 2016

View PDFchevron_right

A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET

Jörg Schulze

IEEE Transactions on Electron Devices, 2005

View PDFchevron_right

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

Guido Groeseneken

Journal of Applied Physics, 2010

View PDFchevron_right

Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel

Daryoosh Dideban, Journal of Electrical and Computer Engineering Innovations

2019

View PDFchevron_right

New Challenges on Leakage Current Improvement In Tunnel FET by Using Low-K Oxide

Benyamin Davaji

Quality Electronic Design, …, 2009

View PDFchevron_right

Analysis of Kink Reduction and reliability issues in Low-voltage Dual Tunnel Diode based SOI TFET

Brinda Bhowmick

Micro & Nano Letters

View PDFchevron_right

Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor

dheeraj SHARMA

Superlattices and Microstructures, 2016

View PDFchevron_right

Design of Si 0.5 Ge 0.5 based tunnel field effect transistor and its performance evaluation

Sunny Anand, Intekhab Amin

View PDFchevron_right

A Novel High Performance Nanoscaled Dual Oxide Doping Less Tunnel Field Effect Transistor

Faisal Bashir

View PDFchevron_right

ON current improvement techniques for double gate-tunnel field effect transistor

Satyam Kumar

2017

View PDFchevron_right

The Tunnel Field-Effect Transistor

Anne Verhulst

Wiley Encyclopedia of Electrical and Electronics Engineering

View PDFchevron_right

Source-All-Around Tunnel Field-Effect Transistor (SAA-TFET): Proposal and Design

Ahmed Maged

2019

View PDFchevron_right

Investigation of Electrical Characteristics of Vertical Junction Si n-Type Tunnel FET

Puja Ghosh

IEEE Transactions on Electron Devices

View PDFchevron_right

Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

Dawit Abdi

IEEE Access, 2021

View PDFchevron_right