Hardware Verification Research Papers - Academia.edu (original) (raw)

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- Distributed Computing, Computer Software, Hardware Design, Specification
- by Thomas Kropf
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- Model Checking, Theorem Proving, Hardware Verification

The main objectives of this work are to describe the online bus pass generation and ticket booking using QR code. Online bus pass generation is helpful to people who are suffering issues with the present technique for the generation of bus pass and renewal. This project consists of two login pages, one for user registration and the other one for admin. Users need to register by submitting their details through online. Once the registration process is done then a security code called One Time Password (OTP) code will be sent to the user's registered mail. This system is used for ticket generation, bus pass formation and renewing of the bus pass of the users. The user can login with Idno and password to perform the pass booking and renewal. Bus Ticket Checker can scan the users QR code to check the validity of bus pass.

This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented.

- by Andrew Kornecki
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- FPGA, Literature Review, Hardware Design, Real Time Systems
- by Nevin Darwish
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- Engineering, Mathematical Sciences, Hardware Verification, Hybrid Approach

This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool "Tetramax" from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulated data output. Its diagnostic capabilities have been verified by hardware-based emulating stuck-at faults at various test points in a demonstrator chip and we subsequently traced back the introduced fault successfully. The used flow simplifies the generation of test vectors and subsequent debugging, especially for large digital integrated circuits.

- by Hans Kerkhoff
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- Hardware Verification
- by Roland Backhouse
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- Hardware Verification, MPC, Round Robin

This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.

- by Gaurav Sengar
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- Computer Hardware, Hardware Verification, Formal Verification, Galois Fields

Recent developments in the field of digital design and hardware verification have found great use for restricted forms of branching programs. In particular, oblivious read-once branching programs (also called "OBDD's") are central to a very common technique for verifying circuits. These programs are useful because they are easily manipulated and compared for equivalence. However, their utility is limited because they cannot compute in polynomial size several simple functions--most notably, integer multiplication. This limitation has prompted the consideration of alternative models, usually restricted classes of branching programs, in the hope of finding one with greater computational power but also easily manipulated and tested for equivalence. Read-once (non-oblivious) branching programs can to some degree be manipulated and tested for equivalence, but it has been an open question whether they can compute integer multiplication in polynomial size. The main result of t...

- by Stephen Ponzio
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- Mathematics, Computer Science, Digital design, Hardware Verification
- by Hans Öhman
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- Hardware Verification, Low Latency, Broadband Communication
- by Natarajan Shankar
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- Formal method, Hardware Verification, Specification Language
- by Romulo Calado
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- Hardware Verification, Testbench
- by Thomas Kropf
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- Digital Circuits, Hardware Description Languages, Vhdl, Safety
- by Shmuel Ur
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- Software Testing, Software Development, Hardware Design, Hardware Verification
- by Yehuda Naveh and +2
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- Hardware Verification

Faulty device drivers are a major source of operating system failures. We argue that the underlying cause of many driver faults is the separation of two highly-related tasks: device verification and driver development. These two tasks have a lot in common, and result in software that is conceptually and functionally similar, yet kept totally separate. The result is a particularly

- by Gernot Heiser
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- OPERATING SYSTEM, Hardware Verification, Automated Testing, Test Coverage

This is a proposal for a bit-precise word-level format, called BTOR. It is easy to parse and has precise semantics. In its basic form it allows to model SMT problems over the quanti er-free theory of bit-vectors in combination with onedimensional arrays. Our main contribution is a sequential extension that can be used to capture model checking problems on the word-level. We present two case studies where BTOR is used as sequential format. Finally, we report on experimental results for the model checking extension of our SMT solver Boolector.

- by Andrew Kornecki
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- FPGA, Literature Review, Hardware Design, Real Time Systems

The underlying model of computation for PROMELA is based on interacting processes with asynchronous communication, and hence SPIN has been mainly used as a verification engine for concurrent software systems. On the other hand, hardware verification has mostly focused on clock synchronous register-transfer level (RTL) models. As a result, verification tools such as SMV which are based on synchronous state machine models have been used more frequently for hardware verification. However, as levels of abstractions are being ...

- by Don Syme
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- Model Checking, Computer Aided Design, Computer Hardware, Theorem Proving
- by Peter Marwedel
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- Distributed Computing, Hardware, Code Generation, Hardware Verification
- by Yehuda Naveh
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- Hardware Verification
- by Thomas Kropf
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- Hardware Verification
- by Somesh Jha
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- Cognitive Science, Distributed Computing, Model Checking, Markov Decision Process
- by Eli Singerman
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- Embedded Software, Formal method, Symbolic Execution, Software Requirements
- by Skander Kort
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- Computer Software, Hardware Verification, Formal Verification, Chip
- by Shamsuzzoha Md
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- Information Systems, Computer Architecture, Formal methods, Theorem Proving
- by Ramesh Bharadwaj
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- Cognitive Science, Model Checking, Computer Software, Hardware Design

The attractiveness of using theorem provers for system design verification lies in their generality. The major practical challenge confronting theorem proving technology is in combining this generality with an acceptable degree of automation. We describe an approach for enhancing the effectiveness of theorem provers for hardware verification through the use of efficient automatic procedures for rewriting, arithmetic and equality reasoning, and an off-the-shelf BDD-based propo-sitional simplifier. These automatic procedures can be combined into general-purpose proof strategies that can efficiently automate a number of proofs including those of hardware correctness. The inference procedures and proof strategies have been implemented in the PVS verification system. They are applied to several examples including an N-bit adder, the Saxe pipelined processor, and the benchmark Tamarack microprocessor design. These examples illustrate the basic design philosophy underlying PVS where powerful and efficient low-level inferences are employed within high-level user-defined proof strategies. This approach is contrasted with approaches based on tactics or batch-oriented theorem proving.

- by Natarajan Shankar
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- Theorem Proving, Hardware Verification

PVS stands for “Prototype Verification System.” It consists of a specification language integrated with support tools and a theorem prover. PVS tries to provide the mechanization needed to apply formal methods both rigorously and productively. This tutorial serves to introduce PVS and its use in the context of hardware verification. In the first section, we briefly sketch the purposes for which PVS is intended and the rationale behind its design, mention some of the uses that we and others are making of it. We give an overview of the PVS specification language and proof checker. The PVS language, system, and theorem prover each have their own reference manuals, which you will need to study in order to make productive use of the system. A pocket reference card, summarizing all the features of the PVS language, system, and prover is also available. The purpose of this tutorial is not to describe in detail the features of PVS and how to use the system. Rather, its purpose is to introduce some of the more unique and powerful capabilities that are provided by PVS and demonstrate how these features can be used in the context of hardware verification. We present completely worked out proofs of two hardware examples. One of the examples is a pipelined microprocessor that has been used as benchmark for model checkers and the other is a parameterized implementation of an N-bit ripple-carry adder.

- by Natarajan Shankar
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- Formal method, Hardware Verification, Specification Language
- by Vladimir Levin
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- Distributed Computing, Design practice, Model Checking, Formal methods

The quantifier-free extensional theory of arrays T_A plays an important role in hardware and software verification. In this article we present a novel decision procedure that refines formula abstractions with lemmas on demand. We consider the case where T_A is combined with a decidable quantifier-free first-order theory T_B. Unlike traditional lazy SMT approaches, where lemmas are added on the boolean abstraction layer, our decision procedure adds lemmas in T_B. We discuss our decision procedure in detail. In particular, we prove soundness and completeness, and discuss complexity. We present our decision procedure in a generic context and provide implementation details and optimizations, in particular for bit-vectors. Finally, we report on experiments and discuss related work.

Deciding satis ability in the theory of arrays, particularly in combination with bit-vectors, is essential for software and hardware veri cation. We precisely describe how the lemmas on demand approach can be applied to this decision problem. In particular, we show how our new propagation based algorithm can be generalized to the extensional theory of arrays. Our implementation achieves competitive performance.

- by Harald Ruess
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- Distributed Computing, Computer Arithmetic, Computer Software, Hardware Design
- by Fred Harris
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- Computer Science, Linear Algebra, Architectural Design, FPGA implementation

- by Janusz Zalewski
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- FPGA, Literature Review, Hardware Design, Real Time Systems

- by J. Zalewski
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- FPGA, Literature Review, Hardware Design, Real Time Systems
- by Eli Singerman
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- Embedded Software, Hardware, Formal method, Symbolic Execution
- by John O'Leary
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- Functional Programming, Model Checking, Formal methods, Theorem Proving