Residue Number System Research Papers (original) (raw)

We consider software-hardware implementation of a digital filter (FIR-filter) using the residue number system and scaling of output samples of each filter channel. It is shown that scaling leads to a significant reduction in instrumental... more

- by and +2
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- Digital Signal Processing, Digital FPGA implementation, Residue Number System, Filter Design
- by Keivan Navi
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- Engineering, Education, Computer Science Education, Engineering Education
- by Ahmad Hiasat and +1
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- Residue Number System, Hardware, Decoding, Hardware Implementation of Algorithms
- by Sorin Cotofana
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- Parallel Algorithms, Digital Signal Processing, Residue Number System, Arithmetic
- by Gian Cardarilli
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- Residue Number System, Power Consumption, Design Methodology, Filter Banks
- by Omid Kavehei
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- Computer Arithmetic, Multidisciplinary, Residue Number System, Low Power

The paper discusses an algorithm for correcting code errors of the residue number system using a positional characteristic. Application of parallel-pipeline computations of this positional characteristic allows us to reduce hardware costs by 7.2% for processing 2-byte data represented in a residue number system code. The main properties of codes allow us to provide the required fault-tolerance for multi-rate DSP devices. The results provided in the paper can be applied to hydroacoustic monitoring tasks.

- by Leonel Sousa
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- Parallel Algorithms, Art, Parallel Processing, Residue Number System
- by Gian Cardarilli
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- Residue Number System, Power Consumption, Design Methodology, Filter Banks
- by sudeep hegde
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- Computer Science, Image Processing, Residue Number System, Sharing
- by Ahmad Hiasat
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- Residue Number System, Computer Software, Systems Architecture, Dynamic Range

Residue Number System (RNS) is a non-weighted system of which arithmetic operation speed-up is the main advantage, but comparison in RNS is not as simple as conventional numeric systems such as binary. Therefore to compare two numbers, converting them from residue representation to weighted systems and then comparing has been proposed. However, reverse conversion is a complex step that burdens high complexity to system, in this paper a modified version of RNS named two-part RNS is used for moduli set {2 1, 2 1, 2 } n n n  and an efficient comparator based on Mixed Radix Conversion (MRC) is presented. By using two-part RNS, the number of moduli in each part decreases, thus the reverse converter can be implemented effectively. Low complexity of reverse converter leads to an increase in the efficiency of proposed comparator. The novel comparator is compared with recently presented methods, as the results of implementation on FPGA illustrate the proposed comparator implies high speed low complexity in large word-widths. Keywords—Computer Arithmetic, Residue Number System (RNS), Parallel Processing, VLSI.

- by Said Boussakta
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- Vlsi Design, Distributed Computing, Computer Arithmetic, Computer Hardware
- by P. Kornerup
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- Cryptography, Residue Number System, Protocols, Arithmetic
- by P. Kornerup
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- Algorithms, Distributed Computing, Computer Arithmetic, Computer Hardware
- by Alberto Nannarelli and +1
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- Residue Number System, FIR filter, Digital Filter Design, Power Dissipation

Implementation of RNS addition and RNS multiplication into FPGAs (Extended Abstract) Luiz Maltar CB, Felipe MG França, Vladmir C. Alves and Cláudio L. Amorim COPPE - Universidade Federal do Rio de Janeiro Caixa Postal 68511, Postal Code... more

- by Alberto Nannarelli and +2
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- Residue Number System, Circuit Complexity, High performance, Digital Filter Design
- by Pallab Maji
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- Electrical Engineering, Residue Number System, Fuzzy Logic Controller
- by Roy Wilmhoff
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- Architecture, Stability, Algorithm, Reflection

Arithmetic operations like addition and multiplication are the most important part for the computation in signal processing applications. Mathematical operations can be computed with increased speed in Residue Number System (RNS) than the conventional binary number systems because all the operations are done carry free and in parallel in RNS system. These carry free and parallel operations speed up in the RNS based computation. Selection of proper moduli set and their values offer maximum speed and minimum hardware for designing a signal processing system. In Residue Number System many intermediate results are constant and processing time can also be reduced using look-up table. Though there are many limitations in the RNS system, still RNS system can be used to speed up the total execution time of a system in comparison with conventional binary system.

- by IAEME Publication
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- Signal Processing, Residue Number System, Dynamic Range, Moduli Set
- by Leonel Sousa
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- Signal Processing, Residue Number System

Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set. This paper suggests a new non-coprime moduli set and investigates its performance. The suggested new moduli set has the general representation as {2 n –2, 2 n , 2 n +2}, where n ∈ {2,3,…..,∞}. The calculations among the moduli are done with this n value. These moduli are 2 spaces apart on the numbers line from each other. This range helps in the algorithm's calculations as to be shown. The proposed non-coprime moduli set is investigated. Conversion algorithm from Binary to Residue is developed. Correctness of the algorithm was obtained through simulation program. Conversion algorithm is implemented.

- by Arnaud Tisserand
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- Cryptography, Residue Number System, Memory, Elliptic Curve Cryptography
- by Keivan Navi
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- Computer Arithmetic, Residue Number System, Computer Software, Systems
- by Keivan Navi
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- Information Systems, Law, Algorithm, Residue Number System
- by Leonel Sousa
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- Residue Number System, Chinese Remainder Theorem, Dynamic Range
- by Sorin Cotofana
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- Residue Number System, Chinese Remainder Theorem, Dynamic Range

As one of the processor's ALU performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. This work aims to build an Efficient Hardware Design for an Adder based on Residual Numbering System (RNS), with a pre-specified special set of moduli to simplify the implementation for proving the feasibility of its usage. Our design can be divided into three basic components: two conversion modules, and an addition module. The conversion modules here are based on a special set of moduli numbers to simplify the hardware implementation. In this work, we focus on forward conversion (conventional to RNS) leaving reverse converter {RNS to conventional} for future works. Depending on this notion, we implemented each component individually in VHDL and then to assemble these components with each other to build a whole RNS-Adder. Simulation results are very attractive in terms of critical path delay.

- by Qasem Abu Al-Haija
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- Residue Number System, Moduli Spaces
- by Michael Soderstrand
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- Logic, VLSI, Residue Number System, Multiple Valued Logic

Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set. This paper suggests a new non-coprime moduli set and investigates its performance. The suggested new moduli set has the general representation as {2 n-2, 2 n , 2 n +2}, where n ∈ {2,3,…..,∞}. The calculations among the moduli are done with this n value. These moduli are 2 spaces apart on the numbers line from each other. This range helps in the algorithm's calculations as to be shown. The proposed non-coprime moduli set is investigated. Conversion algorithm from Binary to Residue is developed. Correctness of the algorithm was obtained through simulation program. Conversion algorithm is implemented.

VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-linear Residue Number System (RNS) based counters. Four VEST cipher family trees are introduced: 80-bit secure VEST-4, 128-bit secure VEST-8, 160-bit secure VEST-16 and 256-bit secure VEST-32. VEST ciphers return 4 to 32 bits of output per clock cycle while occupying ~5K to ~22K ASIC gates including

- by Howard Landman
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- Residue Number System, Performance Improvement, High Speed, Low Latency

- by Pierre-yvan Liardet and +1
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- Residue Number System, Side Channel attacks
- by Sebastiano Impedovo and +1
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- Residue Number System, Chinese Remainder Theorem, Electrical And Electronic Engineering

In this paper, the design of modulo multipliers for the moduli (2^4k + 2^(2k+1) - 2^(3k+1) - 2^k + 1) and (2^4k - 2^(3k+1) + 2^k - 1)is investigated. These moduli are useful for constructing three and four moduli sets with interesting properties resulting in simpler RNS to binary conversion architectures. The derived architectures of the multipliers can facilitate binary to RNS conversion as well. Hardware requirements and multiplication time are derived using unit gate model and ASIC implementation results are presented.

- by Dr. Dattaguru V Kamath and +1
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- Residue Number System
- by Ja-Ling Wu
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- Number Theory, Computer Science, Signal Processing, Digital Signal Processing
- by Alberto Nannarelli and +1
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- Circuits and Systems, Residue Number System, FIR filter, Power Dissipation
- by Alberto Nannarelli and +1
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- Residue Number System, Power Consumption, Low Power, FIR filter
- by Gian Cardarilli
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- Mathematics, Computer Science, Distributed Computing, Residue Number System
- by Lajos Hanzo
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- Signal Processing, Channel Coding, Residue Number System, Communication System