LLVM: lib/Target/AMDGPU/SIRegisterInfo.cpp File Reference (original) (raw)

SI implementation of the TargetRegisterInfo class. More...

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Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
Macros
#define GET_REGINFO_TARGET_DESC
Functions
static void emitUnsupportedError (const Function &Fn, const MachineInstr &MI, const Twine &ErrMsg)
static bool isFIPlusImmOrVGPR (const SIRegisterInfo &TRI, const MachineInstr &MI)
static unsigned getNumSubRegsForSpillOp (const MachineInstr &MI, const SIInstrInfo *TII)
static int getOffsetMUBUFStore (unsigned Opc)
static int getOffsetMUBUFLoad (unsigned Opc)
static int getOffenMUBUFStore (unsigned Opc)
static int getOffenMUBUFLoad (unsigned Opc)
static MachineInstrBuilder spillVGPRtoAGPR (const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
static bool buildMUBUFOffsetLoadStore (const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned getFlatScratchSpillOpcode (const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static const TargetRegisterClass * getAnyVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass * getAlignedVGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass * getAnyAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass * getAlignedAGPRClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth (unsigned BitWidth)
static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth (unsigned BitWidth)

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

◆ GET_REGINFO_TARGET_DESC

#define GET_REGINFO_TARGET_DESC

◆ buildMUBUFOffsetLoadStore()

Definition at line 1434 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::MachineInstrBuilder::getInstr(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), MBB, MI, llvm::Offset, Opc, Reg, spillVGPRtoAGPR(), and TII.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ emitUnsupportedError()

◆ getAlignedAGPRClassForBitWidth()

◆ getAlignedVectorSuperClassForBitWidth()

◆ getAlignedVGPRClassForBitWidth()

◆ getAnyAGPRClassForBitWidth()

◆ getAnyVectorSuperClassForBitWidth()

◆ getAnyVGPRClassForBitWidth()

◆ getFlatScratchSpillOpcode()

◆ getNumSubRegsForSpillOp()

◆ getOffenMUBUFLoad()

int getOffenMUBUFLoad ( unsigned Opc) static

◆ getOffenMUBUFStore()

int getOffenMUBUFStore ( unsigned Opc) static

◆ getOffsetMUBUFLoad()

int getOffsetMUBUFLoad ( unsigned Opc) static

◆ getOffsetMUBUFStore()

int getOffsetMUBUFStore ( unsigned Opc) static

◆ isFIPlusImmOrVGPR()

◆ spillVGPRtoAGPR()

Definition at line 1391 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill(), MBB, MI, MRI, Opc, Reg, llvm::MachineInstr::ReloadReuse, llvm::MachineInstr::setAsmPrinterFlag(), TII, and TRI.

Referenced by buildMUBUFOffsetLoadStore(), and llvm::SIRegisterInfo::buildSpillLoadStore().

◆ EnableSpillSGPRToVGPR

cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true)) ( "amdgpu-spill-sgpr-to-vgpr" , cl::desc("Enable spilling SGPRs to VGPRs") , cl::ReallyHidden , cl::init(true) ) static

◆ SubRegFromChannelTableWidthMap

Initial value:

= {

0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9}

Definition at line 45 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().