LLVM: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp File Reference (original) (raw)

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Macros
#define DEBUG_TYPE "pre-RA-sched"
Functions
STATISTIC (NumBacktracks, "Number of times scheduler backtracked")
STATISTIC (NumUnfolds, "Number of nodes unfolded")
STATISTIC (NumDups, "Number of duplicated nodes")
STATISTIC (NumPRCopies, "Number of physical register copies")
static void GetCostForDef (const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF)
GetCostForDef - Looks up the register class and cost for a given definition.
static bool IsChainDependent (SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII)
IsChainDependent - Test if Outer is reachable from Inner through chain dependencies.
static SDNode * FindCallSeqStart (SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII)
FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.
static void resetVRegCycle (SUnit *SU)
static bool isOperandOf (const SUnit *SU, SDNode *N)
static MVT getPhysicalRegisterVT (SDNode *N, unsigned Reg, const TargetInstrInfo *TII)
getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node.
static void CheckForLiveRegDef (SUnit *SU, MCRegister Reg, SUnit **LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs, const TargetRegisterInfo *TRI, const SDNode *Node=nullptr)
CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers.
static void CheckForLiveRegDefMasked (SUnit *SU, const uint32_t *RegMask, ArrayRef< SUnit * > LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs)
CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs.
static const uint32_t * getNodeRegMask (const SDNode *N)
getNodeRegMask - Returns the register mask attached to an SDNode, if any.
static int checkSpecialNodes (const SUnit *left, const SUnit *right)
static unsigned CalcNodeSethiUllmanNumber (const SUnit *SU, std::vector< unsigned > &SUNumbers)
CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
static unsigned closestSucc (const SUnit *SU)
closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle.
static unsigned calcMaxScratches (const SUnit *SU)
calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e.
static bool hasOnlyLiveInOpers (const SUnit *SU)
hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register.
static bool hasOnlyLiveOutUses (const SUnit *SU)
hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register.
static void initVRegCycle (SUnit *SU)
static bool hasVRegCycleUse (const SUnit *SU)
static bool BUHasStall (SUnit *SU, int Height, RegReductionPQBase *SPQ)
static int BUCompareLatency (SUnit *left, SUnit *right, bool checkPref, RegReductionPQBase *SPQ)
static bool BURRSort (SUnit *left, SUnit *right, RegReductionPQBase *SPQ)
static bool canEnableCoalescing (SUnit *SU)
static bool canClobberReachingPhysRegUse (const SUnit *DepSU, const SUnit *SU, ScheduleDAGRRList *scheduleDAG, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU.
static bool canClobberPhysRegDefs (const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs.
Variables
static RegisterScheduler burrListDAGScheduler ("list-burr", "Bottom-up register reduction list scheduling", createBURRListDAGScheduler)
static RegisterScheduler sourceListDAGScheduler ("source", "Similar to list-burr but schedules in source " "order when possible", createSourceListDAGScheduler)
static RegisterScheduler hybridListDAGScheduler ("list-hybrid", "Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure", createHybridListDAGScheduler)
static RegisterScheduler ILPListDAGScheduler ("list-ilp", "Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure", createILPListDAGScheduler)
static cl::opt< bool > DisableSchedCycles ("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling"))
static cl::opt< bool > DisableSchedRegPressure ("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp"))
static cl::opt< bool > DisableSchedLiveUses ("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp"))
static cl::opt< bool > DisableSchedVRegCycle ("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks"))
static cl::opt< bool > DisableSchedPhysRegJoin ("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity"))
static cl::opt< bool > DisableSchedStalls ("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp"))
static cl::opt< bool > DisableSchedCriticalPath ("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp"))
static cl::opt< bool > DisableSchedHeight ("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp"))
static cl::opt< bool > Disable2AddrHack ("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack"))
static cl::opt< int > MaxReorderWindow ("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp"))
static cl::opt< unsigned > AvgIPC ("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle when no target itinerary exists."))
static constexpr unsigned RegSequenceCost = 1

◆ DEBUG_TYPE

#define DEBUG_TYPE "pre-RA-sched"

◆ BUCompareLatency()

int BUCompareLatency ( SUnit * left, SUnit * right, bool checkPref, RegReductionPQBase * SPQ ) static

◆ BUHasStall()

bool BUHasStall ( SUnit * SU, int Height, RegReductionPQBase * SPQ ) static

◆ BURRSort()

bool BURRSort ( SUnit * left, SUnit * right, RegReductionPQBase * SPQ ) static

Definition at line 2541 of file ScheduleDAGRRList.cpp.

References assert(), BUCompareLatency(), calcMaxScratches(), closestSucc(), llvm::dbgs(), DisableSchedCycles, DisableSchedPhysRegJoin, llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), llvm::SUnit::getNode(), llvm::SDNode::getNumValues(), llvm::SUnit::hasPhysRegDefs, llvm::SUnit::isCall, llvm::SUnit::isCallOp, LLVM_DEBUG, llvm::SUnit::NodeNum, and llvm::SUnit::NodeQueueId.

◆ calcMaxScratches()

◆ CalcNodeSethiUllmanNumber()

CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.

Smaller number is the higher priority.

Definition at line 1952 of file ScheduleDAGRRList.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::SUnit::NodeNum, P, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ canClobberPhysRegDefs()

◆ canClobberReachingPhysRegUse()

canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU.

i.e. DepSU should not be scheduled above SU.

Definition at line 2856 of file ScheduleDAGRRList.cpp.

References llvm::MachineOperand::clobbersPhysReg(), llvm::ArrayRef< T >::empty(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), getNodeRegMask(), llvm::SDep::getReg(), llvm::SDep::getSUnit(), llvm::SDep::isAssignedRegDep(), llvm::SUnit::Preds, llvm::SUnit::Succs, TII, and TRI.

◆ canEnableCoalescing()

bool canEnableCoalescing ( SUnit * SU) static

◆ CheckForLiveRegDef()

◆ CheckForLiveRegDefMasked()

◆ checkSpecialNodes()

◆ closestSucc()

◆ FindCallSeqStart()

FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.

NestLevel and MaxNested are used in recursion to indcate the current level of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum level seen so far.

TODO: It would be better to give CALLSEQ_END an explicit operand to point to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.

Definition at line 491 of file ScheduleDAGRRList.cpp.

References assert(), llvm::ISD::EntryToken, FindCallSeqStart(), N, TII, and llvm::ISD::TokenFactor.

Referenced by FindCallSeqStart().

◆ GetCostForDef()

GetCostForDef - Looks up the register class and cost for a given definition.

Typically this just means looking up the representative register class, but for untyped values (MVT::Untyped) it means inspecting the node's opcode to determine what register class is being generated.

Definition at line 310 of file ScheduleDAGRRList.cpp.

References assert(), llvm::cast(), llvm::ISD::CopyFromReg, llvm::TargetRegisterClass::getID(), llvm::ScheduleDAGSDNodes::RegDefIter::GetIdx(), llvm::ScheduleDAGSDNodes::RegDefIter::GetNode(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), llvm::ScheduleDAGSDNodes::RegDefIter::GetValue(), Reg, RegSequenceCost, TII, and TRI.

◆ getNodeRegMask()

◆ getPhysicalRegisterVT()

◆ hasOnlyLiveInOpers()

◆ hasOnlyLiveOutUses()

◆ hasVRegCycleUse()

◆ initVRegCycle()

void initVRegCycle ( SUnit * SU) static

◆ IsChainDependent()

◆ isOperandOf()

◆ resetVRegCycle()

void resetVRegCycle ( SUnit * SU) static

◆ STATISTIC() [1/4]

STATISTIC ( NumBacktracks ,
"Number of times scheduler backtracked" )

◆ STATISTIC() [2/4]

STATISTIC ( NumDups ,
"Number of duplicated nodes" )

◆ STATISTIC() [3/4]

STATISTIC ( NumPRCopies ,
"Number of physical register copies" )

◆ STATISTIC() [4/4]

STATISTIC ( NumUnfolds ,
"Number of nodes unfolded" )

◆ AvgIPC

cl::opt< unsigned > AvgIPC("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle when no target itinerary exists.")) ( "sched-avg-ipc" , cl::Hidden , cl::init(1) , cl::desc("Average inst/cycle when no target itinerary exists.") ) static

◆ burrListDAGScheduler

RegisterScheduler burrListDAGScheduler("list-burr", "Bottom-up register reduction list scheduling", createBURRListDAGScheduler) ( "list-burr" , "Bottom-up register reduction list scheduling" , createBURRListDAGScheduler ) static

◆ Disable2AddrHack

cl::opt< bool > Disable2AddrHack("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack")) ( "disable-2addr-hack" , cl::Hidden , cl::init(true) , cl::desc("Disable scheduler's two-address hack") ) static

◆ DisableSchedCriticalPath

cl::opt< bool > DisableSchedCriticalPath("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp")) ( "disable-sched-critical-path" , cl::Hidden , cl::init(false) , cl::desc("Disable critical path priority in sched=list-ilp") ) static

◆ DisableSchedCycles

cl::opt< bool > DisableSchedCycles("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling")) ( "disable-sched-cycles" , cl::Hidden , cl::init(false) , cl::desc("Disable cycle-level precision during preRA scheduling") ) static

◆ DisableSchedHeight

cl::opt< bool > DisableSchedHeight("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp")) ( "disable-sched-height" , cl::Hidden , cl::init(false) , cl::desc("Disable scheduled-height priority in sched=list-ilp") ) static

◆ DisableSchedLiveUses

cl::opt< bool > DisableSchedLiveUses("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp")) ( "disable-sched-live-uses" , cl::Hidden , cl::init(true) , cl::desc("Disable live use priority in sched=list-ilp") ) static

◆ DisableSchedPhysRegJoin

cl::opt< bool > DisableSchedPhysRegJoin("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity")) ( "disable-sched-physreg-join" , cl::Hidden , cl::init(false) , cl::desc("Disable physreg def-use affinity") ) static

◆ DisableSchedRegPressure

cl::opt< bool > DisableSchedRegPressure("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp")) ( "disable-sched-reg-pressure" , cl::Hidden , cl::init(false) , cl::desc("Disable regpressure priority in sched=list-ilp") ) static

◆ DisableSchedStalls

cl::opt< bool > DisableSchedStalls("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp")) ( "disable-sched-stalls" , cl::Hidden , cl::init(true) , cl::desc("Disable no-stall priority in sched=list-ilp") ) static

◆ DisableSchedVRegCycle

cl::opt< bool > DisableSchedVRegCycle("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks")) ( "disable-sched-vrcycle" , cl::Hidden , cl::init(false) , cl::desc("Disable virtual register cycle interference checks") ) static

◆ hybridListDAGScheduler

RegisterScheduler hybridListDAGScheduler("list-hybrid", "Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure", createHybridListDAGScheduler) ( "list-hybrid" , "Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure" , createHybridListDAGScheduler ) static

◆ ILPListDAGScheduler

RegisterScheduler ILPListDAGScheduler("list-ilp", "Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure", createILPListDAGScheduler) ( "list-ilp" , "Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure" , createILPListDAGScheduler ) static

◆ MaxReorderWindow

cl::opt< int > MaxReorderWindow("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp")) ( "max-sched-reorder" , cl::Hidden , cl::init(6) , cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp") ) static

◆ RegSequenceCost

◆ sourceListDAGScheduler

RegisterScheduler sourceListDAGScheduler("source", "Similar to list-burr but schedules in source " "order when possible", createSourceListDAGScheduler) ( "source" , "Similar to list-burr but schedules in source " "order when possible" , createSourceListDAGScheduler ) static