X86AsmBackend.cpp Source File (original) (raw)

36using namespace llvm;

38namespace {

40class X86AlignBranchKind {

41private:

42 uint8_t AlignBranchKind = 0;

44public:

45 void operator=(const std::string &Val) {

46 if (Val.empty())

47 return;

50 for (auto BranchType : BranchTypes) {

51 if (BranchType == "fused")

53 else if (BranchType == "jcc")

55 else if (BranchType == "jmp")

57 else if (BranchType == "call")

59 else if (BranchType == "ret")

61 else if (BranchType == "indirect")

63 else {

65 << " to -x86-align-branch=; each element must be one of: fused, "

66 "jcc, jmp, call, ret, indirect.(plus separated)\n";

67 }

68 }

69 }

71 operator uint8_t() const { return AlignBranchKind; }

73};

75X86AlignBranchKind X86AlignBranchKindLoc;

78 "x86-align-branch-boundary", cl::init(0),

80 "Control how the assembler should align branches with NOP. If the "

81 "boundary's size is not 0, it should be a power of 2 and no less "

82 "than 32. Branches will be aligned to prevent from being across or "

83 "against the boundary of specified size. The default value 0 does not "

84 "align branches."));

87 "x86-align-branch",

89 "Specify types of branches to align (plus separated list of types):"

90 "\njcc indicates conditional jumps"

91 "\nfused indicates fused conditional jumps"

92 "\njmp indicates direct unconditional jumps"

93 "\ncall indicates direct and indirect calls"

94 "\nret indicates rets"

95 "\nindirect indicates indirect unconditional jumps"),

99 "x86-branches-within-32B-boundaries", cl::init(false),

101 "Align selected instructions to mitigate negative performance impact "

102 "of Intel's micro code update for errata skx102. May break "

103 "assumptions about labels corresponding to particular instructions, "

104 "and should be used with caution."));

105

107 "x86-pad-max-prefix-size", cl::init(0),

108 cl::desc("Maximum number of prefixes to use for padding"));

109

112 cl::desc("Pad previous instructions to implement align directives"));

113

116 cl::desc("Pad previous instructions to implement branch alignment"));

117

120 std::unique_ptr MCII;

121 X86AlignBranchKind AlignBranchType;

122 Align AlignBoundary;

123 unsigned TargetPrefixMax = 0;

124

126 unsigned PrevInstOpcode = 0;

128 std::pair<MCFragment *, size_t> PrevInstPosition;

129 bool IsRightAfterData = false;

130

131 uint8_t determinePaddingPrefix(const MCInst &Inst) const;

133 bool needAlign(const MCInst &Inst) const;

136

137public:

141 if (X86AlignBranchWithin32BBoundaries) {

142

143

144

145

150 }

151

152 if (X86AlignBranchBoundary.getNumOccurrences())

153 AlignBoundary = assumeAligned(X86AlignBranchBoundary);

154 if (X86AlignBranch.getNumOccurrences())

155 AlignBranchType = X86AlignBranchKindLoc;

156 if (X86PadMaxPrefixSize.getNumOccurrences())

157 TargetPrefixMax = X86PadMaxPrefixSize;

158 }

159

165

168 }

169

171

173

177

182

185

188

191

194 unsigned &RemainingSize) const;

195

197 unsigned &RemainingSize) const;

198

200 unsigned &RemainingSize) const;

201

203

205

208};

209}

210

212 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;

213}

214

216 bool Is16BitMode = false) {

217 switch (Opcode) {

218 default:

220 case X86::JCC_1:

221 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;

222 case X86::JMP_1:

223 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;

224 }

225}

226

228 unsigned Opcode = MI.getOpcode();

231}

232

235 unsigned Opcode = MI.getOpcode();

236 switch (Opcode) {

237 default:

239 case X86::JCC_1: {

242 MI.getOperand(Desc.getNumOperands() - 1).getImm());

243 }

244 }

245}

246

250 return classifySecondCondCodeInMacroFusion(CC);

251}

252

253

255 unsigned Opcode = MI.getOpcode();

260 if (MemoryOperand < 0)

261 return false;

262 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg;

263 MCRegister BaseReg = MI.getOperand(BaseRegNum).getReg();

264 return (BaseReg == X86::RIP);

265}

266

267

270}

271

272

275

277 return false;

280 return FIK != X86::FirstMacroFusionInstKind::Invalid;

281}

282

283

284

285

286

287

288

289

290

291

292uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {

294 "Prefixes can be added only in 32-bit or 64-bit mode.");

297

298

300 if (MemoryOperand != -1)

302

304 if (MemoryOperand >= 0) {

305

307 }

308

310 default:

311 break;

313

316 break;

317 }

319

322 break;

323 }

325

327 break;

328 }

329 }

330

331 if (SegmentReg)

333

336

337 if (MemoryOperand >= 0) {

340 if (BaseReg == X86::ESP || BaseReg == X86::EBP)

342 }

344}

345

346

347bool X86AsmBackend::isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const {

350 return false;

352 return false;

358}

359

360

362 for (auto &Operand : MI) {

363 if (!Operand.isExpr())

364 continue;

365 const MCExpr &Expr = *Operand.getExpr();

368 return true;

369 }

370 return false;

371}

372

373bool X86AsmBackend::allowAutoPadding() const {

375}

376

377bool X86AsmBackend::allowEnhancedRelaxation() const {

378 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;

379}

380

381

382

383

385 switch (InstOpcode) {

386 case X86::POPSS16:

387 case X86::POPSS32:

388 case X86::STI:

389 return true;

390

391 case X86::MOV16sr:

392 case X86::MOV32sr:

393 case X86::MOV64sr:

394 case X86::MOV16sm:

395

396

397 return true;

398 }

399 return false;

400}

401

402

403static bool

405 const std::pair<MCFragment *, size_t> &PrevInstPosition) {

407

408

409

410

411

412

413

414

415

416

417

418 if (auto *DF = dyn_cast_or_null(F))

419 return DF->getContents().size() &&

420 (DF != PrevInstPosition.first ||

421 DF->getContents().size() != PrevInstPosition.second);

422

423 return false;

424}

425

426

428 if ( || ->hasInstructions())

429 return 0;

430

431 switch (F->getKind()) {

432 default:

435 return cast(*F).getContents().size();

437 return cast(*F).getContents().size();

438 }

439}

440

441

442

445

446

447 return false;

448

450

451

452 return false;

453

454 if (isPrefix(PrevInstOpcode, *MCII))

455

456

457 return false;

458

460

461

462 return false;

463

464 if (IsRightAfterData)

465

466

467 return false;

468

469 return true;

470}

471

473 if (.getAllowAutoPadding())

474 return false;

475 assert(allowAutoPadding() && "incorrect initialization!");

476

477

478 if (.getCurrentSectionOnly()->isText())

479 return false;

480

481

482 if (OS.getAssembler().isBundlingEnabled())

483 return false;

484

485

487 return false;

488

489 return true;

490}

491

492

493bool X86AsmBackend::needAlign(const MCInst &Inst) const {

495 return (Desc.isConditionalBranch() &&

497 (Desc.isUnconditionalBranch() &&

501 (Desc.isIndirectBranch() &&

503}

504

505

508

509

510 IsRightAfterData =

512

513 if (!canPadBranches(OS))

514 return;

515

516

518

519 PendingBA = nullptr;

520

521

522

523

524

525 if (!canPadInst(Inst, OS))

526 return;

527

528 if (PendingBA && PendingBA->getNext() == OS.getCurrentFragment()) {

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547 return;

548 }

549

552

553

555 AlignBoundary, STI);

556 OS.insert(PendingBA);

557 }

558}

559

560

562 const MCInst &Inst) {

564 if (auto *F = dyn_cast_or_null(CF))

565 F->setAllowAutoPadding(canPadInst(Inst, OS));

566

567

568 PrevInstOpcode = Inst.getOpcode();

570

571 if (!canPadBranches(OS))

572 return;

573

574

575 PrevInst = Inst;

576

577 if (!needAlign(Inst) || !PendingBA)

578 return;

579

580

582 PendingBA = nullptr;

583

584

585

586

587

588 if (isa_and_nonnull(CF))

590

591

592 MCSection *Sec = OS.getCurrentSectionOnly();

594}

595

596std::optional X86AsmBackend::getFixupKind(StringRef Name) const {

598 unsigned Type;

601#define ELF_RELOC(X, Y) .Case(#X, Y)

602#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"

603#undef ELF_RELOC

604 .Case("BFD_RELOC_NONE", ELF::R_X86_64_NONE)

605 .Case("BFD_RELOC_8", ELF::R_X86_64_8)

606 .Case("BFD_RELOC_16", ELF::R_X86_64_16)

607 .Case("BFD_RELOC_32", ELF::R_X86_64_32)

608 .Case("BFD_RELOC_64", ELF::R_X86_64_64)

610 } else {

612#define ELF_RELOC(X, Y) .Case(#X, Y)

613#include "llvm/BinaryFormat/ELFRelocs/i386.def"

614#undef ELF_RELOC

615 .Case("BFD_RELOC_NONE", ELF::R_386_NONE)

616 .Case("BFD_RELOC_8", ELF::R_386_8)

617 .Case("BFD_RELOC_16", ELF::R_386_16)

618 .Case("BFD_RELOC_32", ELF::R_386_32)

620 }

621 if (Type == -1u)

622 return std::nullopt;

624 }

626}

627

630

638 {"reloc_signed_4byte", 0, 32, 0},

639 {"reloc_signed_4byte_relax", 0, 32, 0},

640 {"reloc_global_offset_table", 0, 32, 0},

641 {"reloc_global_offset_table8", 0, 64, 0},

643

644 };

645

646

647

650

653

655 "Invalid kind!");

658}

659

660bool X86AsmBackend::shouldForceRelocation(const MCAssembler &,

665}

666

668 switch (Kind) {

669 default:

672 return 0;

676 return 1;

680 return 2;

695 return 4;

700 return 8;

701 }

702}

703

711 return;

713

714 assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!");

715

716 int64_t SignedValue = static_cast<int64_t>(Value);

717 if ((Target.isAbsolute() || IsResolved) &&

718 getFixupKindInfo(Fixup.getKind()).Flags &

720

722 Asm.getContext().reportError(

723 Fixup.getLoc(), "value of " + Twine(SignedValue) +

724 " is too large for field of " + Twine(Size) +

725 ((Size == 1) ? " byte." : " bytes."));

726 } else {

727

728

729

730

732 "Value does not fit in the Fixup field");

733 }

734

735 for (unsigned i = 0; i != Size; ++i)

737}

738

739bool X86AsmBackend::mayNeedRelaxation(const MCInst &MI,

741 unsigned Opcode = MI.getOpcode();

742 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;

745 MI.getOperand(MI.getNumOperands() - 1 - SkipOperands).isExpr());

746}

747

748bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,

750

751 return !isInt<8>(Value);

752}

753

754

755

756void X86AsmBackend::relaxInstruction(MCInst &Inst,

758

759 bool Is16BitMode = STI.hasFeature(X86::Is16Bit);

761

762 if (RelaxedOp == Inst.getOpcode()) {

766 OS << "\n";

768 }

769

771}

772

775 unsigned &RemainingSize) const {

777 return false;

778

779

780

781

783 return false;

784

786 if (OldSize == 15)

787 return false;

788

789 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);

790 const unsigned RemainingPrefixSize = [&]() -> unsigned {

793 assert(Code.size() < 15 && "The number of prefixes must be less than 15.");

794

795

796

797

798

799

800 unsigned ExistingPrefixSize = Code.size();

801 if (TargetPrefixMax <= ExistingPrefixSize)

802 return 0;

803 return TargetPrefixMax - ExistingPrefixSize;

804 }();

805 const unsigned PrefixBytesToAdd =

806 std::min(MaxPossiblePad, RemainingPrefixSize);

807 if (PrefixBytesToAdd == 0)

808 return false;

809

811

813 Code.append(PrefixBytesToAdd, Prefix);

816

817

819 F.setOffset(F.getOffset() + PrefixBytesToAdd);

820 }

821

822 RemainingSize -= PrefixBytesToAdd;

823 return true;

824}

825

828 unsigned &RemainingSize) const {

830

831

832 return false;

833

836

841 const unsigned NewSize = Code.size();

842 assert(NewSize >= OldSize && "size decrease during relaxation?");

843 unsigned Delta = NewSize - OldSize;

844 if (Delta > RemainingSize)

845 return false;

849 RemainingSize -= Delta;

850 return true;

851}

852

855 unsigned &RemainingSize) const {

856 bool Changed = false;

857 if (RemainingSize != 0)

858 Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);

859 if (RemainingSize != 0)

860 Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);

861 return Changed;

862}

863

864void X86AsmBackend::finishLayout(MCAssembler const &Asm) const {

865

866

867

868

869

870

871 if (!X86PadForAlign && !X86PadForBranchAlign)

872 return;

873

874

875

876

879 LabeledFragments.insert(S.getFragment(false));

880

883 continue;

884

888

889 if (LabeledFragments.count(&F))

890 Relaxable.clear();

891

893 continue;

894

896 auto &RF = cast(*I);

898 continue;

899 }

900

901 auto canHandle = [](MCFragment &F) -> bool {

902 switch (F.getKind()) {

903 default:

904 return false;

906 return X86PadForAlign;

908 return X86PadForBranchAlign;

909 }

910 };

911

912 if (!canHandle(F)) {

913 Relaxable.clear();

914 continue;

915 }

916

917#ifndef NDEBUG

918 const uint64_t OrigOffset = Asm.getFragmentOffset(F);

919#endif

920 const uint64_t OrigSize = Asm.computeFragmentSize(F);

921

922

923

924

925

926 unsigned RemainingSize = OrigSize;

927 while (!Relaxable.empty() && RemainingSize != 0) {

929

930

931

932 if (padInstructionEncoding(RF, Asm.getEmitter(), RemainingSize))

934

935

936

937

938

939

940

942 break;

943 }

944 Relaxable.clear();

945

946

948 cast(F).setSize(RemainingSize);

949

950#ifndef NDEBUG

951 const uint64_t FinalOffset = Asm.getFragmentOffset(F);

952 const uint64_t FinalSize = Asm.computeFragmentSize(F);

953 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&

954 "can't move start of next fragment!");

955 assert(FinalSize == RemainingSize && "inconsistent size computation?");

956#endif

957

958

959

960

961 if (auto *BF = dyn_cast(&F)) {

962 const MCFragment *LastFragment = BF->getLastFragment();

963 if (!LastFragment)

964 continue;

965 while (&*I != LastFragment)

966 ++I;

967 }

968 }

969 }

970

971

973 Asm.getFragmentOffset(*Section.curFragList()->Tail);

974 Asm.computeFragmentSize(*Section.curFragList()->Tail);

975 }

976}

977

978unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {

980 return 4;

982 return 1;

983 if (STI.hasFeature(X86::TuningFast7ByteNOP))

984 return 7;

985 if (STI.hasFeature(X86::TuningFast15ByteNOP))

986 return 15;

987 if (STI.hasFeature(X86::TuningFast11ByteNOP))

988 return 11;

989

990

991

992 return 10;

993}

994

995

996

997

1000 static const char Nops32Bit[10][11] = {

1001

1002 "\x90",

1003

1004 "\x66\x90",

1005

1006 "\x0f\x1f\x00",

1007

1008 "\x0f\x1f\x40\x00",

1009

1010 "\x0f\x1f\x44\x00\x00",

1011

1012 "\x66\x0f\x1f\x44\x00\x00",

1013

1014 "\x0f\x1f\x80\x00\x00\x00\x00",

1015

1016 "\x0f\x1f\x84\x00\x00\x00\x00\x00",

1017

1018 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",

1019

1020 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",

1021 };

1022

1023

1024 static const char Nops16Bit[4][11] = {

1025

1026 "\x90",

1027

1028 "\x66\x90",

1029

1030 "\x8d\x74\x00",

1031

1032 "\x8d\xb4\x00\x00",

1033 };

1034

1035 const char(*Nops)[11] =

1036 STI->hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;

1037

1039

1040

1041

1042 do {

1043 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);

1044 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;

1045 for (uint8_t i = 0; i < Prefixes; i++)

1046 OS << '\x66';

1047 const uint8_t Rest = ThisNopLength - Prefixes;

1048 if (Rest != 0)

1049 OS.write(Nops[Rest - 1], Rest);

1050 Count -= ThisNopLength;

1051 } while (Count != 0);

1052

1053 return true;

1054}

1055

1056

1057

1058namespace {

1059

1060class ELFX86AsmBackend : public X86AsmBackend {

1061public:

1064 : X86AsmBackend(T, STI), OSABI(OSABI) {}

1065};

1066

1067class ELFX86_32AsmBackend : public ELFX86AsmBackend {

1068public:

1071 : ELFX86AsmBackend(T, OSABI, STI) {}

1072

1073 std::unique_ptr

1074 createObjectTargetWriter() const override {

1076 }

1077};

1078

1079class ELFX86_X32AsmBackend : public ELFX86AsmBackend {

1080public:

1081 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,

1083 : ELFX86AsmBackend(T, OSABI, STI) {}

1084

1085 std::unique_ptr

1086 createObjectTargetWriter() const override {

1089 }

1090};

1091

1092class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {

1093public:

1094 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,

1096 : ELFX86AsmBackend(T, OSABI, STI) {}

1097

1098 std::unique_ptr

1099 createObjectTargetWriter() const override {

1102 }

1103};

1104

1105class ELFX86_64AsmBackend : public ELFX86AsmBackend {

1106public:

1109 : ELFX86AsmBackend(T, OSABI, STI) {}

1110

1111 std::unique_ptr

1112 createObjectTargetWriter() const override {

1114 }

1115};

1116

1117class WindowsX86AsmBackend : public X86AsmBackend {

1118 bool Is64Bit;

1119

1120public:

1123 : X86AsmBackend(T, STI)

1125 }

1126

1127 std::optional getFixupKind(StringRef Name) const override {

1133 }

1134

1135 std::unique_ptr

1136 createObjectTargetWriter() const override {

1138 }

1139};

1140

1141namespace CU {

1142

1143

1145

1146

1147 UNWIND_MODE_BP_FRAME = 0x01000000,

1148

1149

1150 UNWIND_MODE_STACK_IMMD = 0x02000000,

1151

1152

1153 UNWIND_MODE_STACK_IND = 0x03000000,

1154

1155

1156 UNWIND_MODE_DWARF = 0x04000000,

1157

1158

1159 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,

1160

1161

1162 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF

1163 };

1164

1165}

1166

1167class DarwinX86AsmBackend : public X86AsmBackend {

1169

1170

1171 enum { CU_NUM_SAVED_REGS = 6 };

1172

1173 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];

1175 bool Is64Bit;

1176

1177 unsigned OffsetSize;

1178 unsigned MoveInstrSize;

1179 unsigned StackDivide;

1180protected:

1181

1182 unsigned PushInstrSize(unsigned Reg) const {

1183 switch (Reg) {

1184 case X86::EBX:

1185 case X86::ECX:

1186 case X86::EDX:

1187 case X86::EDI:

1188 case X86::ESI:

1189 case X86::EBP:

1190 case X86::RBX:

1191 case X86::RBP:

1192 return 1;

1193 case X86::R12:

1194 case X86::R13:

1195 case X86::R14:

1196 case X86::R15:

1197 return 2;

1198 }

1199 return 1;

1200 }

1201

1202private:

1203

1204

1205 int getCompactUnwindRegNum(unsigned Reg) const {

1206 static const MCPhysReg CU32BitRegs[7] = {

1207 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0

1208 };

1209 static const MCPhysReg CU64BitRegs[] = {

1210 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0

1211 };

1212 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;

1213 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)

1214 if (*CURegs == Reg)

1215 return Idx;

1216

1217 return -1;

1218 }

1219

1220

1221

1222 uint32_t encodeCompactUnwindRegistersWithFrame() const {

1223

1224

1225

1227 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {

1228 unsigned Reg = SavedRegs[i];

1229 if (Reg == 0) break;

1230

1231 int CURegNum = getCompactUnwindRegNum(Reg);

1232 if (CURegNum == -1) return ~0U;

1233

1234

1235

1236 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);

1237 }

1238

1239 assert((RegEnc & 0x3FFFF) == RegEnc &&

1240 "Invalid compact register encoding!");

1241 return RegEnc;

1242 }

1243

1244

1245

1246

1247 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {

1248

1249

1250

1251

1252

1253

1254

1255

1256

1257

1258

1259

1260

1261 for (unsigned i = 0; i < RegCount; ++i) {

1262 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);

1263 if (CUReg == -1) return ~0U;

1264 SavedRegs[i] = CUReg;

1265 }

1266

1267

1268 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);

1269

1270 uint32_t RenumRegs[CU_NUM_SAVED_REGS];

1271 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){

1272 unsigned Countless = 0;

1273 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)

1274 if (SavedRegs[j] < SavedRegs[i])

1275 ++Countless;

1276

1277 RenumRegs[i] = SavedRegs[i] - Countless - 1;

1278 }

1279

1280

1281 uint32_t permutationEncoding = 0;

1282 switch (RegCount) {

1283 case 6:

1284 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]

1285 + 6 * RenumRegs[2] + 2 * RenumRegs[3]

1286 + RenumRegs[4];

1287 break;

1288 case 5:

1289 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]

1290 + 6 * RenumRegs[3] + 2 * RenumRegs[4]

1291 + RenumRegs[5];

1292 break;

1293 case 4:

1294 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]

1295 + 3 * RenumRegs[4] + RenumRegs[5];

1296 break;

1297 case 3:

1298 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]

1299 + RenumRegs[5];

1300 break;

1301 case 2:

1302 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];

1303 break;

1304 case 1:

1305 permutationEncoding |= RenumRegs[5];

1306 break;

1307 }

1308

1309 assert((permutationEncoding & 0x3FF) == permutationEncoding &&

1310 "Invalid compact register encoding!");

1311 return permutationEncoding;

1312 }

1313

1314public:

1317 : X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()),

1318 Is64Bit(TT.isArch64Bit()) {

1319 memset(SavedRegs, 0, sizeof(SavedRegs));

1320 OffsetSize = Is64Bit ? 8 : 4;

1321 MoveInstrSize = Is64Bit ? 3 : 2;

1322 StackDivide = Is64Bit ? 8 : 4;

1323 }

1324

1325 std::unique_ptr

1326 createObjectTargetWriter() const override {

1330 }

1331

1332

1333

1335 const MCContext *Ctxt) const override {

1337 if (Instrs.empty()) return 0;

1338 if (!isDarwinCanonicalPersonality(FI->Personality) &&

1340 return CU::UNWIND_MODE_DWARF;

1341

1342

1343 unsigned SavedRegIdx = 0;

1344 memset(SavedRegs, 0, sizeof(SavedRegs));

1345

1346 bool HasFP = false;

1347

1348

1349 uint64_t CompactUnwindEncoding = 0;

1350

1351 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;

1352 unsigned InstrOffset = 0;

1353 unsigned StackAdjust = 0;

1355 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();

1356

1358 switch (Inst.getOperation()) {

1359 default:

1360

1361

1362 return CU::UNWIND_MODE_DWARF;

1364

1365

1366

1367

1368

1369

1371

1372

1373

1374 if (*MRI.getLLVMRegNum(Inst.getRegister(), true) !=

1375 (Is64Bit ? X86::RBP : X86::EBP))

1376 return CU::UNWIND_MODE_DWARF;

1377

1378

1379 memset(SavedRegs, 0, sizeof(SavedRegs));

1380 StackAdjust = 0;

1381 SavedRegIdx = 0;

1382 MinAbsOffset = std::numeric_limits<int64_t>::max();

1383 InstrOffset += MoveInstrSize;

1384 break;

1385 }

1387

1388

1389

1390

1391

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401 StackSize = Inst.getOffset() / StackDivide;

1402 break;

1403 }

1405

1406

1407

1408

1409

1410

1411

1412

1413

1414

1415

1416

1417 if (SavedRegIdx == CU_NUM_SAVED_REGS)

1418

1419

1420 return CU::UNWIND_MODE_DWARF;

1421

1422 MCRegister Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);

1423 SavedRegs[SavedRegIdx++] = Reg;

1424 StackAdjust += OffsetSize;

1425 MinAbsOffset = std::min(MinAbsOffset, std::abs(Inst.getOffset()));

1426 InstrOffset += PushInstrSize(Reg);

1427 break;

1428 }

1429 }

1430 }

1431

1432 StackAdjust /= StackDivide;

1433

1434 if (HasFP) {

1435 if ((StackAdjust & 0xFF) != StackAdjust)

1436

1437 return CU::UNWIND_MODE_DWARF;

1438

1439

1440

1441 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (int)OffsetSize)

1442 return CU::UNWIND_MODE_DWARF;

1443

1444

1445 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();

1446 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;

1447

1448 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;

1449 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;

1450 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;

1451 } else {

1452 SubtractInstrIdx += InstrOffset;

1453 ++StackAdjust;

1454

1455 if ((StackSize & 0xFF) == StackSize) {

1456

1457 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;

1458

1459

1460 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;

1461 } else {

1462 if ((StackAdjust & 0x7) != StackAdjust)

1463

1464 return CU::UNWIND_MODE_DWARF;

1465

1466

1467 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;

1468

1469

1470

1471 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;

1472

1473

1474 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;

1475 }

1476

1477

1478 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);

1479 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;

1480

1481

1482

1483 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);

1484 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;

1485

1486

1487 CompactUnwindEncoding |=

1488 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;

1489 }

1490

1491 return CompactUnwindEncoding;

1492 }

1493};

1494

1495}

1496

1503 return new DarwinX86AsmBackend(T, MRI, STI);

1504

1506 return new WindowsX86AsmBackend(T, false, STI);

1507

1509

1511 return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);

1512

1513 return new ELFX86_32AsmBackend(T, OSABI, STI);

1514}

1515

1522 return new DarwinX86AsmBackend(T, MRI, STI);

1523

1525 return new WindowsX86AsmBackend(T, true, STI);

1526

1527 if (TheTriple.isUEFI()) {

1529 "Only COFF format is supported in UEFI environment.");

1530 return new WindowsX86AsmBackend(T, true, STI);

1531 }

1532

1534

1535 if (TheTriple.isX32())

1536 return new ELFX86_X32AsmBackend(T, OSABI, STI);

1537 return new ELFX86_64AsmBackend(T, OSABI, STI);

1538}

1539

1540namespace {

1542public:

1543 X86ELFStreamer(MCContext &Context, std::unique_ptr TAB,

1544 std::unique_ptr OW,

1545 std::unique_ptr Emitter)

1548

1550};

1551}

1552

1556 Backend.emitInstructionBegin(S, Inst, STI);

1557 S.MCObjectStreamer::emitInstruction(Inst, STI);

1558 Backend.emitInstructionEnd(S, Inst);

1559}

1560

1561void X86ELFStreamer::emitInstruction(const MCInst &Inst,

1564}

1565

1567 std::unique_ptr &&MAB,

1568 std::unique_ptr &&MOW,

1569 std::unique_ptr &&MCE) {

1570 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),

1571 std::move(MCE));

1572}

unsigned const MachineRegisterInfo * MRI

dxil DXContainer Global Emitter

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")

PowerPC TLS Dynamic Call Fixup

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

static MCInstrInfo * createMCInstrInfo()

static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)

static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)

static size_t getSizeForInstFragment(const MCFragment *F)

static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)

Check if the instruction uses RIP relative addressing.

static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)

Check if the instruction to be emitted is right after any data.

static bool mayHaveInterruptDelaySlot(unsigned InstOpcode)

X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...

static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)

Check if the instruction is valid as the first instruction in macro fusion.

static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)

static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)

static unsigned getFixupKindSize(unsigned Kind)

static bool isRelaxableBranch(unsigned Opcode)

static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)

Check if the instruction is a prefix.

static bool hasVariantSymbol(const MCInst &MI)

Check if the instruction has a variant symbol operand.

static bool is64Bit(const char *name)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool empty() const

empty - Check if the array is empty.

Implements a dense probed hash-table based set.

Generic interface to target specific assembler backends.

virtual bool allowEnhancedRelaxation() const

Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...

virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const

Returns the maximum size of a nop in bytes on this target.

virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0

Write an (optimal) nop sequence of Count bytes to the given output.

virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const

Relax the instruction in the given fragment to the next wider instruction.

virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const

Check whether the given instruction may need relaxation.

virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI)

Hook to check if a relocation is needed for some target specific reason.

virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const

Simple predicate for targets where !Resolved implies requiring relaxation.

virtual void finishLayout(MCAssembler const &Asm) const

Give backend an opportunity to finish layout after relaxation.

virtual unsigned getNumFixupKinds() const =0

Get the number of target specific fixup kinds.

virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const

Map a relocation name used in .reloc to a fixup kind.

virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0

Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...

virtual bool allowAutoPadding() const

Return true if this target might automatically pad instructions and thus need to emit padding enable/...

MCAsmBackend & getBackend() const

Represents required padding such that a particular other set of fragments does not cross a particular...

void setLastFragment(const MCFragment *F)

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

bool emitCompactUnwindNonCanonical() const

Fragment for data and encoded instructions.

void setContents(ArrayRef< char > C)

SmallVectorImpl< MCFixup > & getFixups()

SmallVectorImpl< char > & getContents()

const MCSubtargetInfo * getSubtargetInfo() const

Retrieve the MCSubTargetInfo in effect when the instruction was encoded.

Base class for the full range of assembler expressions which are needed for parsing.

@ SymbolRef

References to labels and assigned expressions.

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

MCFragment * getNext() const

Instances of this class represent a single low-level machine instruction.

void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const

Dump the MCInst as prettily as possible using the additional MC structures, if given.

unsigned getOpcode() const

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Describe properties that are true of each instruction in the target description file.

bool isConditionalBranch() const

Return true if this is a branch which may fall through to the next instruction or may transfer contro...

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Streaming object file generation interface.

MCAssembler & getAssembler()

void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override

Emit the given Instruction into the current section.

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...

bool getAllowAutoPadding() const

const MCInst & getInst() const

void setInst(const MCInst &Value)

Instances of this class represent a uniqued identifier for a section in the current translation unit.

void ensureMinAlignment(Align MinAlignment)

Makes sure that Alignment is at least MinAlignment.

void setHasLayout(bool Value)

Streaming machine code generation interface.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

This represents an "assembler immediate".

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

bool isX32() const

Tests whether the target is X32.

bool isOSBinFormatMachO() const

Tests whether the environment is MachO.

OSType getOS() const

Get the parsed operating system type of this triple.

ArchType getArch() const

Get the parsed architecture type of this triple.

bool isOSBinFormatCOFF() const

Tests whether the OS uses the COFF binary format.

bool isUEFI() const

Tests whether the OS is UEFI.

bool isOSWindows() const

Tests whether the OS is Windows.

bool isOSBinFormatELF() const

Tests whether the OS uses the ELF binary format.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

std::pair< iterator, bool > insert(const ValueT &V)

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

This class implements an extremely fast bulk output stream that can only output to a stream.

raw_ostream & write(unsigned char C)

A raw_ostream that writes to an SmallVector or SmallString.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

CompactUnwindEncodings

Compact unwind encoding values.

Expected< uint32_t > getCPUSubType(const Triple &T)

Expected< uint32_t > getCPUType(const Triple &T)

Reg

All possible values of the reg field in the ModR/M byte.

@ RawFrmDstSrc

RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...

@ RawFrmSrc

RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...

@ RawFrmMemOffs

RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...

bool isPrefix(uint64_t TSFlags)

int getMemoryOperandNo(uint64_t TSFlags)

unsigned getOperandBias(const MCInstrDesc &Desc)

Compute whether all of the def operands are repeated in the uses and therefore should be skipped.

void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)

void emitInstruction(MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)

FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)

AlignBranchBoundaryKind

Defines the possible values of the branch boundary alignment mask.

SecondMacroFusionInstKind

EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(MCRegister Reg)

Given a segment register, return the encoding of the segment override prefix for it.

unsigned getOpcodeForLongImmediateForm(unsigned Opcode)

bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)

@ reloc_global_offset_table8

@ reloc_riprel_4byte_movq_load_rex2

@ reloc_signed_4byte_relax

@ reloc_branch_4byte_pcrel

@ reloc_riprel_4byte_relax

@ reloc_riprel_4byte_relax_evex

@ reloc_riprel_4byte_relax_rex

@ reloc_global_offset_table

@ reloc_riprel_4byte_movq_load

@ reloc_riprel_4byte_relax_rex2

initializer< Ty > init(const Ty &Val)

LocationClass< Ty > location(Ty &L)

NodeAddr< CodeNode * > Code

This is an optimization pass for GlobalISel generic memory operations.

MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)

Construct an X86 Win COFF object writer.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)

MCFixupKind

Extensible enumeration to represent the type of a fixup.

@ FK_PCRel_4

A four-byte pc relative fixup.

@ FK_PCRel_2

A two-byte pc relative fixup.

@ FK_SecRel_2

A two-byte section relative fixup.

@ FirstLiteralRelocationKind

The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_SecRel_8

A eight-byte section relative fixup.

@ FK_PCRel_8

A eight-byte pc relative fixup.

@ FK_SecRel_4

A four-byte section relative fixup.

@ FK_PCRel_1

A one-byte pc relative fixup.

@ FK_SecRel_1

A one-byte section relative fixup.

@ FK_Data_2

A two-byte fixup.

raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

void cantFail(Error Err, const char *Msg=nullptr)

Report a fatal error if Err is a failure value.

std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)

Construct an X86 Mach-O object writer.

bool isIntN(unsigned N, int64_t x)

Checks if an signed integer fits into the given (dynamic) bit width.

OutputIt move(R &&Range, OutputIt Out)

Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.

std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)

Construct an X86 ELF object writer.

Align assumeAligned(uint64_t Value)

Treats the value 0 as a 1, so Align is always at least 1.

MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Implement std::hash so that hash_code can be used in STL containers.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Description of the encoding of one expression Op.

const MCSymbol * Personality

std::vector< MCCFIInstruction > Instructions

Target independent information on a fixup kind.

@ FKF_IsPCRel

Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...