LLVM: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Source File (original) (raw)
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36
37using namespace llvm;
38
39namespace {
40
41class X86AlignBranchKind {
42private:
43 uint8_t AlignBranchKind = 0;
44
45public:
46 void operator=(const std::string &Val) {
47 if (Val.empty())
48 return;
50 StringRef(Val).split(BranchTypes, '+', -1, false);
51 for (auto BranchType : BranchTypes) {
52 if (BranchType == "fused")
54 else if (BranchType == "jcc")
56 else if (BranchType == "jmp")
58 else if (BranchType == "call")
60 else if (BranchType == "ret")
62 else if (BranchType == "indirect")
64 else {
66 << " to -x86-align-branch=; each element must be one of: fused, "
67 "jcc, jmp, call, ret, indirect.(plus separated)\n";
68 }
69 }
70 }
71
72 operator uint8_t() const { return AlignBranchKind; }
74};
75
76X86AlignBranchKind X86AlignBranchKindLoc;
77
79 "x86-align-branch-boundary", cl::init(0),
81 "Control how the assembler should align branches with NOP. If the "
82 "boundary's size is not 0, it should be a power of 2 and no less "
83 "than 32. Branches will be aligned to prevent from being across or "
84 "against the boundary of specified size. The default value 0 does not "
85 "align branches."));
86
88 "x86-align-branch",
90 "Specify types of branches to align (plus separated list of types):"
91 "\njcc indicates conditional jumps"
92 "\nfused indicates fused conditional jumps"
93 "\njmp indicates direct unconditional jumps"
94 "\ncall indicates direct and indirect calls"
95 "\nret indicates rets"
96 "\nindirect indicates indirect unconditional jumps"),
98
100 "x86-branches-within-32B-boundaries", cl::init(false),
102 "Align selected instructions to mitigate negative performance impact "
103 "of Intel's micro code update for errata skx102. May break "
104 "assumptions about labels corresponding to particular instructions, "
105 "and should be used with caution."));
106
108 "x86-pad-max-prefix-size", cl::init(0),
109 cl::desc("Maximum number of prefixes to use for padding"));
110
113 cl::desc("Pad previous instructions to implement align directives"));
114
117 cl::desc("Pad previous instructions to implement branch alignment"));
118
120 const MCSubtargetInfo &STI;
121 std::unique_ptr MCII;
122 X86AlignBranchKind AlignBranchType;
123 Align AlignBoundary;
124 unsigned TargetPrefixMax = 0;
125
126 MCInst PrevInst;
127 unsigned PrevInstOpcode = 0;
128 MCBoundaryAlignFragment *PendingBA = nullptr;
129 std::pair<MCFragment *, size_t> PrevInstPosition;
130
131 uint8_t determinePaddingPrefix(const MCInst &Inst) const;
132 bool isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const;
133 bool needAlign(const MCInst &Inst) const;
134 bool canPadBranches(MCObjectStreamer &OS) const;
135 bool canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const;
136
137public:
138 X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
141 if (X86AlignBranchWithin32BBoundaries) {
142
143
144
145
150 }
151
152 if (X86AlignBranchBoundary.getNumOccurrences())
153 AlignBoundary = assumeAligned(X86AlignBranchBoundary);
154 if (X86AlignBranch.getNumOccurrences())
155 AlignBranchType = X86AlignBranchKindLoc;
156 if (X86PadMaxPrefixSize.getNumOccurrences())
157 TargetPrefixMax = X86PadMaxPrefixSize;
158
159 AllowAutoPadding =
161 AllowEnhancedRelaxation =
162 AllowAutoPadding && TargetPrefixMax != 0 && X86PadForBranchAlign;
163 }
164
165 void emitInstructionBegin(MCObjectStreamer &OS, const MCInst &Inst,
166 const MCSubtargetInfo &STI);
167 void emitInstructionEnd(MCObjectStreamer &OS, const MCInst &Inst);
168
169
170 std::optional getFixupKind(StringRef Name) const override;
171
172 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
173
174 std::optional evaluateFixup(const MCFragment &, MCFixup &, MCValue &,
175 uint64_t &) override;
176 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
177 uint8_t *Data, uint64_t Value, bool IsResolved) override;
178
180 const MCSubtargetInfo &STI) const override;
181
182 bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &,
183 const MCValue &, uint64_t,
184 bool) const override;
185
186 void relaxInstruction(MCInst &Inst,
187 const MCSubtargetInfo &STI) const override;
188
189 bool padInstructionViaRelaxation(MCFragment &RF, MCCodeEmitter &Emitter,
190 unsigned &RemainingSize) const;
191
192 bool padInstructionViaPrefix(MCFragment &RF, MCCodeEmitter &Emitter,
193 unsigned &RemainingSize) const;
194
195 bool padInstructionEncoding(MCFragment &RF, MCCodeEmitter &Emitter,
196 unsigned &RemainingSize) const;
197
198 bool finishLayout() const override;
199
200 unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const override;
201
202 bool writeNopData(raw_ostream &OS, uint64_t Count,
203 const MCSubtargetInfo *STI) const override;
204};
205}
206
208 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
209}
210
212 bool Is16BitMode = false) {
213 switch (Opcode) {
214 default:
216 case X86::JCC_1:
217 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
218 case X86::JMP_1:
219 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
220 }
221}
222
224 unsigned Opcode = MI.getOpcode();
227}
228
231 unsigned Opcode = MI.getOpcode();
232 switch (Opcode) {
233 default:
235 case X86::JCC_1: {
238 MI.getOperand(Desc.getNumOperands() - 1).getImm());
239 }
240 }
241}
242
246 return classifySecondCondCodeInMacroFusion(CC);
247}
248
249
251 unsigned Opcode = MI.getOpcode();
256 if (MemoryOperand < 0)
257 return false;
258 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg;
259 MCRegister BaseReg = MI.getOperand(BaseRegNum).getReg();
260 return (BaseReg == X86::RIP);
261}
262
263
267
268
271
273 return false;
277}
278
279
280
281
282
283
284
285
286
287
288uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
290 "Prefixes can be added only in 32-bit or 64-bit mode.");
291 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode());
292 uint64_t TSFlags = Desc.TSFlags;
293
294
296 if (MemoryOperand != -1)
298
299 MCRegister SegmentReg;
300 if (MemoryOperand >= 0) {
301
303 }
304
306 default:
307 break;
309
312 break;
313 }
315
318 break;
319 }
321
323 break;
324 }
325 }
326
327 if (SegmentReg)
329
332
333 if (MemoryOperand >= 0) {
336 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
338 }
340}
341
342
343bool X86AsmBackend::isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const {
344 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode());
346 return false;
348 return false;
354}
355
356
358 for (auto &Operand : MI) {
359 if (!Operand.isExpr())
360 continue;
361 const MCExpr &Expr = *Operand.getExpr();
364 return true;
365 }
366 return false;
367}
368
369
370
371
373 switch (InstOpcode) {
374 case X86::POPSS16:
375 case X86::POPSS32:
376 case X86::STI:
377 return true;
378
379 case X86::MOV16sr:
380 case X86::MOV32sr:
381 case X86::MOV64sr:
382 case X86::MOV16sm:
383
384
385 return true;
386 }
387 return false;
388}
389
390
391
392bool X86AsmBackend::canPadInst(const MCInst &Inst, MCObjectStreamer &OS) const {
394
395
396 return false;
397
399
400
401 return false;
402
403 if (isPrefix(PrevInstOpcode, *MCII))
404
405
406 return false;
407
409
410
411 return false;
412
413
414
417 Offset != PrevInstPosition.second))
418 return false;
419
420 return true;
421}
422
423bool X86AsmBackend::canPadBranches(MCObjectStreamer &OS) const {
425 return false;
426 assert(allowAutoPadding() && "incorrect initialization!");
427
428
430 return false;
431
432
434 return false;
435
436 return true;
437}
438
439
440bool X86AsmBackend::needAlign(const MCInst &Inst) const {
441 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode());
442 return (Desc.isConditionalBranch() &&
444 (Desc.isUnconditionalBranch() &&
448 (Desc.isIndirectBranch() &&
450}
451
455 if (LLVM_LIKELY(!AutoPadding && !X86PadForAlign)) {
456 S.MCObjectStreamer::emitInstruction(Inst, STI);
457 return;
458 }
459
460 auto &Backend = static_cast<X86AsmBackend &>(S.getAssembler().getBackend());
461 Backend.emitInstructionBegin(S, Inst, STI);
462 S.MCObjectStreamer::emitInstruction(Inst, STI);
463 Backend.emitInstructionEnd(S, Inst);
464}
465
466
467void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
469 bool CanPadInst = canPadInst(Inst, OS);
470 if (CanPadInst)
472
473 if (!canPadBranches(OS))
474 return;
475
476
477 if (!isMacroFused(PrevInst, Inst))
478
479 PendingBA = nullptr;
480
481
482
483
484
485 if (!CanPadInst)
486 return;
487
488 if (PendingBA) {
489 auto *NextFragment = PendingBA->getNext();
490 assert(NextFragment && "NextFragment should not be null");
492 return;
493
494
496 return;
497
498
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501
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510
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513
514
515
516 return;
517 }
518
521
522
523 PendingBA =
525 }
526}
527
528
529void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS,
530 const MCInst &Inst) {
531
533 PrevInstOpcode = Inst.getOpcode();
534 PrevInstPosition = std::make_pair(CF, OS.getCurFragSize());
535
536 if (!canPadBranches(OS))
537 return;
538
539
540 PrevInst = Inst;
541
542 if (!needAlign(Inst) || !PendingBA)
543 return;
544
545
547 PendingBA = nullptr;
548
549
550
551
552
554
555
557}
558
559std::optional X86AsmBackend::getFixupKind(StringRef Name) const {
561 unsigned Type;
563 Type = llvm::StringSwitch(Name)
564#define ELF_RELOC(X, Y) .Case(#X, Y)
565#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
566#undef ELF_RELOC
567 .Case("BFD_RELOC_NONE", ELF::R_X86_64_NONE)
568 .Case("BFD_RELOC_8", ELF::R_X86_64_8)
569 .Case("BFD_RELOC_16", ELF::R_X86_64_16)
570 .Case("BFD_RELOC_32", ELF::R_X86_64_32)
571 .Case("BFD_RELOC_64", ELF::R_X86_64_64)
572 .Default(-1u);
573 } else {
574 Type = llvm::StringSwitch(Name)
575#define ELF_RELOC(X, Y) .Case(#X, Y)
576#include "llvm/BinaryFormat/ELFRelocs/i386.def"
577#undef ELF_RELOC
578 .Case("BFD_RELOC_NONE", ELF::R_386_NONE)
579 .Case("BFD_RELOC_8", ELF::R_386_8)
580 .Case("BFD_RELOC_16", ELF::R_386_16)
581 .Case("BFD_RELOC_32", ELF::R_386_32)
582 .Default(-1u);
583 }
584 if (Type == -1u)
585 return std::nullopt;
587 }
589}
590
591MCFixupKindInfo X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
593
594 {"reloc_riprel_4byte", 0, 32, 0},
595 {"reloc_riprel_4byte_movq_load", 0, 32, 0},
596 {"reloc_riprel_4byte_movq_load_rex2", 0, 32, 0},
597 {"reloc_riprel_4byte_relax", 0, 32, 0},
598 {"reloc_riprel_4byte_relax_rex", 0, 32, 0},
599 {"reloc_riprel_4byte_relax_rex2", 0, 32, 0},
600 {"reloc_riprel_4byte_relax_evex", 0, 32, 0},
601 {"reloc_signed_4byte", 0, 32, 0},
602 {"reloc_signed_4byte_relax", 0, 32, 0},
603 {"reloc_global_offset_table", 0, 32, 0},
604 {"reloc_branch_4byte_pcrel", 0, 32, 0},
605
606 };
607
608
609
611 return {};
612
615
617 "Invalid kind!");
620}
621
623 switch (Kind) {
624 default:
627 return 0;
630 return 1;
633 return 2;
647 return 4;
650 return 8;
651 }
652}
653
654constexpr char GotSymName[] = "_GLOBAL_OFFSET_TABLE_";
655
656
657
658std::optional X86AsmBackend::evaluateFixup(const MCFragment &,
661 if (Fixup.isPCRel()) {
662 switch (Fixup.getKind()) {
664 Target.setConstant(Target.getConstant() - 1);
665 break;
667 Target.setConstant(Target.getConstant() - 2);
668 break;
669 default: {
670 Target.setConstant(Target.getConstant() - 4);
672
673
674
678 } break;
679 }
680 }
681
682 return {};
683}
684
685void X86AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
686 const MCValue &Target, uint8_t *Data,
687 uint64_t Value, bool IsResolved) {
688
689
690 if (Target.getSpecifier())
691 IsResolved = false;
692 maybeAddReloc(F, Fixup, Target, Value, IsResolved);
693
696 return;
698
699 assert(Fixup.getOffset() + Size <= F.getSize() && "Invalid fixup offset!");
700
701 int64_t SignedValue = static_cast<int64_t>(Value);
702 if (IsResolved && Fixup.isPCRel()) {
703
706 "value of " + Twine(SignedValue) +
707 " is too large for field of " + Twine(Size) +
708 ((Size == 1) ? " byte." : " bytes."));
709 } else {
710
711
712
713
715 "Value does not fit in the Fixup field");
716 }
717
718 for (unsigned i = 0; i != Size; ++i)
719 Data[i] = uint8_t(Value >> (i * 8));
720}
721
722bool X86AsmBackend::mayNeedRelaxation(unsigned Opcode,
724 const MCSubtargetInfo &STI) const {
725 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
728 Operands[Operands.size() - 1 - SkipOperands].isExpr());
729}
730
731bool X86AsmBackend::fixupNeedsRelaxationAdvanced(const MCFragment &,
732 const MCFixup &Fixup,
733 const MCValue &Target,
735 bool Resolved) const {
736
737
738
739
740 if (Resolved)
742
743
746 return false;
747 return true;
748}
749
750
751
752void X86AsmBackend::relaxInstruction(MCInst &Inst,
753 const MCSubtargetInfo &STI) const {
754
755 bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
759}
760
761bool X86AsmBackend::padInstructionViaPrefix(MCFragment &RF,
763 unsigned &RemainingSize) const {
765 return false;
766
767
768
769
772 return false;
773
774 const unsigned OldSize = RF.getVarSize();
775 if (OldSize == 15)
776 return false;
777
778 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
779 const unsigned RemainingPrefixSize = [&]() -> unsigned {
780 SmallString<15> Code;
782 assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
783
784
785
786
787
788
789 unsigned ExistingPrefixSize = Code.size();
790 if (TargetPrefixMax <= ExistingPrefixSize)
791 return 0;
792 return TargetPrefixMax - ExistingPrefixSize;
793 }();
794 const unsigned PrefixBytesToAdd =
795 std::min(MaxPossiblePad, RemainingPrefixSize);
796 if (PrefixBytesToAdd == 0)
797 return false;
798
799 const uint8_t Prefix = determinePaddingPrefix(RF.getInst());
800
801 SmallString<256> Code;
802 Code.append(PrefixBytesToAdd, Prefix);
805
806
808 F.setOffset(PrefixBytesToAdd + F.getOffset());
809
810 RemainingSize -= PrefixBytesToAdd;
811 return true;
812}
813
814bool X86AsmBackend::padInstructionViaRelaxation(MCFragment &RF,
816 unsigned &RemainingSize) const {
819
820
821 return false;
822
825
827 SmallString<15> Code;
830 const unsigned NewSize = Code.size();
831 assert(NewSize >= OldSize && "size decrease during relaxation?");
832 unsigned Delta = NewSize - OldSize;
833 if (Delta > RemainingSize)
834 return false;
838 RemainingSize -= Delta;
839 return true;
840}
841
842bool X86AsmBackend::padInstructionEncoding(MCFragment &RF,
844 unsigned &RemainingSize) const {
846 if (RemainingSize != 0)
847 Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
848 if (RemainingSize != 0)
849 Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
851}
852
853bool X86AsmBackend::finishLayout() const {
854
855
856
857
858
859
860 if (!X86PadForAlign && !X86PadForBranchAlign)
861 return false;
862
863
864
865
866 DenseSet<MCFragment *> LabeledFragments;
867 for (const MCSymbol &S : Asm->symbols())
868 LabeledFragments.insert(S.getFragment());
869
871 for (MCSection &Sec : *Asm) {
872 if (!Sec.isText())
873 continue;
874
876 for (MCSection::iterator I = Sec.begin(), IE = Sec.end(); I != IE; ++I) {
878
879 if (LabeledFragments.count(&F))
880 Relaxable.clear();
881
883 continue;
884
888 continue;
889 }
890
891 auto canHandle = [](MCFragment &F) -> bool {
892 switch (F.getKind()) {
893 default:
894 return false;
896 return X86PadForAlign;
898 return X86PadForBranchAlign;
899 }
900 };
901
902 if (!canHandle(F)) {
903 Relaxable.clear();
904 continue;
905 }
906
907
908
909
910
911 unsigned RemainingSize = Asm->computeFragmentSize(F) - F.getFixedSize();
912 while (!Relaxable.empty() && RemainingSize != 0) {
914
915
916
917 Changed |= padInstructionEncoding(RF, Asm->getEmitter(), RemainingSize);
918
919
920
921
922
923
924
927 break;
928 }
929 Relaxable.clear();
930
931
932
933
937 const MCFragment *LastFragment = BF->getLastFragment();
938 if (!LastFragment)
939 continue;
940 while (&*I != LastFragment)
941 ++I;
942 }
943 }
944 }
945
947}
948
949unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {
951 return 4;
953 return 1;
954 if (STI.hasFeature(X86::TuningFast7ByteNOP))
955 return 7;
956 if (STI.hasFeature(X86::TuningFast15ByteNOP))
957 return 15;
958 if (STI.hasFeature(X86::TuningFast11ByteNOP))
959 return 11;
960
961
962
963 return 10;
964}
965
966
967
968
969bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
970 const MCSubtargetInfo *STI) const {
971 static const char Nops32Bit[10][11] = {
972
973 "\x90",
974
975 "\x66\x90",
976
977 "\x0f\x1f\x00",
978
979 "\x0f\x1f\x40\x00",
980
981 "\x0f\x1f\x44\x00\x00",
982
983 "\x66\x0f\x1f\x44\x00\x00",
984
985 "\x0f\x1f\x80\x00\x00\x00\x00",
986
987 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
988
989 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
990
991 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
992 };
993
994
995 static const char Nops16Bit[4][11] = {
996
997 "\x90",
998
999 "\x66\x90",
1000
1001 "\x8d\x74\x00",
1002
1003 "\x8d\xb4\x00\x00",
1004 };
1005
1006 const char(*Nops)[11] =
1007 STI->hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1008
1009 uint64_t MaxNopLength = (uint64_t)getMaximumNopSize(*STI);
1010
1011
1012
1013 do {
1014 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1015 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1016 for (uint8_t i = 0; i < Prefixes; i++)
1017 OS << '\x66';
1018 const uint8_t Rest = ThisNopLength - Prefixes;
1019 if (Rest != 0)
1020 OS.write(Nops[Rest - 1], Rest);
1021 Count -= ThisNopLength;
1022 } while (Count != 0);
1023
1024 return true;
1025}
1026
1027
1028
1029namespace {
1030
1031class ELFX86AsmBackend : public X86AsmBackend {
1032public:
1033 uint8_t OSABI;
1034 ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
1035 : X86AsmBackend(T, STI), OSABI(OSABI) {}
1036};
1037
1038class ELFX86_32AsmBackend : public ELFX86AsmBackend {
1039public:
1040 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
1041 const MCSubtargetInfo &STI)
1042 : ELFX86AsmBackend(T, OSABI, STI) {}
1043
1044 std::unique_ptr
1045 createObjectTargetWriter() const override {
1047 }
1048};
1049
1050class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
1051public:
1052 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
1053 const MCSubtargetInfo &STI)
1054 : ELFX86AsmBackend(T, OSABI, STI) {}
1055
1056 std::unique_ptr
1057 createObjectTargetWriter() const override {
1060 }
1061};
1062
1063class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
1064public:
1065 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
1066 const MCSubtargetInfo &STI)
1067 : ELFX86AsmBackend(T, OSABI, STI) {}
1068
1069 std::unique_ptr
1070 createObjectTargetWriter() const override {
1073 }
1074};
1075
1076class ELFX86_64AsmBackend : public ELFX86AsmBackend {
1077public:
1078 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
1079 const MCSubtargetInfo &STI)
1080 : ELFX86AsmBackend(T, OSABI, STI) {}
1081
1082 std::unique_ptr
1083 createObjectTargetWriter() const override {
1085 }
1086};
1087
1088class WindowsX86AsmBackend : public X86AsmBackend {
1089 bool Is64Bit;
1090
1091public:
1092 WindowsX86AsmBackend(const Target &T, bool is64Bit,
1093 const MCSubtargetInfo &STI)
1094 : X86AsmBackend(T, STI)
1096 }
1097
1098 std::optional getFixupKind(StringRef Name) const override {
1099 return StringSwitch<std::optional>(Name)
1104 }
1105
1106 std::unique_ptr
1107 createObjectTargetWriter() const override {
1109 }
1110};
1111
1112namespace CU {
1113
1114
1115 enum CompactUnwindEncodings {
1116
1117
1118 UNWIND_MODE_BP_FRAME = 0x01000000,
1119
1120
1121 UNWIND_MODE_STACK_IMMD = 0x02000000,
1122
1123
1124 UNWIND_MODE_STACK_IND = 0x03000000,
1125
1126
1127 UNWIND_MODE_DWARF = 0x04000000,
1128
1129
1130 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1131
1132
1133 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1134 };
1135
1136}
1137
1138class DarwinX86AsmBackend : public X86AsmBackend {
1139 const MCRegisterInfo &MRI;
1140
1141
1142 enum { CU_NUM_SAVED_REGS = 6 };
1143
1144 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1145 Triple TT;
1146 bool Is64Bit;
1147
1148 unsigned OffsetSize;
1149 unsigned MoveInstrSize;
1150 unsigned StackDivide;
1151protected:
1152
1153 unsigned PushInstrSize(MCRegister Reg) const {
1155 case X86::EBX:
1156 case X86::ECX:
1157 case X86::EDX:
1158 case X86::EDI:
1159 case X86::ESI:
1160 case X86::EBP:
1161 case X86::RBX:
1162 case X86::RBP:
1163 return 1;
1164 case X86::R12:
1165 case X86::R13:
1166 case X86::R14:
1167 case X86::R15:
1168 return 2;
1169 }
1170 return 1;
1171 }
1172
1173private:
1174
1175
1176 int getCompactUnwindRegNum(unsigned Reg) const {
1177 static const MCPhysReg CU32BitRegs[7] = {
1178 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1179 };
1180 static const MCPhysReg CU64BitRegs[] = {
1181 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1182 };
1183 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1184 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
1185 if (*CURegs == Reg)
1186 return Idx;
1187
1188 return -1;
1189 }
1190
1191
1192
1193 uint32_t encodeCompactUnwindRegistersWithFrame() const {
1194
1195
1196
1197 uint32_t RegEnc = 0;
1198 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1199 unsigned Reg = SavedRegs[i];
1200 if (Reg == 0) break;
1201
1202 int CURegNum = getCompactUnwindRegNum(Reg);
1203 if (CURegNum == -1) return ~0U;
1204
1205
1206
1207 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
1208 }
1209
1210 assert((RegEnc & 0x3FFFF) == RegEnc &&
1211 "Invalid compact register encoding!");
1212 return RegEnc;
1213 }
1214
1215
1216
1217
1218 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232 for (unsigned i = 0; i < RegCount; ++i) {
1233 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1234 if (CUReg == -1) return ~0U;
1235 SavedRegs[i] = CUReg;
1236 }
1237
1238
1239 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1240
1241 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1242 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1243 unsigned Countless = 0;
1244 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
1245 if (SavedRegs[j] < SavedRegs[i])
1246 ++Countless;
1247
1248 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1249 }
1250
1251
1252 uint32_t permutationEncoding = 0;
1253 switch (RegCount) {
1254 case 6:
1255 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1256 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1257 + RenumRegs[4];
1258 break;
1259 case 5:
1260 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1261 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1262 + RenumRegs[5];
1263 break;
1264 case 4:
1265 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1266 + 3 * RenumRegs[4] + RenumRegs[5];
1267 break;
1268 case 3:
1269 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1270 + RenumRegs[5];
1271 break;
1272 case 2:
1273 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1274 break;
1275 case 1:
1276 permutationEncoding |= RenumRegs[5];
1277 break;
1278 }
1279
1280 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1281 "Invalid compact register encoding!");
1282 return permutationEncoding;
1283 }
1284
1285public:
1286 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
1287 const MCSubtargetInfo &STI)
1288 : X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()),
1289 Is64Bit(TT.isX86_64()) {
1290 memset(SavedRegs, 0, sizeof(SavedRegs));
1291 OffsetSize = Is64Bit ? 8 : 4;
1292 MoveInstrSize = Is64Bit ? 3 : 2;
1293 StackDivide = Is64Bit ? 8 : 4;
1294 }
1295
1296 std::unique_ptr
1297 createObjectTargetWriter() const override {
1301 }
1302
1303
1304
1305 uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
1306 const MCContext *Ctxt) const override {
1308 if (Instrs.empty()) return 0;
1309 if (!isDarwinCanonicalPersonality(FI->Personality) &&
1311 return CU::UNWIND_MODE_DWARF;
1312
1313
1314 unsigned SavedRegIdx = 0;
1315 memset(SavedRegs, 0, sizeof(SavedRegs));
1316
1317 bool HasFP = false;
1318
1319
1320 uint64_t CompactUnwindEncoding = 0;
1321
1322 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1323 unsigned InstrOffset = 0;
1324 unsigned StackAdjust = 0;
1325 uint64_t StackSize = 0;
1326 int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
1327
1328 for (const MCCFIInstruction &Inst : Instrs) {
1329 switch (Inst.getOperation()) {
1330 default:
1331
1332
1333 return CU::UNWIND_MODE_DWARF;
1335
1336
1337
1338
1339
1340
1342
1343
1344
1345 if (*MRI.getLLVMRegNum(Inst.getRegister(), true) !=
1346 (Is64Bit ? X86::RBP : X86::EBP))
1347 return CU::UNWIND_MODE_DWARF;
1348
1349
1350 memset(SavedRegs, 0, sizeof(SavedRegs));
1351 StackAdjust = 0;
1352 SavedRegIdx = 0;
1353 MinAbsOffset = std::numeric_limits<int64_t>::max();
1354 InstrOffset += MoveInstrSize;
1355 break;
1356 }
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372 StackSize = Inst.getOffset() / StackDivide;
1373 break;
1374 }
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1389
1390
1391 return CU::UNWIND_MODE_DWARF;
1392
1393 MCRegister Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1394 SavedRegs[SavedRegIdx++] = Reg.id();
1395 StackAdjust += OffsetSize;
1396 MinAbsOffset = std::min(MinAbsOffset, std::abs(Inst.getOffset()));
1397 InstrOffset += PushInstrSize(Reg);
1398 break;
1399 }
1400 }
1401 }
1402
1403 StackAdjust /= StackDivide;
1404
1405 if (HasFP) {
1406 if ((StackAdjust & 0xFF) != StackAdjust)
1407
1408 return CU::UNWIND_MODE_DWARF;
1409
1410
1411
1412 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (int)OffsetSize)
1413 return CU::UNWIND_MODE_DWARF;
1414
1415
1416 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1417 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1418
1419 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1420 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1421 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1422 } else {
1423 SubtractInstrIdx += InstrOffset;
1424 ++StackAdjust;
1425
1426 if ((StackSize & 0xFF) == StackSize) {
1427
1428 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1429
1430
1431 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1432 } else {
1433 if ((StackAdjust & 0x7) != StackAdjust)
1434
1435 return CU::UNWIND_MODE_DWARF;
1436
1437
1438 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1439
1440
1441
1442 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1443
1444
1445 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1446 }
1447
1448
1449 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1450 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1451
1452
1453
1454 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1455 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
1456
1457
1458 CompactUnwindEncoding |=
1459 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1460 }
1461
1462 return CompactUnwindEncoding;
1463 }
1464};
1465
1466}
1467
1474 return new DarwinX86AsmBackend(T, MRI, STI);
1475
1477 return new WindowsX86AsmBackend(T, false, STI);
1478
1480
1482 return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
1483
1484 return new ELFX86_32AsmBackend(T, OSABI, STI);
1485}
1486
1493 return new DarwinX86AsmBackend(T, MRI, STI);
1494
1496 return new WindowsX86AsmBackend(T, true, STI);
1497
1498 if (TheTriple.isUEFI()) {
1500 "Only COFF format is supported in UEFI environment.");
1501 return new WindowsX86AsmBackend(T, true, STI);
1502 }
1503
1505
1506 if (TheTriple.isX32())
1507 return new ELFX86_X32AsmBackend(T, OSABI, STI);
1508 return new ELFX86_64AsmBackend(T, OSABI, STI);
1509}
1510
1511namespace {
1513public:
1514 X86ELFStreamer(MCContext &Context, std::unique_ptr TAB,
1515 std::unique_ptr OW,
1516 std::unique_ptr Emitter)
1519
1520 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1521};
1522}
1523
1524void X86ELFStreamer::emitInstruction(const MCInst &Inst,
1525 const MCSubtargetInfo &STI) {
1527}
1528
1530 std::unique_ptr &&MAB,
1531 std::unique_ptr &&MOW,
1532 std::unique_ptr &&MCE) {
1533 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
1534 std::move(MCE));
1535}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
#define LLVM_LIKELY(EXPR)
dxil DXContainer Global Emitter
static unsigned getRelaxedOpcode(unsigned Opcode)
PowerPC TLS Dynamic Call Fixup
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
Definition X86AsmBackend.cpp:211
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
Definition X86AsmBackend.cpp:244
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
Definition X86AsmBackend.cpp:250
static bool mayHaveInterruptDelaySlot(unsigned InstOpcode)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
Definition X86AsmBackend.cpp:372
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
Definition X86AsmBackend.cpp:269
constexpr char GotSymName[]
Definition X86AsmBackend.cpp:654
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
Definition X86AsmBackend.cpp:229
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
Definition X86AsmBackend.cpp:223
static unsigned getFixupKindSize(unsigned Kind)
Definition X86AsmBackend.cpp:622
static bool isRelaxableBranch(unsigned Opcode)
Definition X86AsmBackend.cpp:207
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
Definition X86AsmBackend.cpp:264
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
Definition X86AsmBackend.cpp:357
static bool is64Bit(const char *name)
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
Generic interface to target specific assembler backends.
virtual MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
Context object for machine code objects.
LLVM_ABI bool emitCompactUnwindNonCanonical() const
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
bool getAllowAutoPadding() const
void setAllowAutoPadding(bool V)
unsigned getOpcode() const
MCSection * getParent() const
LLVM_ABI void setVarFixups(ArrayRef< MCFixup > Fixups)
MCFragment * getNext() const
ArrayRef< MCOperand > getOperands() const
size_t getVarSize() const
LLVM_ABI void setVarContents(ArrayRef< char > Contents)
MutableArrayRef< char > getVarContents()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
MutableArrayRef< MCFixup > getVarFixups()
void setInst(const MCInst &Inst)
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
FT * newSpecialFragment(Args &&...args)
MCAssembler & getAssembler()
MCRegister getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
Streaming machine code generation interface.
MCFragment * getCurrentFragment() const
size_t getCurFragSize() const
bool getAllowAutoPadding() const
MCSection * getCurrentSectionOnly() const
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
constexpr unsigned id() const
void push_back(const T &Elt)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX86_64() const
Tests whether the target is x86 (64-bit).
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
raw_ostream & write(unsigned char C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
LLVM_ABI Expected< uint32_t > getCPUSubType(const Triple &T)
LLVM_ABI Expected< uint32_t > getCPUType(const Triple &T)
VE::Fixups getFixupKind(uint8_t S)
bool isPrefix(uint64_t TSFlags)
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
void emitInstruction(MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)
Definition X86AsmBackend.cpp:452
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(MCRegister Reg)
Given a segment register, return the encoding of the segment override prefix for it.
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_riprel_4byte_movq_load_rex2
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_evex
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
@ reloc_riprel_4byte_relax_rex2
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
Apply fixup expression for edge to block content.
bool isRelocation(MCFixupKind FixupKind)
NodeAddr< CodeNode * > Code
Context & getContext() const
BaseReg
Stack frame base register. Bit 0 of FREInfo.Info.
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition X86AsmBackend.cpp:1487
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
uint16_t MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
Definition X86AsmBackend.cpp:1529
FunctionAddr VTableAddr Count
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
FunctionAddr VTableAddr uintptr_t uintptr_t Data
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
ArrayRef(const T &OneElt) -> ArrayRef< T >
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
constexpr bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition X86AsmBackend.cpp:1468
Implement std::hash so that hash_code can be used in STL containers.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions