Network on chip Research Papers (original) (raw)

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  • Arbitration, Power Management, Power Consumption, First-Order Logic

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs,... more

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliabil-ity ...

• • by André Baca Mejia
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  • Computer Science, Routing, Routing algorithm, Network on Chips
• • by Juha Plosila
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  • Energy Consumption, Parallel Processing, Chip, Network on chip
• • by Haytham Ahmed
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  • Topology, Optimization, Analysis, Chip
• • by Jos Huisken and +1
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  • Levels of Abstraction, Network on chip
• • by Serge Weber
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  • Mesh generation, Routing algorithm, Fault Tolerance, Adaptive Routing
• • by Alex Chow
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  • Power Electronics, VLSI, VERY LARGE SCALE INTEGRATED CIRCUITS, Very Large Scale Integration

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called 'N-byte RCC (Repetition of Computation and Combination)''. This algorithm is the iterative process of message computation by the 'slicing-by-4'... more

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called 'N-byte RCC (Repetition of Computation and Combination)''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the 'zero block lookup tables'. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

• • by Taekyu Kim
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  • High Speed, Parallel Algorithm, Network on chip, Parallel Architecture
• • by Timo Knuutila
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  • Performance Improvement, Community Structure, Network on chip
• • by parashuram B S
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  • Computer Science, Reinforcement Learning, Routing, Routing algorithm
• • by Luca Benini
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  • Computer Aided Design, Topology, Computer Hardware, Comparative Study
• • by Abdelkrim Zitouni
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  • Computer Architecture, Routing, Routing algorithm, Flow Control
• • by Victor Goulart
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  • Network coding, Network on chip
• • by Isaac Liu
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  • Computer Architecture, Cyber Physical Systems, Hardware, Microarchitecture
• • by Simon Moore
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  • Program Analysis, Communication System, Data Sharing, High performance

In this paper, we address the problem of high-level ex- ploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to pro- pose a methodology supported by a design... more

In this paper, we address the problem of high-level ex- ploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to pro- pose a methodology supported by a design framework (namely, PI- RATE ) to generate and to simulate a configurable NoC-IP core for the power/performance exploration of the on-chip interconnection network. The NoC-IP core is composed of a set of parameterized modules, such as interconnection elements and switches, to form different on-chip micro- network topologies. The proposed framework has been applied to explore several network topologies by varying the workload and to analyze a case study designed for cryptographic hardware acceleration in high perfor- mance web server systems.

• • by Cristina Silvano
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  • Case Study, Perforation, Network on chip, Design framework

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second... more

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

• • by Ron Ho
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  • Power Electronics, VLSI, VERY LARGE SCALE INTEGRATED CIRCUITS, Very Large Scale Integration

... EMBEDDED SYSTEMS Mehdi Modarressi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran modarressi@ce.sharif.edu Shaahin Hessabi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran... more

... EMBEDDED SYSTEMS Mehdi Modarressi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran modarressi@ce.sharif.edu Shaahin Hessabi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran hessabi@sharif.edu ...

• • by Maziar Goudarzi
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  • Computer Science, Computer Architecture, Embedded Systems, Energy Consumption
• • by Amira Mrabti
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  • Intellectual Property, Packaging, XML, Packet Switching
• • by Cristina Silvano
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  • Synchronization, Efficiency, Message Passing, NoC
• • by Mahdi Nikdast
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  • Optical Waveguides, Network Routing, Network on chip, Anti Counterfeiting Technologies
• • by Luciano Bononi
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  • Modeling and Simulation, System Design, Network on chip, Parallel Computer
• • by Hana Huang
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  • Marketing, Chemical Engineering, Optical Engineering, Bioinformatics
• • by Cesar augusto Saavedra.R
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  • Computer Architecture, Computational Modeling, Energy Consumption, Soc
• • by Stergios Stergiou
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  • Distributed Computing, Architecture, Computer Software, Case Study
• • by Rabah Attia
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  • Nanophotonics, Optical Waveguides, Silicon Photonics, Si
• • by Raha Tudu
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  • Photonic Integrated Circuits, Routing algorithm, Deadlock Avoidance, Silicon Photonics
• • by Aline Mello
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  • Performance, Distributed System, Computer Network, Standard Deviation
• • by Pasi Liljeberg and +1
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  • Parallel Algorithms, Computational Modeling, Hot Spot, Multicore Processing
• • by Janet Roveda
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  • Computer Science, Vlsi Design, VLSI, Flow Control
• • by Jesus Villanueva
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  • OPERATING SYSTEM, Performance Evaluation, System Simulation, Network on chip
• • by Paolo Mantovani
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  • Silicon on Insulator, Network on chip, Voltage Regulators, Electrical And Electronic Engineering
• • by Leonel Tedesco and +2
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  • Distributed System, Computer Network, Standard Deviation, Quality of Service

Bio-inspired paradigms such as spiking neural networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable network on chip (NoC)-based SNN... more

Bio-inspired paradigms such as spiking neural networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable network on chip (NoC)-based SNN architecture, implemented on Xilinx Virtex II-Pro FPGA hardware. In association with a genetic algorithm-based hardware evolution platform, EMBRACE-FPGA provides a computing platform for intrinsic hardware evolution, which can be used to explore the evolution and adaptive capabilities of hardware SNNs. Results demonstrate the application of the hardware SNN evolution platform to solve the XOR benchmark problem.

• • by Fearghal Morgan
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  • Genetic Algorithm, Network on chip, SPIKING NEURAL NETWORK, Evolvable Hardware
• • by Hải Phan
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  • Microcontrollers, Network on chip, Integrated Circuit Design
• • by Eran Socher
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  • Radio Frequency, Chip, Network on chip, Speed of Light
• • by Dimitrios Soudris
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  • Theory and Practice, Network on chip, Medicine Studies
• • by Slava Kalyuga
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  • Management, Marketing, Engineering, Ecological Engineering
• • by Israel Cidon
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  • Routing, Resource Allocation, Field-Programmable Gate Arrays, Throughput
• • by Igor V Schagaev
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  • FPGA, Working Conditions, System on Chip, Field Programmable Gate Array
• • by luis chavez
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  • Management, Marketing, Engineering, Ecological Engineering

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus... more

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-efficient design scheme that optimizes energy consumption and hardware costs in VFI-based NoC systems. Since on-chip networks take up a substantial portion of system power budget in NoC-based systems, the proposed scheme uses communication-aware VFI partitioning and tile mapping/routing algorithms to minimize the inter-VFI communications. Experimental results show that the proposed design technique can reduce communication energy consumption by 32–51% over existing techniques and total energy consumption by 3–14%.

• • by WooJoong Kim
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  • Routing algorithm, Energy Consumption, Computer Hardware, Low Power Design
• • by Amit Singh
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  • Energy Consumption, Hardware/Software Co-Design, Computer Software, Energy Saving
• • by Juha Plosila
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  • Routing algorithm, New Technology, Computer Network, System on Chip
• • by David Geer
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  • System on Chip, Chip, Network on chip, Network Topology
• • by Bonnie Zare
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  • Management, Marketing, Engineering, Ecological Engineering

Micro/nanostructure photonic devices offer a variety of enabling properties, including low power-consumption, cost-efficient, compact size, and reliability. These distinctive features have been exploited in a wealth of applications... more

Micro/nanostructure photonic devices offer a variety of enabling properties, including low power-consumption, cost-efficient, compact size, and reliability. These distinctive features have been exploited in a wealth of applications ranging from telecommunication and optical interconnect to photonic network on chip. In this paper, we review two main classes of micro/nanostructure photonic devices, to provide the kinds of functions for optical signal processing.

• • by Xiaomeng Sun
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  • Optical Signal Processing, Low Power Consumption, Cost Efficiency, Optical fiber
• • by Ney L V Calazans
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  • Multiplexing, Low Power Electronics, Network on chip, Integrated Circuit Design
• • by Vito Giannini
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  • Analog Circuits, Software Defined Radio, Power Consumption, Network on chip
• • by Ajay Joshi
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  • System on Chip, Communication Channels, Chip, Network on chip