Integrated Circuit Design Research Papers (original) (raw)

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• • by and +1
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  • Power Electronics, Driver, Vertical Cavity Surface Emitting Laser, Power Control
• • by Ahmed Eltawil and +1
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  • Engineering, Computer Science, System on Chip, Reliability
• • by Linda Katehi
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  • High Frequency, Micromachining, Ceramics, Electronic Circuits
• • by mut tha
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  • Logic, Data Analysis, Energy Saving, Activation Energy
• • by Ville Leppänen
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  • Resource Allocation, System on Chip, Data transfer, Integrated Circuit Design

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of... more

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power

• • by Seungyong Choi
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  • Copper, System on Chip, Cost effectiveness, High performance
• • by Mamun Bin Ibne Reaz
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  • Analog Circuits, Power Consumption, Integrated Circuit, Dynamic Threshold
• • by Binjie Cheng
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  • Circuit simulation, Fluctuations, Gaussian distribution, Parameter Extraction
• • by xuan ngoc Pham
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  • Computer Vision, Image Processing, Computational Complexity, Stereoscopy
• • by Luca Benini
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  • Computer Aided Design, Topology, Computer Hardware, Comparative Study
• • by Kurt Keutzer
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  • System-level design, High Speed, Network Routing, Delays
• • by Eby Friedman
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  • Distributed Computing, VLSI, Computer Hardware, Very Large Scale Integration
• • by Vytautas Stuikys
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  • Software Engineering, Intellectual Property, Productivity, Design Patterns
• • by Shiban Koul
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  • Materials Science, Microstrip Antennas, Computational Electromagnetics, Micromachining
• • by M. Stan
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  • Engineering, Computer Science, Computer Aided Engineering, Design
• • by Aiman H. El-Maleh
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  • Computational Modeling, Evolutionary Computation, Fuzzy Logic, VLSI
• • by andrew brawley
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  • Quantum Computing, Quantum Information, Silicon on Insulator, Quantum Computer
• • by shyamasundar R.K.
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  • Computer Science, Semantics, VLSI, Synchronization
• • by David Nguyen
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  • Design, Linear Programming, Local Search, Power Consumption
• • by Cristina Silvano
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  • Digital System Design, System on Chip, Design Space Exploration, Full Text Search
• • by Jaime Ramirez-angulo and +1
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  • Vlsi Design, Analog Circuits, Digital Circuits, Ambient Intelligence
• • by amit sinha
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  • Program Evaluation, Algorithms, Energy Consumption, Leakage Current

As SoC complexity grows new methodologies and tools for system design and time-effective ditsign space exploration are required. In this paper we introduce a tool called CASSE, what stands for Camellia system-on-chip simulation... more

As SoC complexity grows new methodologies and tools for system design and time-effective ditsign space exploration are required. In this paper we introduce a tool called CASSE, what stands for Camellia system-on-chip simulation environment. CASSE is a fast, flexible, and modular SystemC-based simulation environment which aims to be useful for design-space exploration and system-level design at different abstraction levels. The tool uses transaction-level modeling techniques for fast simulations and easy architectural modeling, and bridge the gap to system implementation by a progressive refinement approach. CASSE is being used in the European 1ST-2001-34410 CAMELLIA project, which focuses on the mapping of innovative smart imaging applications onto an existing video encoding architecture.

• • by Tomás Bautista and +1
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  • System Design, System on Chip, Design Space Exploration, System-level design
• • by Eli Lyons
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  • Vlsi Design, Education, Product Design, VLSI
• • by Ney L V Calazans
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  • Topology, Low Power Electronics, Capacitance, Network Topology

Wireless biosensor applications require RF electronics to operate in immediate proximity of the body. This work investigates the effect of human body on RF circuits by simulations and measurements. Design methodology and initial design... more

Wireless biosensor applications require RF electronics to operate in immediate proximity of the body. This work investigates the effect of human body on RF circuits by simulations and measurements. Design methodology and initial design guidelines for body-worn discrete RF electronics are presented. The test structures are manufactured using printed electronics technology well suited for thin, flexible body-worn wireless sensor applications. The results indicate that in direct contact the human body significantly affects the performance of an RF circuit and needs to be considered. The research is relevant for modeling-based design of flexible body-worn wireless sensors.

• • by Shahed Alam
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  • Biosensors, Wireless Sensor Networks, Printed Electronics, Sensors
• • by Christoph Grimm
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  • Computer Science, Microelectronics, Signal Processing, Computational Modeling
• • by shouli yan
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  • Circuits and Systems, Simulation, Process Simulation, Feedforward
• • by Juergen Schloeffel
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  • Vlsi Design, Signal Integrity, VLSI, Model Order Reduction
• • by James Warnock
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  • High Frequency, Fixed Point Theory, Power Supply, Cycle Time
• • by Matthias Bucher
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  • High Frequency, Radio Frequency, Scaling, Circuit Design
• • by Duane S Boning
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  • Process Integration, Chip, Process Development, Chemical Mechanical Polishing
• • by mozhgan nouri
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  • Physics, Radio Frequency, Circuit Design, Front end
• • by Thomas Demeester
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  • Frequency-domain analysis, Time Domain, Simulation Software, Integrated Circuit Design
• • by M. Stan
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  • Engineering, Computer Science, Vlsi Design, VLSI
• • by Christofer Tautermann
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  • Data Compression, System on Chip, Encoding, Chip
• • by Ujjwal Singh
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  • High Frequency, Electrical And Electronic Engineering, Integrated Circuit Design

A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and... more

A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.

• • by Ratnadip Dey
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  • Delays, Switches, Integrated Circuit Design
• • by M siva subramanian
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  • Analog Circuits, Digital Circuits, Model validation, Design process
• • by Dimitrios Soudris
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  • Hardware Description Languages, Vhdl, Segmentation, Reliability

Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any... more

Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any functional influence. How to make all the test logics work harmoniously and obtain high fault coverage with low area and performance overhead are the two main issues of DFT. Based on the design of a general-purposed CPU chip, this paper introduces some advanced topics to conquer the problems, including technologies of memory built-in-self-test (BIST), internal scan design, logic BIST, IEEE Std. 1149.1 (JTAG)-compatible boundary scan design and the correlations among them. These technologies offer a convenient and reliable DFT scheme for digital circuit designs, especially for large-scale ones, like a general-purpose CPU chip.

• • by Xiutao Yang
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  • Digital Circuits, Asic, Chip, Design for Testability

Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of... more

Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.

• • by Mohammad Hossein Maghami
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  • English Literature, Globalization, Mathematics Education, Iterative Methods
• • by Sani Nassif
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  • Forecasting, Process Design, Political processes modeling and forecasting, Process Variation
• • by Apirak Suadet
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  • Impedance, Harmonic distortion, Logic Gates, Logic Gate
• • by Hanfeng Wang
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  • Consumer Electronics, Cost effectiveness, Fluctuations, Impedance

The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a... more

The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combinational logic and the single event latchup (SEL). The dual modular redundancy (DMR) and a SEL power-switch (SPS) are the basis for a modified ASIC design flow. Measurement results have proven the correct functionality of DMR and SPS circuits, as well as a high fault tolerance of implemented ASICs along with moderate overhead in respect of power consumption and occupied silicon area.

• • by Marko Ilic
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  • Fault Tolerance, Power Consumption, Design Methodology, Redundancy
• • by Raikos George and +1
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  • Analog Circuit Design, Low Power Electronics, Positive Feedback, Integrated Circuit Design
• • by Kevin Zhang
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  • Power Management, Low Power, Low Power Electronics, Circuit Design
• • by Raha Tudu
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  • Photonic Integrated Circuits, Routing algorithm, Deadlock Avoidance, Silicon Photonics
• • by Aline Mello
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  • Performance, Distributed System, Computer Network, Standard Deviation