DPL-based novel CMOS 1-Trit Ternary Full-Adder (original) (raw)
Related papers
An Analysis in to CMOS 1-Trit Ternary Full-Adder Technology
Grenze International Journal of Engineering and Technology GIJET
An Ultra-Low Power Ternary Multi-Digit Adder Applies GDI Method for Binary Operations
Journal of Electrical and Computer Engineering Innovations
2023
Design and characterization of a low power ternary DSP
2003
AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND GDI TECHNIQUE
DPL-based novel Binary-to-ternary converter on CMOS technology
AEU - International Journal of Electronics and Communications, 2018
Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
IEEE Access, 2021
Novel 1-Bit Full-Adder Cell with ultra-low Delay, PDP and EDP
AREA AND POWER EFFICIENT CMOS ADDER DESIGN BY HYBRIDIZING PTL AND TECHNIQUE
High-Efficient circuits for ternary addition
Low Power-Area GDI & PTL Techniques Based Full Adder Designs
Computer Science & Information Technology ( CS & IT ), 2013
Design of Full Adder Using Subthreshold DTPT Logic
Advances in systems science and applications, 2016
Simulative & Comparative Study of Cmos Techniques Using Full Adder 1 Shikha Singhal
SIMULATIVE & COMPARATIVE STUDY OF CMOS TECHNIQUES USING FULL ADDER
An ultra-low-power CNFET based dual V ternary dynamic Half Adder
Microelectronics Journal, 2021
Low Power-High Speed 11T Full Adder DSM Design
International Journal of Computer Applications, 2014
Design and Analysis of an Efficient Full Adder Using Systematic Cell Design Methodology
ICTACT Journal on Microelectronics, 2017
Design of Low Power Low Voltage Circuit using CMOS Ternary Logic
LOW POWER BASED TERNARY HALF ADDER USING FIN TYPE FIELD EFFECT TRANSISTOR TECHNOLOGY
IRJET, 2022
Two new topologies for low-power Half-Adder in 180nm CMOS technology
World Applied Sciences Journal
International Journal of Engineering Research and Technology (IJERT), 2014
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder
Low-Power and High – Performance Design Techniques for CMOS 4-bit ALU by using CPL , DPL , DVL
2017
IEICE Electronics Express, 2014
A High-Performance Full Adder Design with Low Area, Power and Delay
International Journal of Scientific Research in Science and Technology IJSRST
International Journal of Scientific Research in Science and Technology, 2022
Novel direct designs for 3-input XOR function for low-power and high-speed applications
International Journal of Electronics, 2010
Synthesis of high performance low power PTL circuits
… of the 2003 Asia and South …, 2003
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
A new 6-T multiplexer based full-adder for low power and leakage current optimization
IEICE Electronics Express, 2012
Low‐power consumption ternary full adder based on CNTFET
IET Circuits, Devices & Systems, 2016
Comparative Analysis of Energy Efficient Low Power 1bit Full Addera at 120 nm technology
IJAET July-2012 ISSN, 1963
Physical Design Implementation of Ternary Arithmetic Circuits
International Journal for Research in Applied Science and Engineering Technology, 2017
Fast and Energy-Efficient CNFET Adders With CDM and Sensitivity-Based Device-Circuit Co-Optimization
Mona Hashemi, Kawsar Haghshenas
2018
A Review of 1-Bit Full Adder Design Using Different Dynamic CMOS Techniques
2021