LLVM: lib/Target/ARM/ARMLoadStoreOptimizer.cpp File Reference (original) (raw)

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Macros
#define DEBUG_TYPE "arm-ldst-opt"
#define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
#define ARM_PREALLOC_LOAD_STORE_OPT_NAME "ARM pre- register allocation load / store optimization pass"
Functions
STATISTIC (NumLDMGened, "Number of ldm instructions generated")
STATISTIC (NumSTMGened, "Number of stm instructions generated")
STATISTIC (NumVLDMGened, "Number of vldm instructions generated")
STATISTIC (NumVSTMGened, "Number of vstm instructions generated")
STATISTIC (NumLdStMoved, "Number of load / store instructions moved")
STATISTIC (NumLDRDFormed,"Number of ldrd created before allocation")
STATISTIC (NumSTRDFormed,"Number of strd created before allocation")
STATISTIC (NumLDRD2LDM, "Number of ldrd instructions turned back into ldm")
STATISTIC (NumSTRD2STM, "Number of strd instructions turned back into stm")
STATISTIC (NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's")
STATISTIC (NumSTRD2STR, "Number of strd instructions turned back into str's")
INITIALIZE_PASS (ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false, false) static bool definesCPSR(const MachineInstr &MI)
static int getMemoryOpOffset (const MachineInstr &MI)
static const MachineOperand & getLoadStoreBaseOp (const MachineInstr &MI)
static const MachineOperand & getLoadStoreRegOp (const MachineInstr &MI)
static int getLoadStoreMultipleOpcode (unsigned Opcode, ARM_AM::AMSubMode Mode)
static ARM_AM::AMSubMode getLoadStoreMultipleSubMode (unsigned Opcode)
static bool isT1i32Load (unsigned Opc)
static bool isT2i32Load (unsigned Opc)
static bool isi32Load (unsigned Opc)
static bool isT1i32Store (unsigned Opc)
static bool isT2i32Store (unsigned Opc)
static bool isi32Store (unsigned Opc)
static bool isLoadSingle (unsigned Opc)
static unsigned getImmScale (unsigned Opc)
static unsigned getLSMultipleTransferSize (const MachineInstr *MI)
static bool ContainsReg (const ArrayRef< std::pair< unsigned, bool > > &Regs, unsigned Reg)
static bool isValidLSDoubleOffset (int Offset)
static bool mayCombineMisaligned (const TargetSubtargetInfo &STI, const MachineInstr &MI)
Return true for loads/stores that can be combined to a double/multi operation without increasing the requirements for alignment.
static unsigned getUpdatingLSMultipleOpcode (unsigned Opc, ARM_AM::AMSubMode Mode)
static int isIncrementOrDecrement (const MachineInstr &MI, Register Reg, ARMCC::CondCodes Pred, Register PredReg)
Check if the given instruction increments or decrements a register and return the amount it is incremented/decremented.
static MachineBasicBlock::iterator findIncDecBefore (MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset)
Searches for an increment or decrement of Reg before MBBI.
static MachineBasicBlock::iterator findIncDecAfter (MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset, const TargetRegisterInfo *TRI)
Searches for a increment or decrement of Reg after MBBI.
static unsigned getPreIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode)
static unsigned getPostIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode)
static bool isMemoryOp (const MachineInstr &MI)
Returns true if instruction is a memory operation that this pass is capable of operating on.
static void InsertLDR_STR (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, MachineInstr *MI)
INITIALIZE_PASS_BEGIN (ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt
arm prera ldst static false cl::opt< unsigned > InstReorderLimit ("arm-prera-ldst-opt-reorder-limit", cl::init(8), cl::Hidden)
static bool IsSafeAndProfitableToMove (bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSetImpl< MachineInstr * > &MemOps, SmallSet< unsigned, 4 > &MemRegs, const TargetRegisterInfo *TRI, AliasAnalysis *AA)
static void forEachDbgRegOperand (MachineInstr *MI, std::function< void(MachineOperand &)> Fn)
static void updateRegisterMapForDbgValueListAfterMove (SmallDenseMap< Register, SmallVector< MachineInstr * >, 8 > &RegisterMap, MachineInstr *DbgValueListInstr, MachineInstr *InstrToReplace)
static DebugVariable createDebugVariableFromMachineInstr (MachineInstr *MI)
static int getBaseOperandIndex (MachineInstr &MI)
static bool isPostIndex (MachineInstr &MI)
static bool isPreIndex (MachineInstr &MI)
static bool isLegalOrConvertableAddressImm (unsigned Opcode, int Imm, const TargetInstrInfo *TII, int &CodesizeEstimate)
static void AdjustBaseAndOffset (MachineInstr *MI, Register NewBaseReg, int Offset, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
static MachineInstr * createPostIncLoadStore (MachineInstr *MI, int Offset, Register NewReg, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Variables
static cl::opt< bool > AssumeMisalignedLoadStores ("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt"))
This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled.
arm prera ldst opt
arm prera ldst ARM_PREALLOC_LOAD_STORE_OPT_NAME
arm prera ldst false

◆ ARM_LOAD_STORE_OPT_NAME

◆ ARM_PREALLOC_LOAD_STORE_OPT_NAME

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-ldst-opt"

◆ AdjustBaseAndOffset()

Definition at line 3010 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), getBaseOperandIndex(), llvm::MachineFunction::getRegInfo(), llvm::isLegalAddressImm(), llvm_unreachable, MI, MRI, llvm::Offset, TII, and TRI.

◆ ContainsReg()

◆ createDebugVariableFromMachineInstr()

◆ createPostIncLoadStore()

Definition at line 3065 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstrBuilder::add(), llvm::ARM_AM::add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrModeMask, llvm::ARMII::AddrModeT2_i7, llvm::ARMII::AddrModeT2_i7s2, llvm::ARMII::AddrModeT2_i7s4, llvm::ARMII::AddrModeT2_i8, llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::RegState::Define, getPostIndexedLoadStoreOpcode(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, llvm::Offset, llvm::ARM_AM::sub, TII, TRI, and llvm::MCInstrDesc::TSFlags.

◆ findIncDecAfter()

◆ findIncDecBefore()

◆ forEachDbgRegOperand()

◆ getBaseOperandIndex()

◆ getImmScale()

◆ getLoadStoreBaseOp()

◆ getLoadStoreMultipleOpcode()

◆ getLoadStoreMultipleSubMode()

◆ getLoadStoreRegOp()

◆ getLSMultipleTransferSize()

◆ getMemoryOpOffset()

◆ getPostIndexedLoadStoreOpcode()

◆ getPreIndexedLoadStoreOpcode()

◆ getUpdatingLSMultipleOpcode()

◆ INITIALIZE_PASS()

◆ INITIALIZE_PASS_BEGIN()

◆ InsertLDR_STR()

static void InsertLDR_STR ( MachineBasicBlock & MBB, MachineBasicBlock::iterator & MBBI, int Offset, bool isDef, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo * TII, MachineInstr * MI ) static

Definition at line 1731 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::getKillRegState(), llvm::getUndefRegState(), MBB, MBBI, MI, llvm::Offset, and TII.

◆ InstReorderLimit()

arm prera ldst static false cl::opt< unsigned > InstReorderLimit ( "arm-prera-ldst-opt-reorder-limit" , cl::init(8) , cl::Hidden ) static

◆ isi32Load()

◆ isi32Store()

◆ isIncrementOrDecrement()

◆ isLegalOrConvertableAddressImm()

◆ isLoadSingle()

◆ isMemoryOp()

◆ isPostIndex()

◆ isPreIndex()

◆ IsSafeAndProfitableToMove()

Definition at line 2216 of file ARMLoadStoreOptimizer.cpp.

References llvm::sampleprof::Base, llvm::SmallSet< T, N, C >::count(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineOperand::getReg(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::SmallSet< T, N, C >::size(), and TRI.

◆ isT1i32Load()

◆ isT1i32Store()

◆ isT2i32Load()

◆ isT2i32Store()

◆ isValidLSDoubleOffset()

static bool isValidLSDoubleOffset ( int Offset) static

◆ mayCombineMisaligned()

◆ STATISTIC() [1/11]

STATISTIC ( NumLDMGened ,
"Number of ldm instructions generated"
)

◆ STATISTIC() [2/11]

STATISTIC ( NumLDRD2LDM ,
"Number of ldrd instructions turned back into ldm"
)

◆ STATISTIC() [3/11]

STATISTIC ( NumLDRD2LDR ,
"Number of ldrd instructions turned back into ldr's"
)

◆ STATISTIC() [4/11]

STATISTIC ( NumLDRDFormed ,
"Number of ldrd created before allocation"
)

◆ STATISTIC() [5/11]

◆ STATISTIC() [6/11]

STATISTIC ( NumSTMGened ,
"Number of stm instructions generated"
)

◆ STATISTIC() [7/11]

STATISTIC ( NumSTRD2STM ,
"Number of strd instructions turned back into stm"
)

◆ STATISTIC() [8/11]

STATISTIC ( NumSTRD2STR ,
"Number of strd instructions turned back into str's"
)

◆ STATISTIC() [9/11]

STATISTIC ( NumSTRDFormed ,
"Number of strd created before allocation"
)

◆ STATISTIC() [10/11]

STATISTIC ( NumVLDMGened ,
"Number of vldm instructions generated"
)

◆ STATISTIC() [11/11]

STATISTIC ( NumVSTMGened ,
"Number of vstm instructions generated"
)

◆ updateRegisterMapForDbgValueListAfterMove()

◆ ARM_PREALLOC_LOAD_STORE_OPT_NAME

arm prera ldst ARM_PREALLOC_LOAD_STORE_OPT_NAME

◆ AssumeMisalignedLoadStores

cl::opt< bool > AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt")) ( "arm-assume-misaligned-load-store" , cl::Hidden , cl::init(false) , cl::desc("Be more conservative in ARM load/store opt") ) static

This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled.

This can be used to create libraries that are robust even when users provoke undefined behaviour by supplying misaligned pointers.

See also

mayCombineMisaligned()

Referenced by InstReorderLimit().

◆ false

◆ opt