RISCVVLOptimizer.cpp File Reference (original) (raw)

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Macros
#define	DEBUG_TYPE "riscv-vl-optimizer"
#define	PASS_NAME "RISC-V VL Optimizer"
#define	VSEG_CASES(Prefix, EEW)
#define	VSSEG_CASES(EEW)
#define	VSSSEG_CASES(EEW)
#define	VSUXSEG_CASES(EEW)
#define	VSOXSEG_CASES(EEW)

Functions
static raw_ostream &	operator<< (raw_ostream &OS, const OperandInfo &OI)
static raw_ostream &	operator<< (raw_ostream &OS, const std::optional< OperandInfo > &OI)
static std::pair< unsigned, bool >	getEMULEqualsEEWDivSEWTimesLMUL (unsigned Log2EEW, const MachineInstr &MI)
	Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.
static unsigned	getIntegerExtensionOperandEEW (unsigned Factor, const MachineInstr &MI, const MachineOperand &MO)
	Dest has EEW=SEW.
static std::optional< unsigned >	getOperandLog2EEW (const MachineOperand &MO)
static std::optional< OperandInfo >	getOperandInfo (const MachineOperand &MO)
static bool	isTupleInsertInstr (const MachineInstr &MI)
	Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.
static bool	isSupportedInstr (const MachineInstr &MI)
	Return true if this optimization should consider MI for VL reduction.
static bool	isVectorOpUsedAsScalarOp (const MachineOperand &MO)
	Return true if MO is a vector operand but is used as a scalar operand.
static std::optional< DemandedVL >	getMinimumVLForVSLIDEDOWN_VX (const MachineOperand &UserOp, const MachineRegisterInfo *MRI)
	Given a vslidedown.vx like:
static bool	isSegmentedStoreInstr (const MachineInstr &MI)
static bool	isPhysical (const MachineOperand &MO)

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-vl-optimizer"

◆ PASS_NAME

#define PASS_NAME "RISC-V VL Optimizer"

◆ VSEG_CASES

#define VSEG_CASES	(	Prefix,
EEW )

Value:

RISCV::Prefix##SEG2E##EEW##_V: \

case RISCV::Prefix##SEG3E##EEW##_V: \

case RISCV::Prefix##SEG4E##EEW##_V: \

case RISCV::Prefix##SEG5E##EEW##_V: \

case RISCV::Prefix##SEG6E##EEW##_V: \

case RISCV::Prefix##SEG7E##EEW##_V: \

case RISCV::Prefix##SEG8E##EEW##_V

Definition at line 220 of file RISCVVLOptimizer.cpp.

◆ VSOXSEG_CASES

#define VSOXSEG_CASES	(	EEW	)

◆ VSSEG_CASES

#define VSSEG_CASES	(	EEW	)

◆ VSSSEG_CASES

#define VSSSEG_CASES	(	EEW	)

◆ VSUXSEG_CASES

#define VSUXSEG_CASES	(	EEW	)

◆ getEMULEqualsEEWDivSEWTimesLMUL()

◆ getIntegerExtensionOperandEEW()

◆ getMinimumVLForVSLIDEDOWN_VX()

Given a vslidedown.vx like:

slideamt = ADDI x, -1 v = PseudoVSLIDEDOWN_VX passthru, src, slideamt, avl=1

v will only read the first slideamt + 1 lanes of src, which = x. This is a common case when lowering extractelement.

Note that if x is 0, slideamt will be all ones. In this case src will be completely slid down and none of its lanes will be read (since slideamt is greater than the largest VLMAX of 65536) so we can demand any minimum VL.

Definition at line 1407 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::RISCV::getRVVMCOpcode(), llvm::MachineOperand::isImm(), llvm::Register::isVirtual(), MI, and MRI.

◆ getOperandInfo()

◆ getOperandLog2EEW()

Dest EEW encoded in the instruction

Definition at line 233 of file RISCVVLOptimizer.cpp.

References assert(), getIntegerExtensionOperandEEW(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), llvm::RISCVII::getSEWOpNum(), Info, llvm::RISCVII::isFirstDefTiedToFirstUse(), llvm::RISCVII::isTiedPseudo(), llvm_unreachable, MI, llvm::MCOI::OPERAND_REGISTER, llvm::RVV, VSOXSEG_CASES, VSSEG_CASES, VSSSEG_CASES, and VSUXSEG_CASES.

Referenced by getOperandInfo().

◆ isPhysical()

◆ isSegmentedStoreInstr()

◆ isSupportedInstr()

Return true if this optimization should consider MI for VL reduction.

This white-list approach simplifies this optimization for instructions that may have more complex semantics with relation to how it uses VL.

Definition at line 894 of file RISCVVLOptimizer.cpp.

References isTupleInsertInstr(), MI, and llvm::RVV.

◆ isTupleInsertInstr()

Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.

Currently it's lowered to INSERT_SUBREG.

Definition at line 1490 of file RISCVVLOptimizer.cpp.

References assert(), llvm::RISCVVType::decodeVLMUL(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::RISCVRI::isVRegClass(), MI, MRI, llvm::RISCV::RVVBitsPerBlock, TRI, and llvm::TargetRegisterClass::TSFlags.

Referenced by isSupportedInstr().