Jitter Research Papers - Academia.edu (original) (raw)

An OSGi (Open Services Gateway Initiative) home gateway system manages the integration of heterogeneous home networks protocols and devices to develop ubiquitous applications. Wired and wireless heterogeneous home networks have different... more

An OSGi (Open Services Gateway Initiative) home gateway system manages the integration of heterogeneous home networks protocols and devices to develop ubiquitous applications. Wired and wireless heterogeneous home networks have different QoS concerns. For instance, jitter and latency are important concerns in web phones, while packet loss ratio is important in on-line video. This study adopts UPnP QoS specification version 1.0 to design an adaptive QoS management mechanism based on the RMD (Resource Management in DiffServ) architecture. This study monitors real-time network traffic, and adaptively controls the bandwidth, to satisfy the minimum but most important quality for each application in home network congestion. Simulation results indicate that the average jitter, latency and packet loss are reduced by 0.1391 ms, 0.0066 s, and 5.43%, respectively. The packet loss ratio is reduced by 4.53%, and the throughput is increased by 1.2% in high definition video stream; the packet loss ratio is reduced by 1.89% for standard definition video stream, and in VoIP (Voice over IP) the jitter and latency are reduced to 0.0407 ms and 0.0209 s, respectively.

Abstract— This paper presents an adaptive control scheme for suppressing jitter in laser beams. The variable-order adaptive controller is based on an adaptive lattice filter that implicitly identifies the disturbance statistics from... more

Abstract— This paper presents an adaptive control scheme for suppressing jitter in laser beams. The variable-order adaptive controller is based on an adaptive lattice filter that implicitly identifies the disturbance statistics from real-time sensor data. The multi-channel adaptive ...

A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error < 33 mUI. Following initial lock, the DLL operates... more

A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error < 33 mUI. Following initial lock, the DLL operates closed-loop to compensate for V,T drift consuming 6mW @ 1.6GHz. In addition the DLL filters high frequency input jitter and corrects 20% DCD without additional correction.

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test... more

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13µm CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz.

Parkinson's disease is a central nervous-system disorder. 90% of people with parkinson disease are reported to have speech and voice disorders. Vocal folds are normally weakened by this disorder and the patient talks improperly. Various... more

Parkinson's disease is a central nervous-system disorder. 90% of people with parkinson disease are reported to have speech and voice disorders. Vocal folds are normally weakened by this disorder and the patient talks improperly. Various elements of the speech patterns of healthy people and those with parkinson disease were studied for prediction of parkinson's disease. Optimized features affecting the data classification process were then identified using genetic algorithms and the KNN classification method was used to eventually classify the data based on different numbers of optimized features.

Overlay management systems face the challenges of increased complexity and heterogeneity because of the many elements involved in providing overlay services. In dynamic networks, the challenge and complexity is increased. Service... more

Overlay management systems face the challenges of increased complexity and heterogeneity because of the many elements involved in providing overlay services. In dynamic networks, the challenge and complexity is increased. Service composition allows simple services to be dynamically combined into more complex services in order to provide new services. In this paper, we deal with the problem of composing multiple autonomic elements to achieve system wide goals. Using a selforganizing approach, autonomic entities are dynamically and seamlessly composed into service-specific overlay networks. The paper describes and discusses the details of the composition approach. Results of extensive simulation are presented.

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists,... more

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 40% energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations.

A low-jitter (<1 ps) trigger system for pulsewaveform-based calibration and intercomparison of high-speed samplers is described. The system uses a commercially available pulse generator and pulse splitter/delay line.

A robust digital image stabilization algorithm is proposed using a Kalman filter-based global motion prediction and phase correlation-based motion correction. Global motion is basically estimated by adaptively averaging multiple local... more

A robust digital image stabilization algorithm is proposed using a Kalman filter-based global motion prediction and phase correlation-based motion correction. Global motion is basically estimated by adaptively averaging multiple local motions obtained by phase correlation. The distribution of phase correlation determines a local motion vector, and the global motion is obtained by suitably averaging multiple local motions. By accumulating the global motion at each frame, we can obtain the optimal motion vector that can stabilize the corresponding frame. The proposed algorithm is robust to camera vibration or unwanted movement regardless of object's movement. Experimental results show that the proposed digital image stabilization algorithm can efficiently remove camera jitter and provide continuously stabilized video.

Oscillators are key components of electronic systems. Undesired perturbations, i.e. noise, in practical electronic systems adversely affect the spectral and timing properties of oscillators resulting in phase noise, which is a key... more

Oscillators are key components of electronic systems. Undesired perturbations, i.e. noise, in practical electronic systems adversely affect the spectral and timing properties of oscillators resulting in phase noise, which is a key performance limiting factor, being a major contributor to bit-error-rate (BER) of RF communication systems, and creating synchronization problems in clocked and sampled-data systems. In this paper, we first present a theory and numerical methods for nonlinear perturbation and noise analysis of oscillators described by a system of differential-algebraic equations (DAEs), which extends our recent results on perturbation analysis of autonomous ordinary differential equations (ODEs). In developing the above theory, we rely on novel results we establish for linear periodically time-varying (LPTV) systems: Floquet theory for DAEs. We then use this nonlinear perturbation analysis to derive the stochastic characterization, including the resulting oscillator spectrum, of phase noise in oscillators due to colored (e.g., 1= f noise), as opposed to white, noise sources. The case of white noise sources has already been treated by us in a recent publication. The results of the theory developed in this work enabled us to implement a rigorous and effective analysis and design tool in a circuit simulator for low phase noise oscillator design.

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern... more

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase-locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in integrated-circuit design, the book will also be of interest to researchers and graduate students in electrical engineering.

A novel architecture for clock generation in dual-loop subrate clock and data recovery (CDR) circuits is proposed based on an adjustable phase-locked loop (PLL). The adjustable PLL (adjPLL) generates eight equidistant clock phases, whose... more

A novel architecture for clock generation in dual-loop subrate clock and data recovery (CDR) circuits is proposed based on an adjustable phase-locked loop (PLL). The adjustable PLL (adjPLL) generates eight equidistant clock phases, whose timing with respect to a reference clock can be simultaneously shifted in steps of 3 ps, controllable by a digital value. The programmable phase shift is achieved by adding the weighted outputs of several XOR phase detectors. The measured tracking jitter of the PLL, fabricated in 90-nm SOI CMOS, is 0.94 ps rms at 2.5 GHz, and the power consumption is 20 mW at DD = 0 9 V. The circuit occupies an area of only 0.016 mm 2 .

A two-channel multibit CA audio digital-to-analogconverter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no oversampled synchronous clocks to operate and rejects input sample... more

A two-channel multibit CA audio digital-to-analogconverter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no oversampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-ofband noise of -63 dBr with less than 0.1' phase nonlinearity.

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and... more

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.

The purpose of this study was to examine the algorithm-measuring capabilities used in the Time-Frequency Analysis Software Program for 32-bit Windows (TF32) for measuring fundamental frequency (F0), its dependent measures, and... more

The purpose of this study was to examine the algorithm-measuring capabilities used in the Time-Frequency Analysis Software Program for 32-bit Windows (TF32) for measuring fundamental frequency (F0), its dependent measures, and signal-to-noise ratio (SNR). The stability, accuracy, and linearity of its algorithm to systematic changes in aspiration noise and/or spectral slope (to mimic the perceptual characteristics of breathiness, roughness, and hoarseness) were evaluated using its analysis output to five female and five male synthesized voices. TF32 was used to calculate F0, Jitter%, Shimmer%, and SNR for each of the synthesized signals. The findings indicate that although TF32 produced stable results for male synthesized samples, they were not accurate when measuring F0, Jitter%, and Shimmer% with the addition of noise and variations in open quotient independently and in combination. In contrast, TF32 was neither stable nor accurate in making the same measurements for female synthesized samples. However, TF32 was stable and accurate in measuring SNR for male and most of female voices. These results point to an inappropriate F0 extraction algorithm in TF32 and stress the need for further research to remediate the algorithm or to identify a superior one.

This paper addresses the clock recovery problem while transporting MPEG-2 Systems Layer streams over packet-switched networks. The packet delay variation (jitter) introduced by the network a ects the stability and thus the quality of the... more

This paper addresses the clock recovery problem while transporting MPEG-2 Systems Layer streams over packet-switched networks. The packet delay variation (jitter) introduced by the network a ects the stability and thus the quality of the recovered clock. A decoder design methodology is described in which a jitter estimator that performs restamping on all the incoming packets containing clock values is used in conjunction with a standard phase-locked loop (PLL). A simple implementation of this methodology is described, where a new heuristic has been added to the standard PLL to eliminate the e ects of the jitter. The methodology is evaluated by both analysis and extensive simulation experiments in a multi-hop ATM network using constant bit-rate MPEG-2 Transport Streams produced by hardware encoders with varying levels of cross tra c. The results show that the restamping approach outperforms standard dejittering methods, especially under heavy load conditions.

This paper discusses the issue of how to obtain Quality of Service (QoS) for the new applications (Multimedia, VoIP, ...) over IP networks. QoS principles and parameters (Delay, jitter, ...) are discussed together with the architectures,... more

This paper discusses the issue of how to obtain Quality of Service (QoS) for the new applications (Multimedia, VoIP, ...) over IP networks. QoS principles and parameters (Delay, jitter, ...) are discussed together with the architectures, frameworks, protocols and mechanisms being proposed for obtaining a guaranteed application support over the Internet and private IP networks.

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a... more

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-m CMOS CDR consumes 33 mW at 8 Gb/s. Die area including voltage regulator is 0.08 mm 2 . Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

The 1e filter ("one Euro filter") is a simple algorithm to filter noisy signals for high precision and responsiveness. It uses a first order low-pass filter with an adaptive cutoff frequency: at low speeds, a low cutoff stabilizes the... more

The 1e filter ("one Euro filter") is a simple algorithm to filter noisy signals for high precision and responsiveness. It uses a first order low-pass filter with an adaptive cutoff frequency: at low speeds, a low cutoff stabilizes the signal by reducing jitter, but as speed increases, the cutoff is increased to reduce lag. The algorithm is easy to implement, uses very few resources, and with two easily understood parameters, it is easy to tune. In a comparison with other filters, the 1e filter has less lag using a reference amount of jitter reduction.

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and... more

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.

Wireless LAN technologies implemented on controller-based wireless LAN design not to mention their critical evaluation is an issue which causes a great deal of debate. Entering into a new era that the needs of technology optimization grow... more

Wireless LAN technologies implemented on controller-based wireless LAN design not to mention their critical evaluation is an issue which causes a great deal of debate. Entering into a new era that the needs of technology optimization grow rapidly, Enterprise wireless networking is meaningful to be achieved not to mention that it is considered a basic topic to be analyzed. This research is particularly outstanding for the reader because it will analyze the most important standards and protocols of wireless technology, distinctly 802.11 network tailored o business needs. It must be stressed that the wireless LAN controller-based WLAN design, and autonomous AP based wireless LAN design will be compared and contrasted. Furthermore, there will be critically evaluated related technologies including WLAN controller, CAPWAP and DTLS, user authentication - EAP and EAP methods not to mention 802.11n and 802.11ac. All the above, will be adopted and implemented on a medium company with 265 employees. There will also be provided floor plans for the two buildings and two floors that the company owes not to mention a logical diagram where all will be connected wirelessly based on national and international communication standards. Considering the factors related to this topic, the question of what specific consequences arise when addressing this theme must be elaborated.

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high... more

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain. ¡ err . For simplicity, it is assumed that, every time step

The performance of free-space optical (FSO) communication systems is compromised by atmospheric fading and pointing errors. The pointing errors are widely considered as a combination of two components: boresight and jitter. A statistical... more

The performance of free-space optical (FSO) communication systems is compromised by atmospheric fading and pointing errors. The pointing errors are widely considered as a combination of two components: boresight and jitter. A statistical model is investigated for pointing errors with nonzero boresight by taking into account the laser beamwidth, detector aperture size, and jitter variance. A novel closed-form probability density function (PDF) is derived for this new nonzero boresight pointing error model. Furthermore, we obtain closed-form PDF for the composite lognormal turbulence channels and finite series approximate PDF for the composite Gamma-Gamma turbulence channels, which is suitable for terrestrial FSO applications impaired by building sway. We conduct error rate analysis of on-off keying signaling with intensity modulation and direct detection over the lognormal and Gamma-Gamma fading channels. Asymptotic error rate analysis and outage probability of such a system are also presented based on the derived composite PDFs. It is shown that the boresight can only affect the coding gain, while the diversity order is determined by the atmospheric fading effect as well as the pointing error effect.

In this paper, a hard real-time execution environment extension is proposed for an open source real-time operating system, FreeRTOS, in order to support a special case of hard real-time tasks, called ModXs. The goal is to obtain a... more

In this paper, a hard real-time execution environment extension is proposed for an open source real-time operating system, FreeRTOS, in order to support a special case of hard real-time tasks, called ModXs. The goal is to obtain a real-time system which has both the capabilities offered by a dynamic, preemptive, priority based scheduling and execution environment and the determinism and predictability of a hard real time execution environment. This paper also presents an implementation of the system which was tested and validated on a hardware platform EFM32-G8900-STK.

This paper discusses some results for simulation and modeling of charge-pump Delay Locked Loops. A novel model based on a sampled-time approach is presented, and used for jitter analysis. The model is applied to input signal jitter,... more

This paper discusses some results for simulation and modeling of charge-pump Delay Locked Loops. A novel model based on a sampled-time approach is presented, and used for jitter analysis. The model is applied to input signal jitter, internally generated jitter and is further extended to handle jitter effects related with the control charge-pump. Behavior models for simulation purposes are derived from the theoretical model, and design considerations based on these are presented. a

Objective: The aim of this study was to identify the effects of objective laryngopharyngeal reflux (LPR) on the acoustic parameters of patients by comparing their voice samples with that of control subjects. Study Design: Prospective... more

Objective: The aim of this study was to identify the effects of objective laryngopharyngeal reflux (LPR) on the acoustic parameters of patients by comparing their voice samples with that of control subjects. Study Design: Prospective study in two tertiary reference hospitals. Methods: 48 consecutive patients with symptoms related to LPR and 64 control subjects were included in the study. Suspected LPR patients underwent a 24-hour ambulatory pH monitoring, and 25 (52%) of them were shown to have objective LPR. Acoustical evaluation results of objective LPR patients were compared with that of symptomatic LPR patients and control subjects. Results: All frequency perturbation values obtained from objective and symptomatic LPR patients were higher than the control subjects (P ! 0.01). Mean fundamental frequency, amplitude perturbation measures, and noise-to-harmonics ratio were not significantly different between groups. Conclusion: LPR patients have significantly different frequency perturbation values than control subjects.

Simulation-based programmable logic controller (PLC) code verification is a part of virtual commissioning, where the control code is verified against a virtual prototype of an application. With today's general OPC interface, it is easy to... more

Simulation-based programmable logic controller (PLC) code verification is a part of virtual commissioning, where the control code is verified against a virtual prototype of an application. With today's general OPC interface, it is easy to connect a PLC to a simulation tool for, e.g., verification purposes. However, there are some problems with this approach that can lead to an unreliable verification result. In this paper, four major problems with the OPC interface are described, and two possible solutions to the problems are presented: a general IEC 61131-3-based software solution, and a new OPC standard solution.

This paper presents an improved design of voltage controlled oscillator (VCO) utilizing the three differential cell CMOS inverters for forming the ring oscillator. The differential cell reduces the power supply fluctuations impact... more

This paper presents an improved design of voltage
controlled oscillator (VCO) utilizing the three differential cell
CMOS inverters for forming the ring oscillator. The differential
cell reduces the power supply fluctuations impact on the
oscillator jitter while the negative feedback from frequency to
voltage converter reduces the jitter at high frequencies. Finally
the proposed model is designed using CMOS 0.18um foundry
technology and simulated using P-Spice software. The result
shows that the proposed design improves the jitter attenuation at
different offset frequencies up to 40dB.

The implementation of a fully integrated multi standard low-jitter clock generator is presented. A L� fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 GHz wireline Serializer-Deserializer (SerDes) transmitting clock and... more

The implementation of a fully integrated multi standard low-jitter clock generator is presented. A L� fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 GHz wireline Serializer-Deserializer (SerDes) transmitting clock and spread spectrum clock generator (SSCG) for Serial AT Attachment (SATA I, 11, 1lI) characterized by a spread modulation of 5000 ppm. A mUlti-range voltage-controlled oscillator (YCO) is presented to handle the wide range of operation. The PLL ex hibits less than 3.5ps rms jitter at 6.3 GHz with power consumption of7 mW from 1.2 V and 2.5 V supply. EMI reduction is 20 dB. The design has been implemented in 90 nm CMOS process and occupies an area ofO.14xO.16 mm 2 • Index Terms-Phase-locked loop (PLL), Serializer Deserializer (SerDes), Spread spectrum clock generator (SSCG).

This paper discusses the pitch variation in Malay and English emotional voice samples for six emotion states. LP analysis is carried out to calculate the emotion features in speech and the results are observed in terms of average pitch,... more

This paper discusses the pitch variation in Malay and English emotional voice samples for six emotion states. LP analysis is carried out to calculate the emotion features in speech and the results are observed in terms of average pitch, pitch range and jitter. Comparison between male and female pitch is also done. Based on the pitch variation analysis, language factor does not affect the acoustic correlates of emotional speech.

We investigate the performance and design of free-space optical (FSO) communication links over slow fading channels from an information theory perspective. A statistical model for the optical intensity fluctuation at the receiver due to... more

We investigate the performance and design of free-space optical (FSO) communication links over slow fading channels from an information theory perspective. A statistical model for the optical intensity fluctuation at the receiver due to the combined effects of atmospheric turbulence and pointing errors is derived. Unlike earlier work, our model considers the effect of beam width, detector size, and jitter variance explicitly. Expressions for the outage probability are derived for a variety of atmospheric conditions. For given weather and misalignment conditions, the beam width is optimized to maximize the channel capacity subject to outage. Large gains in achievable rate are realized versus using a nominal beam width. In light fog, by optimizing the beam width, the achievable rate is increased by 80% over the nominal beam width at an outage probability of 10 −5 . Well-known error control codes are then applied to the channel and shown to realize much of the achievable gains.

The past few years have witnessed the emergence of many real-time networked applications on the Internet. These types of applications require special support from the underlying network such as reliability, timeliness, and guaranteed... more

The past few years have witnessed the emergence of many real-time networked applications on the Internet. These types of applications require special support from the underlying network such as reliability, timeliness, and guaranteed delivery, as well as different levels of ...

Terahertz technology is one of the research fronts in the microwave society. Among many technical challenges, achieving high-power terahertz radiation has been attracting many efforts. In this paper, we investigate the possibility of... more

Terahertz technology is one of the research fronts in the microwave society. Among many technical challenges, achieving high-power terahertz radiation has been attracting many efforts. In this paper, we investigate the possibility of power synthesis at low-end frequencies of the terahertz gap based on discrete sources. We show that by applying precision digital phase control, such a power synthesis can be achieved, overcoming the difficulty of phase alignment at these frequencies.

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio... more

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180nm as well as 90nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances. Index Terms-tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit.

The development of a three-electrode trigatron gap with the trigger electrode inside the main electrode is discussed in this paper. Two models of the operation mechanism are proposed to explain the breakdown in the trigatron gap. In... more

The development of a three-electrode trigatron gap with the trigger electrode inside the main electrode is discussed in this paper. Two models of the operation mechanism are proposed to explain the breakdown in the trigatron gap. In addition, a mathematical model was proposed to calculate the breakdown time based on the theoretical analysis. The influence of different parameters on the breakdown time is discussed. Some characteristics in dry air have been experimentally determined such as the influence of the air pressure and the influence of the undervoltage ratio on the spark gap operation. The experimental results show that the operating voltage range between 0.5 and 0.7 might be reasonable. Then, the experimental results and analysis demonstrate that there are three regions divided by two inflection points, and the corresponding values of the undervoltage ratio are threshold values presenting different breakdown processes.

As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor... more

As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express ® , DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in .2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to correct for PVT variation for optimum jitter performance and to monitor PLL bandwidth and jitter peaking.

Highly linear 3-level unit elements are available in any fully differential circuit. This is because each unit element in such a circuit can be either positively selected, negatively selected, or not selected. This paper presents a study... more

Highly linear 3-level unit elements are available in any fully differential circuit. This is because each unit element in such a circuit can be either positively selected, negatively selected, or not selected. This paper presents a study of dynamic element techniques for such elements. It is shown how traditional dynamic element-matching techniques for 2-level unit elements such as the data directed swapper, the vector selector, and the tree structure can be adapted toward linear 3-level elements. In all these cases, the amount of hardware is reduced significantly by using 3-level elements. Also several efficient "data weighted averaging"-like implementations are presented.

Ahstract-Last few decades has brought many fundamental changes to data communications and the Internet. Internet has its roots in a networking project started by ARPA which consisted of four computers. Now the Internet spans the However... more

Ahstract-Last few decades has brought many fundamental changes to data communications and the Internet. Internet has its roots in a networking project started by ARPA which consisted of four computers. Now the Internet spans the However transition to the new version has been remarkably slow. Thus in the interim, various transition mechanisms can be employed. In this paper two such mechanisms, namely configured tunnel and 6to4 transition mechanism, have been empirically evaluated for performance. Both mechanisms are implemented on two different Linux distributions, and performance related metrics like throughput, delay, jitter and CPU usage of the transition end nodes are measured. The results obtained on the test-bed show that TCPIUDP throughput and jitter values of the two mechanisms are similar, but delay reading is significantly different depending on the choice of transition mechanism and operating system.

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL... more

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 μm CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm2. Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.

In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the Single Sideband to Carrier Ratio (SSCR). The validity of the relationship between the time-and... more

In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the Single Sideband to Carrier Ratio (SSCR). The validity of the relationship between the time-and frequency-domain figures of merit has been first tested through the simulation of a widely popular case: the phase noise spectrum featured by PLL synthesizers. As a further proof, measurements have also been performed on CMOS and bipolar integrated VCOs and PLLs, by adopting time-to-amplitude conversion techniques.

In this paper, a high precision 80 GHz radar distance measurement system is presented. It is based on an ultra-wideband SiGe monostatic transceiver chip, which enables a bandwidth of 25.6 GHz around a center frequency of 80 GHz (i.e.... more

In this paper, a high precision 80 GHz radar distance measurement system is presented. It is based on an ultra-wideband SiGe monostatic transceiver chip, which enables a bandwidth of 25.6 GHz around a center frequency of 80 GHz (i.e. 32%). All components besides the silicon radar chip are off-the-shelf electronics, which makes the sensor well-suited for low-cost industrial measurement applications.

Mobile Ad hoc NETwork (MANET) is a collection of mobile nodes that are arbitrarily located so that the interconnections between nodes are dynamically changing. In MANET mobile nodes forms a temporary network without the use of any... more

Mobile Ad hoc NETwork (MANET) is a collection of mobile nodes that are arbitrarily located so that the interconnections between nodes are dynamically changing. In MANET mobile nodes forms a temporary network without the use of any existing network infrastructure or centralized administration. A routing protocol is used to find routes between mobile nodes to facilitate communication within the network. The main goal of such an ad hoc network routing protocol is to establish correct and efficient route between a pair of mobile nodes so that messages delivered within the active route timeout interval. Route should be discovered and maintained with a minimum of overhead and bandwidth consumption. This paper presents performance evaluation of three different routing protocols i.e. Dynamic Source Routing Protocol (DSR), Ad hoc On-demand Distance Vector (AODV), Fisheye State Routing (FSR) and Zone Routing Protocol (ZRP) with respect to variable pause times. Performance of DSR, FSR and ZRP is evaluated based on Average end-to-end delay, Packet delivery ratio, Throughput and Average Jitter.

Objective: Single fiber EMG (SFEMG) is a potent electrophysiological method to evaluate impaired neuromuscular transmission, and allows sensitive diagnosis of neuromuscular transmission abnormalities such as myasthenia gravis. The jitter... more

Objective: Single fiber EMG (SFEMG) is a potent electrophysiological method to evaluate impaired neuromuscular transmission, and allows sensitive diagnosis of neuromuscular transmission abnormalities such as myasthenia gravis. The jitter and fiber density values are different for various muscles and age groups and the reference values increase with age. In this study, we evaluated the reference values of jitter and fiber density of frontalis muscle in healthy subjects older than 70 years. Methods: We evaluated the jitter and fiber density of frontalis muscle in 32 healthy subjects. Twenty-two of them were between 70 and 79 years old (meanGSD, 73.9G1.7), and 10 of them were older than 80 years (meanGSD, 82.2G1.2). Results: Normal limit of jitter (95% confidence limit) was calculated as 40.4 ms for healthy subjects between 70 and 79 years old and 43.7 ms for healthy subjects older than 80 years and normal limit of fiber density (95% confidence limit) were calculated as 1.90 for subjects between 70 and 79 years old and 2.14 for subjects older than 80 years. Conclusions: We designated the reference values of jitter and fiber density for frontalis muscle in healthy subjects older than 70 years. Our reference values may have value to diagnose neuromuscular transmission abnormalities in elderly patients. Significance: SFEMG is sensitive for neuromuscular transmission abnormalities and it is important to know the reference values of frontalis muscle in healthy subjects older than 70 years.

We investigate the effects of input device latency and spatial jitter on 2D pointing tasks and a 3D movement. First, we characterize jitter and latency in a 3D tracking device and an optical mouse used for baseline comparison. We present... more

We investigate the effects of input device latency and spatial jitter on 2D pointing tasks and a 3D movement. First, we characterize jitter and latency in a 3D tracking device and an optical mouse used for baseline comparison. We present an experiment based on ISO 9241-9, which measures performance of pointing devices. We added latency and jitter to the mouse and compared it to a 3D tracker. Results indicate that latency has a stronger effect on performance than small spatial jitter. A second experiment found that erratic jitter "spikes" can affect 3D movement performance.