Wafer Research Papers - Academia.edu (original) (raw)

Defect detection is an important step in industrial production of monocrystalline silicon. Through the study of deep learning, this work proposes a framework for classifying monocrystalline silicon wafer defects using deep transfer... more

Defect detection is an important step in industrial production of monocrystalline silicon. Through the study of deep learning, this work proposes a framework for classifying monocrystalline silicon wafer defects using deep transfer learning (DTL). An existing pre-trained deep learning model was used as the starting point for building a new model. We studied the use of DTL and the potential adaptation of MobileNetV2 that was pre-trained using ImageNet for extracting monocrystalline silicon wafer defect features. This has led to speeding up the training process and to improving performance of the DTL-MobileNetV2 model in detecting and classifying six types of monocrystalline silicon wafer defects (crack, double contrast, hole, microcrack, saw-mark and stain). The process of training the DTL-MobileNetV2 model was optimized by relying on the dense block layer and global average pooling (GAP) method which had accelerated the convergence rate and improved generalization of the classificat...

The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To characterize modern ultrathin films, a reconsideration and review of Psi-MOSFET... more

The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To characterize modern ultrathin films, a reconsideration and review of Psi-MOSFET physics and models is required. Selected numerical simulations are presented, which shed light on the intriguing features governing Psi-MOSFET characteristics. Updated models accounting for the density of interface states and

Thermal oxidation is a process done to grow a layer of oxide on the surface of a silicon wafer at elevated temperatures to form silicon dioxide. Usually, it en- counters instability in oxide growth and results in variation in the oxide... more

Thermal oxidation is a process done to grow a layer of oxide on the surface of a silicon wafer at elevated temperatures to form silicon dioxide. Usually, it en- counters instability in oxide growth and results in variation in the oxide thickness formed. This leads to downtime of furnace and wafer scrap. This study focuses on the factors leading to this phenomenon and finding the optimum settings of these factors. The factors that cause instability to oxide thickness were narrowed down to location of wafer in furnace, oxidation time, gas flow rate and temperature. Characterization and optimization were done using Design of Experiments. Full factorial design was implemented using 4 factors and 2 levels, resulting in 16 runs. Data analysis was done using Multiple Regression Analysis in JMP software. Actual versus predicted plot is examined to determine whether the model fit is significant. Adjusted R2 value was obtained at 99.8% or 0.998 indicating that there is very minimal variatio...

Abstract: - The paper presents achievements made in original works performed by authors in the field of virtual prototyping atmospherical wafer manipulating robots and specific application for atmospherical wafer manipulation tasks. There... more

Abstract: - The paper presents achievements made in original works performed by authors in the field of virtual prototyping atmospherical wafer manipulating robots and specific application for atmospherical wafer manipulation tasks. There are succesively presented virtual ...

Wafers are low-moisture-baked foods. They are formed from a batter and baked between hot plates. The quality of wafer sheets is mainly controlled by flour property, water level and temperature, mixing action, baking time and temperature.... more

Wafers are low-moisture-baked foods. They are formed from a batter and baked between hot plates. The quality of wafer sheets is mainly controlled by flour property, water level and temperature, mixing action, baking time and temperature. The quality is judged by attributes of the batter such as the density, viscosity, holding time and temperature, and by properties of the wafer such as weight, surface colour, fragility and moisture content. In this study, the batter-specific gravity of 1.11–1.19 was recorded. Water and gluten content did not affect density. Water level, but not gluten content, however affected viscosity. Batter holding time drastically changed viscosity. The temperature of plates did significantly affect bake time. For wafer sheets with a high quality, 155–165% water level, 170 °C baking temperature and 2 min of bake time were found to be adequate. Wafer sheets baked at the lower temperatures stuck to the plates and broke up to several pieces. At a lower water level (<145%) and baking temperature of 150 °C, tough and flinty sheets were obtained, whereas at a water level higher than 160% and a higher temperature (190 °C), fragile sheets were obtained.

We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and... more

We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current drives in 〈110〉 channels, consistent with data.

Chemically amplified resist (CAR) performance can be greatly influenced by post apply bake (PAB) and post exposure bake (PEB) conditions. The difficulty with optimizing these conditions for photomask process is cost and time. In typical... more

Chemically amplified resist (CAR) performance can be greatly influenced by post apply bake (PAB) and post exposure bake (PEB) conditions. The difficulty with optimizing these conditions for photomask process is cost and time. In typical wafer CAR resist development, multiple wafer splits and skews can be rapidly processed with relatively low cost and fast turn around time, whereas in photomask processing each ebeam-written mask with a set of DOE conditions can be expensive and time consuming to produce. This paper discusses a novel mask design and testing methodology that allow for many combinations of PEB and PAB conditions to be evaluated with one mask. In brief, this methodology employs orthogonal PAB and PEB thermal gradients across a plate. Some thermal profile, darkloss, resist top down critical dimensions (CD), and SEM cross section image results will be shared and discussed.

We report a low-temperature process for covalent bonding of thermal SiO2 to plasma-enhanced chemical vapor deposited (PECVD) SiO2 for Si-compound semiconductor integration. A record-thin interfacial oxide layer of 60 nm demonstrates... more

We report a low-temperature process for covalent bonding of thermal SiO2 to plasma-enhanced chemical vapor deposited (PECVD) SiO2 for Si-compound semiconductor integration. A record-thin interfacial oxide layer of 60 nm demonstrates sufficient capability for gas byproduct diffusion and absorption, leading to a high surface energy of 2.65 J/m2 after a 2-h 300°C anneal. O2 plasma treatment and surface chemistry optimization in dilute hydrofluoric (HF) solution and NH4OH vapor efficiently suppress the small-size interfacial void density down to 2 voids/cm2, dramatically increasing the wafer-bonded device yield. Bonding-induced strain, as determined by x-ray diffraction measurements, is negligible. The demonstration of a 50 mm InP epitaxial layer transferred to a silicon-on-insulator (SOI) substrate shows the promise of the method for wafer-scale applications.

Microscopic imaging is used in most core technology processes where integrated circuit (IC) digital images reveal important information. We present a new method for navigation on wafers that is based on localization of microscopic... more

Microscopic imaging is used in most core technology processes where integrated circuit (IC) digital images reveal important information. We present a new method for navigation on wafers that is based on localization of microscopic eye-point images using a previously acquired wafer map. It is fast enough for in-line microscopy and robust to visual changes occurring during the manufacturing process, such as contrast variation, rescaling, rotation, and partial feature obliteration. The method uses geometric hashing, a highly efficient technique drawn from the object recognition field. This approach proved to be highly reliable when tested on typical wafer images.