LLVM: llvm::LanaiInstrInfo Class Reference (original) (raw)

#include "[Target/Lanai/LanaiInstrInfo.h](LanaiInstrInfo%5F8h%5Fsource.html)"

Public Member Functions
	LanaiInstrInfo (const LanaiSubtarget &STI)
virtual const LanaiRegisterInfo &	getRegisterInfo () const
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, Register DestinationRegister, Register SourceRegister, bool KillSource, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool	expandPostRAPseudo (MachineInstr &MI) const override
bool	getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand &BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo TRI) const
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TrueBlock, MachineBasicBlock &FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Condition) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TrueBlock, MachineBasicBlock FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition at line 27 of file LanaiInstrInfo.h.

◆ analyzeBranch()

Definition at line 562 of file LanaiInstrInfo.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::Instruction::eraseFromParent(), llvm::getImm(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ analyzeCompare()

◆ analyzeSelect()

◆ areMemAccessesTriviallyDisjoint()

Definition at line 88 of file LanaiInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::LocationSize::getValue(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::LocationSize::hasValue(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), llvm::LocationSize::precise(), and TRI.

◆ copyPhysReg()

◆ decomposeMachineOperandsTargetFlags()

◆ expandPostRAPseudo()

◆ getMemOperandsWithOffsetWidth()

◆ getMemOperandWithOffsetWidth()

◆ getRegisterInfo()

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const	override

◆ insertBranch()

◆ isLoadFromStackSlot()

◆ isLoadFromStackSlotPostFE()

◆ isStoreToStackSlot()

◆ loadRegFromStackSlot()

◆ optimizeCompareInstr()

Definition at line 285 of file LanaiInstrInfo.cpp.

References B(), llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), flagSettingOpcodeVariant(), llvm::get(), llvm::MachineInstr::getOpcode(), getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), I, llvm::LPCC::ICC_CC, llvm::LPCC::ICC_CS, llvm::LPCC::ICC_EQ, llvm::LPCC::ICC_F, llvm::LPCC::ICC_GE, llvm::LPCC::ICC_GT, llvm::LPCC::ICC_HI, llvm::LPCC::ICC_LE, llvm::LPCC::ICC_LS, llvm::LPCC::ICC_LT, llvm::LPCC::ICC_MI, llvm::LPCC::ICC_NE, llvm::LPCC::ICC_PL, llvm::LPCC::ICC_T, llvm::LPCC::ICC_VC, llvm::LPCC::ICC_VS, llvm::MachineOperand::isDef(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), MBB, MI, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Sub, TRI, and llvm::LPCC::UNKNOWN.

◆ optimizeSelect()

Definition at line 493 of file LanaiInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), canFoldIntoSelect(), llvm::MachineInstr::clearKillInfo(), llvm::MachineInstrBuilder::copyImplicitOps(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), getOppositeCondition(), llvm::MachineOperand::getReg(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, llvm::MCInstrDesc::operands(), llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().