Logic circuits Research Papers - Academia.edu (original) (raw)

This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented.

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- Computer Aided Manufacturing, Machine Vision, Very Large Scale Integration, Digital Logic

Intrinsic evolution in evolvable hardware research has hitherto been limited to using standard electronic components as the media for problem solving. However, recently it has been argued that because such components are human designed and intentionally has predictable responses; they may not be the optimal medium to use when trying to get a naturally inspired search technique to solve a problem. Evolution has been demonstrated as capable of exploiting the physical properties of material to form solutions; however, by giving evolution only conventional components, we may be placing arbitrary constraints on our ability to solve certain problems. We have shown for the first time, that liquid crystal can be used as the physical substrate for evolution. We demonstrate that it is possible to evolve various functions, including a tone discriminator, in materio.

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design. Index Termsreversible ALU design, reversible full adder, propagation delay. I.

- by Ashutosh Singh
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- Computers, Reversible Logic, Logic Synthesis, Logic Gates

This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitors all gate output swings and flags all abnormal voltage excursions. These detectors cover classes of faults that cannot be tested by stuck-at testing methods only. Circuit simulations have shown that abnormal gate output excursions caused by the presence of a defect are common with CML. We also show that this technique works well below "at-speed" frequencies. Finally, variants of the built-in detectors with reduced area overhead are proposed.

- by Saman Adham
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- Computer Science, Fault Detection, Digital Circuits, Detectors

This paper presents a new operation (exorlink) and an algorithm to minimize Exclusive-OR Sum-of-Products expressions (ESOP's) for multiple valued input, two valued output, incompletely specified functions. Exorlink is a more powerful operation than any other existing one for this problem. Evaluation on benchmark functions is given and it proves the superiority of the program to those known from the literature.

This paper proposes a new transistor topology to design gates required by Null Convention Logic for low voltage operation. The new topology enables implement all functionalities required by this design style. Extensive simulation results conducted in a 65 nm CMOS technology allow comparing the new topology to popular static and semi-static ones and indicate that the former presents better speed, energy and leakage trade-offs for different voltage levels, demonstrating the suitability of the new topology for low voltage applications. Drawbacks are an area of 4 minimum size transistors and reduced robustness against soft errors, when operating at non-minimum voltages.

- by Ney L V Calazans
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- Topology, Low Power Electronics, Capacitance, Network Topology
- by Ruby B. Lee
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- Sorting Algorithm, Logic Design, Block Cipher, Logic circuits

This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation.

- by Maria-cristina Marinescu
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- Computer Science, Parallel Algorithms, Pipeline, Speculation
- by Aneesh Koorapaty
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- Management, Computer Science, Algorithms, Design

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of

- by Wen T. Shiue
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- Engineering, VLSI, Digital Circuits, Very Large Scale Integration

Quantum gates which are represented by unitary matrices have potentials to implement reversible logic circuits. Y and y+ gates are two well known quantum gates which are used to synthesize the reversible logic circuits. In this paper we have used behavioral description of these gates, instead of unitary matrix description, to synthesize reversible logic circuits. By this method, Y and y+ gates are shown in the truth table form. Results show that bigger circuits with more number of gates can be synthesized using proposed Inethod. Some benchmarks of reversible logic circuits are also optimized and compared to other works.

- by Majid Mohammadi
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- Quantum Computing, Quantum Mechanics, Space Technology, Optimization

This paper presents an artificial intelligence based solution, proposed to solve electromagnetic interference problems between high voltage power lines and nearby metallic pipelines, for different construction geometries. The presented artificial intelligence method is a neural network one. Results gained with neural networks are compared to the finite element solutions considered as standard ones.

- by Czumbil Levente
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- Information Systems, Marketing, Engineering, Mechanical Engineering

Compiling high-level hardware languages can produce circuits containing combinational cycles that can never be sensitized. Such circuits do have well-defined functional behavior, but wreak havoc with most logic synthesis and timing tools, which assume acyclic combinational logic. As such, some sort of cycle-removal step is usually necessary for handling these circuits.

- by Stephen A. Edwards
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- Computer Science, High Level Synthesis, Hardware, Circuit Analysis
- by Mohammad Ali Mirzaei
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- Manufacturing, FPGA, Computer Hardware, Field-Programmable Gate Arrays

This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-μm CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz

- by mohamed allam
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- Low Power, Low Power Electronics, BIT, High performance

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.

- by Vadivel S
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- VLSI, Digital Circuits, Digital design, Power Consumption
- by Mitchell Thornton
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- Distributed Computing, Computer Hardware, Computer Software, Redundancy
- by Josep L. Rossello
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- Logic Programming, Microcontrollers, Logic Design, Logic Gates

Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit, the threshold voltage of the n-MOS transistors in the pass gate network must be reduced to about the zero voltage through threshold adjustments implants in order to eliminate the threshold voltage drop. Thus on the other hand reduces the overall noise immunity and makes the transistor more susceptible to sub threshold conduction in the off mode. Presented CPL design style is highly modular as a wide range of function can be realized by using this basic pass transistor structure.

- by harpreet parashar
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- VLSI, Time-Delay Systems, Very Large Scale Integration, Throughput

The recent development of Field-Programmable Gate Array (FPGA) architectures, with soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and IP cores, offers the potential for high computing power. Presently FPGAs are considered as a major platform for high performance embedded applications as it provides the opportunity for reconfiguration as well as good clock speed and design resources. As the complexities in the embedded applications increase, use of an operating system brings in a lot of advantages. In present day application scenarios most embedded systems have real-time requirements that demand the use of Real-time operating systems (RTOS), which creates a suitable environment for real time applications to be designed and expanded easily. In an RTOS the design process is simplified by splitting the application code into separate tasks and then the scheduler executes them according to a specific schedule, meeting the real-time deadline. In this research work, we propose the design and implementation of a real-time FPGA based application, which demonstrates the creation of real-time process tasks in FPGA systems for successful real-time communication between multiple FPGA systems. We have chosen the RSA based encryption and decryption algorithm for this implementation, as security is one of the most important need for data communication. At first we demonstrate the real-time execution of multiple process tasks in a single FPGA system for the encryption and decryption of data. Next we describe the most challenging part of our work, where we establish the real-time communication between two FPGA systems, each running the encryption engine and decryption engine respectively and communicating with one another via an RS232 communication link. The results show that our design is better in terms of execution speed in comparison with the existing research works.

- by Sangeet Saha and +1
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- Embedded Systems, Field-Programmable Gate Arrays, Encryption, OPERATING SYSTEM

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30× smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000× area overhead reduction compared to a worst-case based approach.

- by Mircea Stan
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- Sensor, Sensor Arrays, Sensors, Yield

We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in digital signal applications. The circuit uses the nonrestoring method to obtain quotient (root) bits. The quotient (root) value in each iterative step is kept in binary form whereas the partial remainders (radicands) are in redundant binary representations. The iterative core is a redundant binary and binary subtraction, implemented by a carry-save adder. The quotient (root) bit selection logic inputs leading three digits of partial remainders (radicands) and can be implemented in a simple circuit. The resultant circuit in 1.2 μm CMOS technology has an area of 6.72 mm2 and a speed of 47.7 ns and 49.2 ns for rounded quotient and square-root outputs respectively

- by Loc Hoang
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- Iterative Methods, VLSI, Very Large Scale Integration, BIT
- by Stefan Nedelcu
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- Logic Programming, Microcontrollers, Logic Design, Logic Gates

DSerent fast Fourier transform (FFT) algorithms for hardware implementation have been considered. We propose an implementation whereby two radix-N1'2 passes are carried out in parallel and in which each N1'2-point transform is carried out via a serial input parallel output transform circuit. The processing rate is one clock cycle per input point for the N-point transform regardless of the value of N chosen. The circuit is being implemented with TTL logic and will be used to perform spatial frequency domain filtering on two dimensional infrared camera images in real time; real time meaning processing between frame display.

- by Henry Buijs
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- Image Processing, Frequency-domain analysis, Hardware, Spatial Frequency

The pressure of fundamental limits on classical computation and the promise of exponential speedups from quantum effects have recently brought quantum circuits [10] to the attention of the Electronic Design Automation community . We discuss efficient quantum logic circuits which perform two tasks: (i) implementing generic quantum computations and (ii) initializing quantum registers. In contrast to conventional computing, the latter task is nontrivial because the state-space of an n-qubit register is not finite and contains exponential superpositions of classical bit strings. Our proposed circuits are asymptotically optimal for respective tasks and improve earlier published results by at least a factor of two.

- by Sourav Samanta
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- Quantum Computing, Computer Aided Design, Quantum Theory, Semiconductor Devices
- by T. Yildirim and +1
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- Design Methodology, Low Power Consumption, Encoding, Digital Circuit Synthesis
- by Igor Markov
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- Quantum Computing, Computer Graphics, Digital Signal Processing, Computer Hardware

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed for the first time. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Furthermore, both small load dependence and small fan-in dependence of gate delay time are also attained with this technique. A two-input gate fabricated with 0.3-pm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub-2-v supply. 1987, pp. 838-840. neers of Japan and the

- by Kazuo Yano
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- Digital Circuits, Degradation, High Speed, Voltage
- by Michael E. Imhof
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- Fault Detection, Fault Tolerance, Online testing, Low Power

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS 1 , are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.

- by Santanu Kar Mahapatra
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- Nanoelectronics, Packaging, Fabrication, Low Power

In this paper, we explain a new EDA tool framework that extends the reach of electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification

- by Fedor Pikus and +1
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- Data Mining, Layout, Real Time Application, Circuit Analysis

A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, can be modeled with Boolean relations. However, solving Boolean relations is a computationally expensive task. This paper presents a novel recursive algorithm for solving Boolean relations. The algorithm has several features: efficiency, wide exploration of solutions, and customizable cost function. The experimental results show the applicability of the method in logic minimization problems and tangible improvements with regard to previous heuristic approaches.

Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on Ant Colony Optimization (ACO). The paper studies the opportunities offered by ACO in comparison with other simulated-based ATPGs. The method is implemented and is shown to efficiently generate a set of test vectors that achieve a high fault coverage in a short time. Several benchmark circuits are attempted, and favorable results comparisons are reported.

- by Haidar Harmanani
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- Genetics, Mathematics, Computer Science, Ant Colony Optimization

- by Majid Mohammadi
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- Quantum Computing, Quantum Mechanics, Space Technology, Optimization

Interfas entre las compuertas logicas TTL y CMOS

- by Josue Leiva
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- Electronic Engineering, Electronics, Electronic Circuits, Logic circuits

This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity. This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.

- by Mahmod Kassab
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- Computer Architecture, Computational Modeling, Optimization, Arithmetic

In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-V t ) and multi-oxide-thickness (multi-t ox ) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

- by Volkan Kursun
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- Nanoelectronics, Circuits and Systems, System on Chip, Leakage Current
- by O. Franza
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- Topology, Frequency, Jitter, Network Topology

Ia. REPORT SECURITY CLASSIFICATION Ib. RESTRICTIVE MARKINGS Unclassified None Za. SECURITY CLASSIFICATION AUTHORITY 3. DISTRIBUTION IAVAILABILITY OF REPORT 2~b. I)ECLAS1FICATION DOWNGRADING SCHEDULE Approved for public release; distribution unlimited A. PERFORMING ORGANIZATION REPORT NUMBER(S) S MONITORING ORGANIZATION REPORT NUMBER(S) UILU-ENG-90-2252 6s. NAME OF I RFORMING ORGANIZATION 6b. OFFICE SYMBOL 7a. NAME OF MONITORING ORGANIZATION

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool.

- by Alex Bystrov
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- Distributed Computing, Logic, Computer Hardware, Cryptography

Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a Binary Decision Diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.

- by Rupali Singh
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- Quantum Computing, Quantum Logic, Optical computing, Data Structures

ABSTRACT This paper presents a self-test methodology and test structures for testing Through Silicon Vias (TSVs) in 3D-IC system prior to stacking in order to improve overall yield. A Scan Switch Network (SSN) architecture is proposed to perform pre-bond TSV scan testing. In the SSN, novel self-test structures are proposed and integrated to detect TSV defects by stuck-atfault and delay-based tests. By exploiting the inherent delay characteristics of TSV, the variation of TSV-to-substrate resistance caused by TSV defects can be mapped to a path delay change and detected. Compared with prior works, the proposed test architecture addresses pre-bond TSV testing under an integrated test solution with low overhead. Test chip measurement and analysis are presented to verify the proposed self-test methodology and structures.

- by Chao Wang and +1
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- Logic circuits

This paper deals with the practical application of the newly developed stochastic watt-hour meter. The limit of its precision is analyzed theoretically, via simulation, and experimentally. The precision of 0.0062% is achieved in the... more

This paper extends our original proposal to use Particle Swarm Optimization (PSO) to design combinational logic circuits in which a binary representation was adopted. In this case, we study the impact of the representation adopted. For that sake, we adopt 2 integer representations (one of which is proposed by us) and we compare them with respect to our previous binary representation and with respect to a multiobjective genetic algorithm that uses an integer encoding. For our comparative study, we adopted several combinational logic circuits of one and several outputs whose designs have been previously studied in the specialized literature. Our results indicate that PSO can be a competitive algorithm for circuit design when using one of the integer representations proposed.

- by Erika Luna
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- Computer Science, Computational Modeling, Evolutionary Computation, Genetic Algorithms
- by Maria Marinescu
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- Computer Science, Parallel Algorithms, Pipeline, Speculation

This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V.

- by C. Chakrabarti
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- Heuristics, Scheduling, VLSI, High Level Synthesis

A 3.8-11s 257-mW CMOS 16 X 16-b multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and higher logic functionality. Its multiplication time is the fastest ever reported, including bipolar and GaAs IC's, and it can he enhanced further to 2.6 ns with 60 mW at 77 K.

- by Kazuo Yano
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- Computer Aided Design, Performance, VLSI, Josephson Junctions

As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results obtained using the 70nm Berkeley Predictive Models [1], our proposed circuit increases the noise immunity by least 2X compared to previous circuits.

- by Adrian Ionescu
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- Nanoelectronics, Packaging, Fabrication, Low Power

- by Rachit Patel
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- VLSI, Time-Delay Systems, Very Large Scale Integration, Throughput