Reconfigurable Hardware Research Papers - Academia.edu (original) (raw)

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- Distributed Computing, Reconfigurable Computing, Computer Hardware, Video Compression
- by Georgi Gaydadjiev
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- Distributed Computing, Reconfigurable Computing, Polymorphism, FPGA
- by Miguel Figueroa
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- Embedded Systems, Computer Aided Design, Computer Hardware, Coding
- by Christoph Steiger
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- Distributed Computing, Computer Hardware, OPERATING SYSTEM, Computer Software
- by James Moscola and +1
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- Computer Science, Computer Networks, Automata, Field-Programmable Gate Arrays
- by Shreya Sen
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- Multitasking, Hardware, System on Chip, Reconfigurable Hardware
- by Miriam Leeser
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- Reconfigurable Hardware, Software Implementation, K Means, K means algorithm
- by Yvon Savaria
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- Distributed Computing, Digital Signal Processing, VLSI, Computer Hardware
- by Miriam Leeser
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- Fixed Point Theory, Reconfigurable Hardware, Formation Control, Floating Point
- by Zhiyuan Li
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- Distributed Computing, Reconfigurable Computing, VLSI, Computer Hardware
- by Sorin Cotofana
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- Reconfigurable Hardware, Cycle Time, Partial Reconfiguration

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.

- by T. Kalganova
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- Algorithms, Artificial Intelligence, Computer Aided Design, Multidisciplinary

Evolvable Hardware (EHW) refers to HW design and self reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. In addition, we illustrate with an example how evolution can recover functionality lost due to an increase in temperature. In the particular case of space applications, these characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life

- by Gerhard Klimeck
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- Genetics, Analog Circuits, Fuzzy Logic, Evolutionary genetics
- by E. Cabal-yepez
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- Engineering, Technology, Vibrations, Safety
- by Jean-jacques Quisquater
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- Reconfigurable Hardware, Design Criteria, Hardware Implementation of Algorithms, Block Cipher
- by Jörn W. Janneck
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- Case Study, Reconfigurable Hardware, Programming Model, Parallel Computer
- by Joao Cardoso
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- Finite Automata, Reconfigurable Hardware, Pattern Matching, Intrusion Detection System
- by Wayne Burleson
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- FPGA, Digital Communication, Reconfigurable Hardware, Performance Improvement
- by Manasseh Dickson
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- Software Security, Flow Control, Reconfigurable Hardware, Random access memory
- by Steve McKeever
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- Language Design, Hardware Design, Reconfigurable Hardware, Levels of Abstraction
- by Tiberiu Chelcea and +1
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- Architectural Design, Asynchronous circuit design, Reconfigurable Hardware, Low Power
- by Eduardo Ros
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- Computer Architecture, Computational Modeling, Real Time Computing, Computer Networks
- by Paul Beckett
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- Computer Architecture, Reconfigurable Hardware, MIMD, Programming Paradigm
- by Daniel Roggen
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- Software Design, Reconfigurable Hardware, Obstacle Avoidance, SPIKING NEURAL NETWORK
- by Guy Gogniat and +1
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- Distributed Computing, Computer Hardware, Reconfigurable Hardware, Security Policy
- by Joao Cardoso
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- Network Security, Case Study, Reconfigurable Hardware, Signal
- by Antonio García Ríos and +1
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- Distributed Computing, Computational Complexity, Digital Signal Processing, Computer Hardware
- by HARSH SINGH
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- Reconfigurable Hardware
- by Jorge Cerqueira
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- Hardware Design, Case Study, Reconfigurable Hardware, Software Implementation
- by Walid Najjar
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- Image Processing, Reconfigurable Computing, Language Design, Computer Model
- by Christof Paar
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- Reconfigurable Hardware
- by Gerard Rauwerda
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- Distributed Computing, Orthogonal Frequency Division Multiplexing (OFDM), Computer Hardware, Software Defined Radio
- by Nirmal Saxena
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- Computer Architecture, Data Compression, Field-Programmable Gate Arrays, Hardware
- by Christof Paar
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- Trusted Computing, Reconfigurable Hardware, Field Programmable Gate Array, Trusted Platform Module
- by Ryan Kastner
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- Methodology, Covert Channels, Field-Programmable Gate Arrays, Language Design
- by Walid Najjar
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- Image Processing, Reconfigurable Computing, Pattern Recognition, Timing Analysis
- by Jean-jacques Quisquater
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- Reconfigurable Hardware, Field Programmable Gate Array, Hardware Implementation of Algorithms, Block Cipher
- by Enrique Canto
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- Video Processing, System Architecture, Consumer Electronics, Reconfigurable Hardware
- by Ryan Kastner
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- Computer Architecture, Intellectual Property, Static Analysis, Embedded Systems
- by Antonio Ferrari
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- Distributed Computing, SAT Solver Design, VLSI, Computer Hardware
- by Jose M. Ferrandez
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- Augmented Reality, Reconfigurable Hardware, Real Time, User Perception
- by Sonia Mota and +1
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- FPGA, Speech Recognition, Computer Hardware, Reconfigurable Hardware
- by Joao Cardoso
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- Algorithms, Software Engineering, Programming Languages, Intellectual Property

In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full implementations of the new Advanced Encryption Standard, Rijndael, and the older American federal standard, Triple DES, were developed and experimentally tested using the SLAAC-1V FPGA accelerator board, based on Xilinx Virtex 1000 devices. The experimental clock frequencies were equal to 91 MHz for Triple DES, and 52 MHz for Rijndael. This translates to the throughputs of 116 Mbit/s for Triple DES, and 577, 488, and 423 Mbit/s for Rijndael with 128-, 192-, and 256-bit keys respectively. We also demonstrate a capability to enhance our circuit to handle the encryption and decryption throughputs of over 1 Gbit/s regardless of the chosen algorithm. Our estimates show that this gigabit-rate, double-algorithm, encryption/ decryption circuit will fit in one Virtex 1000 FPGA taking approximately 80% of the area.

- by Peter Bellows
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- Information Security, Reconfigurable Hardware, Experimental Tests

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and conn...

- by Youngkwan Cho
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- Semiconductors, Routing, Software, Humans

Nowadays a lot of multimedia applications are emerging on portable appliances. However these applications require both the flexibility of upgradable devices (typically software based) and a powerful computing engine (typically hardware).... more