LLVM: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp File Reference (original) (raw)

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

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Macros
#define DEBUG_TYPE "amdgpu-isel"
#define GET_GLOBALISEL_IMPL
#define AMDGPUSubtarget GCNSubtarget
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Enumerations
enum class SrcStatus { IS_SAME, IS_UPPER_HALF, IS_LOWER_HALF, IS_UPPER_HALF_NEG, IS_LOWER_HALF_NEG, IS_HI_NEG, IS_LO_NEG, IS_BOTH_NEG, INVALID, NEG_START = IS_UPPER_HALF_NEG , NEG_END = IS_BOTH_NEG , HALF_START = IS_UPPER_HALF , HALF_END = IS_LOWER_HALF_NEG }
enum class TypeClass { VECTOR_OF_TWO, SCALAR, NONE_OF_LISTED }
Functions
static Register getWaveAddress (const MachineInstr *Def)
static unsigned getLogicalBitOpcode (unsigned Opc, bool Is64)
static int getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
static bool isLaneMaskFromSameBlock (Register Reg, MachineRegisterInfo &MRI, MachineBasicBlock *MBB)
static unsigned gwsIntrinToOpcode (unsigned IntrID)
static bool parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static bool shouldUseAndMask (unsigned Size, unsigned &Mask)
static Register stripCopy (Register Reg, MachineRegisterInfo &MRI)
static Register stripBitCast (Register Reg, MachineRegisterInfo &MRI)
static bool isExtractHiElt (MachineRegisterInfo &MRI, Register In, Register &Out)
static bool isConstant (const MachineInstr &MI)
static bool isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
static std::pair< Register, unsigned > computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelValueTracking &ValueTracking)
Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
static std::pair< unsigned, uint8_t > BitOp3_Op (Register R, SmallVectorImpl< Register > &Src, const MachineRegisterInfo &MRI)
static bool isTruncHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
Test if the MI is truncating to half, such as reg0:n = G_TRUNC reg1:2n
static bool isLshrHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
Test if the MI is logic shift right with half bits, such as reg0:2n =G_LSHR reg1:2n, CONST(n)
static bool isShlHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
Test if the MI is shift left with half bits, such as reg0:2n =G_SHL reg1:2n, CONST(n)
static bool isUnmergeHalf (const MachineInstr *MI, const MachineRegisterInfo &MRI)
Test function, if the MI is reg0:n, reg1:n = G_UNMERGE_VALUES reg2:2n
static TypeClass isVectorOfTwoOrScalar (Register Reg, const MachineRegisterInfo &MRI)
static SrcStatus getNegStatus (Register Reg, SrcStatus S, const MachineRegisterInfo &MRI)
static std::optional< std::pair< Register, SrcStatus > > calcNextStatus (std::pair< Register, SrcStatus > Curr, const MachineRegisterInfo &MRI)
static SmallVector< std::pair< Register, SrcStatus > > getSrcStats (Register Reg, const MachineRegisterInfo &MRI, SearchOptions SO, int MaxDepth=3)
static std::pair< Register, SrcStatus > getLastSameOrNeg (Register Reg, const MachineRegisterInfo &MRI, SearchOptions SO, int MaxDepth=3)
static bool isSameBitWidth (Register Reg1, Register Reg2, const MachineRegisterInfo &MRI)
static unsigned updateMods (SrcStatus HiStat, SrcStatus LoStat, unsigned Mods)
static bool isValidToPack (SrcStatus HiStat, SrcStatus LoStat, Register NewReg, Register RootReg, const SIInstrInfo &TII, const MachineRegisterInfo &MRI)
static bool checkRB (Register Reg, unsigned int RBNo, const AMDGPURegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
static Register getLegalRegBank (Register NewReg, Register RootReg, const AMDGPURegisterBankInfo &RBI, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const SIInstrInfo &TII)
static Register buildRegSequence (SmallVectorImpl< Register > &Elts, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static void selectWMMAModsNegAbs (unsigned ModOpcode, unsigned &Mods, SmallVectorImpl< Register > &Elts, Register &Src, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static bool isNoUnsignedWrap (MachineInstr *Addr)
static void addZeroImm (MachineInstrBuilder &MIB)
static Register buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
Return a resource descriptor for use with an arbitrary 64-bit pointer.
static Register buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static Register buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static std::optional< uint64_t > getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
Get an immediate that must be 32-bits, and treated as zero extended.
unsigned getNamedBarrierOp (bool HasInlineConst, Intrinsic::ID IntrID)

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo

This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

◆ AMDGPUSubtarget

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-isel"

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

◆ SrcStatus

Enumerator
IS_SAME
IS_UPPER_HALF
IS_LOWER_HALF
IS_UPPER_HALF_NEG
IS_LOWER_HALF_NEG
IS_HI_NEG
IS_LO_NEG
IS_BOTH_NEG
INVALID
NEG_START
NEG_END
HALF_START
HALF_END

Definition at line 4451 of file AMDGPUInstructionSelector.cpp.

◆ TypeClass

◆ addZeroImm()

◆ BitOp3_Op()

Definition at line 3889 of file AMDGPUInstructionSelector.cpp.

References BitOp3_Op(), llvm::getSrcRegIgnoringCopies(), I, LHS, llvm::MIPatternMatch::m_AllOnesInt(), llvm::MIPatternMatch::m_Not(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, and RHS.

Referenced by BitOp3_Op(), and BitOp3_Op().

◆ buildAddr64RSrc()

◆ buildOffsetSrc()

◆ buildRegSequence()

Definition at line 5042 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), B(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm_unreachable, MRI, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by selectWMMAModsNegAbs(), and selectWMMAModsNegAbs().

◆ buildRSRC()

◆ calcNextStatus()

Definition at line 4691 of file AMDGPUInstructionSelector.cpp.

References getNegStatus(), INVALID, IS_HI_NEG, IS_LOWER_HALF, IS_LOWER_HALF_NEG, IS_SAME, IS_UPPER_HALF, IS_UPPER_HALF_NEG, isLshrHalf(), isShlHalf(), isTruncHalf(), isUnmergeHalf(), MI, MRI, and Opc.

Referenced by getLastSameOrNeg(), and getSrcStats().

◆ checkRB()

◆ computeIndirectRegIndex()

◆ getConstantZext32Val()

◆ getLastSameOrNeg()

◆ getLegalRegBank()

◆ getLogicalBitOpcode()

◆ getNamedBarrierOp()

◆ getNegStatus()

Definition at line 4535 of file AMDGPUInstructionSelector.cpp.

References INVALID, IS_BOTH_NEG, IS_HI_NEG, IS_LO_NEG, IS_LOWER_HALF, IS_LOWER_HALF_NEG, IS_SAME, IS_UPPER_HALF, IS_UPPER_HALF_NEG, isVectorOfTwoOrScalar(), llvm_unreachable, MRI, Reg, SCALAR, and VECTOR_OF_TWO.

Referenced by calcNextStatus().

◆ getSrcStats()

◆ getV_CMPOpcode()

Definition at line 1224 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, Select, and Size.

◆ getWaveAddress()

◆ gwsIntrinToOpcode()

◆ isConstant()

Definition at line 2935 of file AMDGPUInstructionSelector.cpp.

References MI.

Referenced by allConstant(), llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), getMemcpyLoadsAndStores(), slpvectorizer::BoUpSLP::getReorderingData(), isSimpleVIDSequence(), slpvectorizer::BoUpSLP::processBuildVector(), slpvectorizer::BoUpSLP::reorderBottomToTop(), tryFoldHelper(), and tryToFindDuplicates().

◆ isExtractHiElt()

Definition at line 2777 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), llvm::MIPatternMatch::m_GLShr(), llvm::MIPatternMatch::m_GTrunc(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_SpecificICst(), llvm::MIPatternMatch::mi_match(), MRI, stripBitCast(), and stripCopy().

Referenced by buildRegSequence16().

◆ isLaneMaskFromSameBlock()

Definition at line 1585 of file AMDGPUInstructionSelector.cpp.

References llvm::RegisterBank::getID(), llvm::isa(), isLaneMaskFromSameBlock(), LHS, llvm::MIPatternMatch::m_GAnd(), llvm::MIPatternMatch::m_Reg(), MBB, MI, llvm::MIPatternMatch::mi_match(), MRI, Reg, and RHS.

Referenced by isLaneMaskFromSameBlock().

◆ isLshrHalf()

◆ isNoUnsignedWrap()

◆ isSameBitWidth()

◆ isShlHalf()

◆ isTruncHalf()

◆ isUnmergeHalf()

◆ isValidToPack()

◆ isVCmpResult()

◆ isVectorOfTwoOrScalar()

◆ parseTexFail()

◆ selectWMMAModsNegAbs()

Definition at line 5070 of file AMDGPUInstructionSelector.cpp.

References assert(), buildRegSequence(), llvm::MIPatternMatch::m_GFabs(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

◆ shouldUseAndMask()

◆ stripBitCast()

◆ stripCopy()

◆ updateMods()