LLVM: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp File Reference (original) (raw)

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

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Macros
#define DEBUG_TYPE "amdgpu-isel"
#define GET_GLOBALISEL_IMPL
#define AMDGPUSubtarget GCNSubtarget
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Functions
static Register getWaveAddress (const MachineInstr *Def)
static unsigned getLogicalBitOpcode (unsigned Opc, bool Is64)
static int getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
static bool isLaneMaskFromSameBlock (Register Reg, MachineRegisterInfo &MRI, MachineBasicBlock *MBB)
static unsigned gwsIntrinToOpcode (unsigned IntrID)
static bool parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static bool shouldUseAndMask (unsigned Size, unsigned &Mask)
static Register stripCopy (Register Reg, MachineRegisterInfo &MRI)
static Register stripBitCast (Register Reg, MachineRegisterInfo &MRI)
static bool isExtractHiElt (MachineRegisterInfo &MRI, Register In, Register &Out)
static bool isConstant (const MachineInstr &MI)
static bool isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
static std::pair< Register, unsigned > computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits)
Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
static Register matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
Match a zero extend from a 32-bit value to 64-bits.
static std::pair< unsigned, uint8_t > BitOp3_Op (Register R, SmallVectorImpl< Register > &Src, const MachineRegisterInfo &MRI)
static Register buildRegSequence (SmallVectorImpl< Register > &Elts, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static void selectWMMAModsNegAbs (unsigned ModOpcode, unsigned &Mods, SmallVectorImpl< Register > &Elts, Register &Src, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
static bool isNoUnsignedWrap (MachineInstr *Addr)
static void addZeroImm (MachineInstrBuilder &MIB)
static Register buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
Return a resource descriptor for use with an arbitrary 64-bit pointer.
static Register buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static Register buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
static std::optional< uint64_t > getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
Get an immediate that must be 32-bits, and treated as zero extended.
unsigned getNamedBarrierOp (bool HasInlineConst, Intrinsic::ID IntrID)

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:

This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

◆ AMDGPUSubtarget

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-isel"

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

◆ addZeroImm()

◆ BitOp3_Op()

Definition at line 3648 of file AMDGPUInstructionSelector.cpp.

References BitOp3_Op(), llvm::getSrcRegIgnoringCopies(), I, LHS, llvm::MIPatternMatch::m_AllOnesInt(), llvm::PatternMatch::m_Not(), llvm::MIPatternMatch::m_Reg(), llvm::PatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, and RHS.

Referenced by BitOp3_Op().

◆ buildAddr64RSrc()

◆ buildOffsetSrc()

◆ buildRegSequence()

◆ buildRSRC()

◆ computeIndirectRegIndex()

◆ getConstantZext32Val()

◆ getLogicalBitOpcode()

◆ getNamedBarrierOp()

◆ getV_CMPOpcode()

Definition at line 1116 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::FCMP_FALSE, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_TRUE, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, Select, and Size.

◆ getWaveAddress()

◆ gwsIntrinToOpcode()

◆ isConstant()

◆ isExtractHiElt()

Definition at line 2622 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::LLT::fixed_vector(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getShuffleMask(), llvm::MIPatternMatch::m_GLShr(), llvm::MIPatternMatch::m_GTrunc(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_SpecificICst(), llvm::MIPatternMatch::mi_match(), MRI, stripBitCast(), and stripCopy().

Referenced by buildRegSequence16().

◆ isLaneMaskFromSameBlock()

◆ isNoUnsignedWrap()

◆ isVCmpResult()

◆ matchZeroExtendFromS32()

◆ parseTexFail()

◆ selectWMMAModsNegAbs()

Definition at line 4306 of file AMDGPUInstructionSelector.cpp.

References assert(), buildRegSequence(), llvm::MIPatternMatch::m_GFabs(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().

◆ shouldUseAndMask()

◆ stripBitCast()

◆ stripCopy()