LLVM: llvm::AMDGPURegisterBankInfo Class Reference (original) (raw)

#include "[Target/AMDGPU/AMDGPURegisterBankInfo.h](AMDGPURegisterBankInfo%5F8h%5Fsource.html)"

Public Member Functions
bool	buildVCopy (MachineIRBuilder &B, Register DstReg, Register SrcReg) const
bool	collectWaterfallOperands (SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
bool	executeInWaterfallLoop (MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs) const
	Legalize instruction MI where operands in OpIndices must be SGPRs.
Register	buildReadFirstLane (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
bool	executeInWaterfallLoop (MachineIRBuilder &B, MachineInstr &MI, ArrayRef< unsigned > OpIndices) const
void	constrainOpWithReadfirstlane (MachineIRBuilder &B, MachineInstr &MI, unsigned OpIdx) const
bool	applyMappingDynStackAlloc (MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
bool	applyMappingLoad (MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
bool	applyMappingImage (MachineIRBuilder &B, MachineInstr &MI, const OperandsMapper &OpdMapper, int RSrcIdx) const
unsigned	setBufferOffsets (MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const
bool	applyMappingSBufferLoad (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
bool	applyMappingBFE (MachineIRBuilder &B, const OperandsMapper &OpdMapper, bool Signed) const
bool	applyMappingMAD_64_32 (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
void	applyMappingSMULU64 (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
Register	handleD16VData (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
	Handle register layout difference for f16 images for some subtargets.
std::pair< Register, unsigned >	splitBufferOffsets (MachineIRBuilder &B, Register Offset) const
void	applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override
	See RegisterBankInfo::applyMapping.
const ValueMapping *	getValueMappingForPtr (const MachineRegisterInfo &MRI, Register Ptr) const
	Return the mapping for a pointer argument.
const RegisterBankInfo::InstructionMapping &	getInstrMappingForLoad (const MachineInstr &MI) const
unsigned	getRegBankID (Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const
const ValueMapping *	getSGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const ValueMapping *	getVGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const ValueMapping *	getAGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
void	split64BitValueForMapping (MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
	Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
template<unsigned NumOps>
InstructionMappings	addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
RegisterBankInfo::InstructionMappings	getInstrAlternativeMappingsIntrinsic (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
RegisterBankInfo::InstructionMappings	getInstrAlternativeMappingsIntrinsicWSideEffects (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
unsigned	getMappingType (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
bool	isSALUMapping (const MachineInstr &MI) const
const InstructionMapping &	getDefaultMappingSOP (const MachineInstr &MI) const
const InstructionMapping &	getDefaultMappingVOP (const MachineInstr &MI) const
const InstructionMapping &	getDefaultMappingAllVGPR (const MachineInstr &MI) const
const InstructionMapping &	getImageMapping (const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
	AMDGPURegisterBankInfo (const GCNSubtarget &STI)
bool	isDivergentRegBank (const RegisterBank *RB) const override
	Returns true if the register bank is considered divergent.
unsigned	copyCost (const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
	Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
unsigned	getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
	Get the cost of using ValMapping to decompose a register.
const RegisterBank &	getRegBankFromRegClass (const TargetRegisterClass &RC, LLT) const override
	Get a register bank that covers RC.
bool	isScalarLoadLegal (const MachineInstr &MI) const
InstructionMappings	getInstrAlternativeMappings (const MachineInstr &MI) const override
	Get the alternative mappings for MI.
const InstructionMapping &	getInstrMapping (const MachineInstr &MI) const override
	This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.
template<unsigned NumOps>
RegisterBankInfo::InstructionMappings	addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
Public Member Functions inherited from llvm::RegisterBankInfo
const RegisterBank *	getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
	Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
virtual	~RegisterBankInfo ()=default
const RegisterBank &	getRegBank (unsigned ID) const
	Get the register bank identified by ID.
unsigned	getMaximumSize (unsigned RegBankID) const
	Get the maximum size in bits that fits in the given register bank.
const RegisterBank *	getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
	Get the register bank of Reg.
unsigned	getNumRegBanks () const
	Get the total number of register banks.
bool	cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const
InstructionMappings	getInstrPossibleMappings (const MachineInstr &MI) const
	Get the possible mapping for MI.
void	applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
	Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
TypeSize	getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
	Get the size in bits of Reg.
bool	verify (const TargetRegisterInfo &TRI) const
	Check that information hold by this instance make sense for the given TRI.
const InstructionMapping &	getInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
	Method to get a uniquely generated InstructionMapping.
const InstructionMapping &	getInvalidInstructionMapping () const
	Method to get a uniquely generated invalid InstructionMapping.

Additional Inherited Members
Public Types inherited from llvm::RegisterBankInfo
using	InstructionMappings = SmallVector<const InstructionMapping *, 4>
	Convenient type to represent the alternatives for mapping an instruction.
Static Public Member Functions inherited from llvm::RegisterBankInfo
static void	applyDefaultMapping (const OperandsMapper &OpdMapper)
	Helper method to apply something that is like the default mapping.
static const TargetRegisterClass *	constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
	Constrain the (possibly generic) virtual register Reg to RC.
Static Public Attributes inherited from llvm::RegisterBankInfo
static const unsigned	DefaultMappingID = UINT_MAX
	Identifier used when the related instruction mapping instance is generated by target independent code.
static const unsigned	InvalidMappingID = UINT_MAX - 1
	Identifier used when the related instruction mapping instance is generated by the default constructor.
Protected Member Functions inherited from llvm::RegisterBankInfo
	RegisterBankInfo (const RegisterBank *RegBanks, unsigned NumRegBanks, const unsigned Sizes, unsigned HwMode)
	Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
	RegisterBankInfo ()
	This constructor is meaningless.
const RegisterBank &	getRegBank (unsigned ID)
	Get the register bank identified by ID.
const TargetRegisterClass *	getMinimalPhysRegClass (MCRegister Reg, const TargetRegisterInfo &TRI) const
	Get the MinimalPhysRegClass for Reg.
const InstructionMapping &	getInstrMappingImpl (const MachineInstr &MI) const
	Try to get the mapping of MI.
const PartialMapping &	getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
	Get the uniquely generated PartialMapping for the given arguments.
const ValueMapping &	getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
	The most common ValueMapping consists of a single PartialMapping.
const ValueMapping &	getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
	Get the ValueMapping for the given arguments.
template
const ValueMapping *	getOperandsMapping (Iterator Begin, Iterator End) const
	Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
const ValueMapping *	getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const
	Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.
const ValueMapping *	getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const
	Get the uniquely generated array of ValueMapping for the given arguments.
Protected Attributes inherited from llvm::RegisterBankInfo
const RegisterBank **	RegBanks
	Hold the set of supported register banks.
unsigned	NumRegBanks
	Total number of register banks.
const unsigned *	Sizes
	Hold the sizes of the register banks for all HwModes.
unsigned	HwMode
	Current HwMode for the target.
DenseMap< hash_code, std::unique_ptr< const PartialMapping > >	MapOfPartialMappings
	Keep dynamically allocated PartialMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< const ValueMapping > >	MapOfValueMappings
	Keep dynamically allocated ValueMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< ValueMapping[]> >	MapOfOperandsMappings
	Keep dynamically allocated array of ValueMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< const InstructionMapping > >	MapOfInstructionMappings
	Keep dynamically allocated InstructionMapping in a separate map.
DenseMap< MCRegister, const TargetRegisterClass * >	PhysRegMinimalRCs
	Getting the minimal register class of a physreg is expensive.

Definition at line 42 of file AMDGPURegisterBankInfo.h.

◆ addMappingFromTable() [1/2]

Definition at line 307 of file AMDGPURegisterBankInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, OpIdx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::RegisterBankInfo::Sizes, and TRI.

◆ addMappingFromTable() [2/2]

◆ applyMappingBFE()

Definition at line 1462 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), B(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::constrainSelectedInstRegOperands(), llvm::getIConstantVRegValWithLookThrough(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::isa(), llvm_unreachable, llvm::maskTrailingOnes(), MI, MRI, Opc, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, S64, llvm::LLT::scalar(), llvm::Signed, TII, and TRI.

Referenced by applyMappingImpl().

◆ applyMappingDynStackAlloc()

Definition at line 1159 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::assumeAligned(), B(), llvm::MachineFunction::getInfo(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::Log2(), MI, MRI, llvm::LLT::scalar(), SPReg, llvm::TargetFrameLowering::StackGrowsUp, TRI, and llvm::Align::value().

Referenced by applyMappingImpl().

◆ applyMappingImage()

◆ applyMappingImpl()

See RegisterBankInfo::applyMapping.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 2191 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), applyMappingBFE(), applyMappingDynStackAlloc(), applyMappingImage(), applyMappingLoad(), applyMappingMAD_64_32(), applyMappingSBufferLoad(), applyMappingSMULU64(), assert(), B(), llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, buildVCopy(), llvm::cast(), llvm::SmallVectorImpl< T >::clear(), collectWaterfallOperands(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, constrainOpWithReadfirstlane(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MachineInstrSpan::end(), executeInWaterfallLoop(), extendLow32IntoHigh32(), llvm::LLT::fixed_vector(), llvm::AMDGPU::getBaseWithConstantOffset(), getExtendOp(), llvm::MachineBasicBlock::getFirstTerminator(), getHalfSizedType(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::Type::getInt32Ty(), getIntrinsicID(), llvm::AMDGPU::getIntrinsicID(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::LLT::getNumElements(), llvm::MachineBasicBlock::getParent(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::Hi, I, llvm::AMDGPU::isFlatGlobalAddrSpace(), llvm::AMDGPU::RsrcIntrinsic::IsImage, llvm::LLT::isScalar(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, llvm_unreachable, llvm::Lo, llvm::AMDGPU::lookupRsrcIntrinsic(), llvm::LegalizerHelper::lowerAbsToMaxNeg(), llvm::MIPatternMatch::m_SpecificICstOrSplat(), llvm::make_range(), MBB, MI, llvm::MIPatternMatch::mi_match(), MRI, llvm::LegalizerHelper::narrowScalar(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::PartialMapping::RegBank, reinsertVectorIndexAdd(), llvm::SmallVectorImpl< T >::resize(), llvm::reverse(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, S32, S64, llvm::LLT::scalar(), setRegsToType(), llvm::Signed, llvm::SmallVectorTemplateCommon< T, typename >::size(), split64BitValueForMapping(), substituteSimpleCopyRegs(), Subtarget, TII, TRI, unpackV2S16ToS32(), llvm::LegalizerHelper::widenScalar(), llvm::LegalizerHelper::widenScalarDst(), llvm::LegalizerHelper::widenScalarSrc(), X, and Y.

◆ applyMappingLoad()

Definition at line 1041 of file AMDGPURegisterBankInfo.cpp.

References assert(), B(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::cast(), llvm::LLT::divide(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::LegalizerHelper::fewerElementsVector(), llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineMemOperand::getSize(), llvm::LLT::getSizeInBits(), llvm::LocationSize::getValue(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::AMDGPUSubtarget::GFX12, llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::LLT::isScalar(), isScalarLoadLegal(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, MI, MRI, llvm::LegalizerHelper::narrowScalar(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::LegalizerHelper::reduceLoadStoreWidth(), llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), splitUnequalType(), Subtarget, and widen96To128().

Referenced by applyMappingImpl().

◆ applyMappingMAD_64_32()

Definition at line 1568 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), B(), buildReadFirstLane(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::CmpInst::ICMP_SLT, llvm::MIPatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, S1, S32, llvm::LLT::scalar(), and Subtarget.

Referenced by applyMappingImpl().

◆ applyMappingSBufferLoad()

Definition at line 1344 of file AMDGPURegisterBankInfo.cpp.

References B(), llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::MachineInstrSpan::end(), executeInWaterfallLoop(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineFunction::getMachineMemOperand(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), getSBufferLoadCorrespondingBufferLoadOpcode(), llvm::SmallSet< T, N, C >::insert(), llvm::make_range(), MI, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, MRI, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), and setBufferOffsets().

Referenced by applyMappingImpl().

◆ applyMappingSMULU64()

Definition at line 2124 of file AMDGPURegisterBankInfo.cpp.

References llvm::Add, llvm::RegisterBankInfo::applyDefaultMapping(), assert(), B(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::Hi, MI, MRI, llvm::LLT::scalar(), setRegsToType(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and split64BitValueForMapping().

Referenced by applyMappingImpl().

◆ buildReadFirstLane()

Definition at line 701 of file AMDGPURegisterBankInfo.cpp.

References assert(), B(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::RegisterBankInfo::getRegBank(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S32, llvm::LLT::scalar(), and TRI.

Referenced by applyMappingMAD_64_32(), constrainOpWithReadfirstlane(), and executeInWaterfallLoop().

◆ buildVCopy()

◆ collectWaterfallOperands()

Definition at line 972 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::SmallSet< T, N, C >::empty(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::SmallSet< T, N, C >::insert(), MI, MRI, and TRI.

Referenced by applyMappingImpl(), and executeInWaterfallLoop().

◆ constrainOpWithReadfirstlane()

◆ copyCost()

◆ executeInWaterfallLoop() [1/2]

Legalize instruction MI where operands in OpIndices must be SGPRs.

If any of the required SGPR operands are VGPRs, perform a waterfall loop to execute the instruction for each unique combination of values in all lanes in the wave. The block will be split such that rest of the instructions are moved to a new block.

Essentially performs this loop: Save Execution Mask For (Lane : Wavefront) { Enable Lane, Disable all other lanes SGPR = read SGPR value for current lane from VGPR VGPRResult[Lane] = use_op SGPR } Restore Execution Mask

There is additional complexity to try for compare values to identify the unique values used.

Definition at line 773 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::AMDGPU::LaneMaskConstants::AndSaveExecOpc, assert(), B(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), buildReadFirstLane(), llvm::SmallSet< T, N, C >::count(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineBasicBlock::end(), llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::AMDGPU::LaneMaskConstants::get(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::CmpInst::ICMP_EQ, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineFunction::insert(), llvm::RegState::Kill, llvm::make_range(), MBB, MBBI, MI, llvm::AMDGPU::LaneMaskConstants::MovOpc, llvm::AMDGPU::LaneMaskConstants::MovTermOpc, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Range, S1, llvm::LLT::scalar(), llvm::MachineBasicBlock::splice(), Subtarget, TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), TRI, and llvm::AMDGPU::LaneMaskConstants::XorTermOpc.

Referenced by applyMappingImage(), applyMappingImpl(), applyMappingSBufferLoad(), and executeInWaterfallLoop().

◆ executeInWaterfallLoop() [2/2]

◆ getAGPROpMapping()

◆ getBreakDownCost()

◆ getDefaultMappingAllVGPR()

◆ getDefaultMappingSOP()

◆ getDefaultMappingVOP()

◆ getImageMapping()

Definition at line 3685 of file AMDGPURegisterBankInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), getRegBankID(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getInstrAlternativeMappings()

Get the alternative mappings for MI.

Alternative in the sense different from getInstrMapping.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 468 of file AMDGPURegisterBankInfo.cpp.

References addMappingFromTable(), assert(), llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstrAlternativeMappings(), getInstrAlternativeMappingsIntrinsic(), getInstrAlternativeMappingsIntrinsicWSideEffects(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), isScalarLoadLegal(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, MRI, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPUAS::REGION_ADDRESS, Size, and TRI.

◆ getInstrAlternativeMappingsIntrinsic()

◆ getInstrAlternativeMappingsIntrinsicWSideEffects()

◆ getInstrMapping()

This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.

Any mapping that would cause a VGPR to SGPR generated is illegal.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 3835 of file AMDGPURegisterBankInfo.cpp.

◆ getInstrMappingForLoad()

Definition at line 3744 of file AMDGPURegisterBankInfo.cpp.

References llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), llvm::AMDGPU::isFlatGlobalAddrSpace(), isScalarLoadLegal(), MI, MRI, Size, Subtarget, and TRI.

Referenced by getInstrMapping().

◆ getMappingType()

◆ getRegBankFromRegClass()

Get a register bank that covers RC.

Precondition

RC is a user-defined register class (as opposed as one generated by TableGen).

Note

The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.

Todo

This should be TableGen'ed.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 288 of file AMDGPURegisterBankInfo.cpp.

References llvm::LLT::scalar(), and TRI.