Embedded processor Research Papers - Academia.edu (original) (raw)

Top Papers
Most Cited Papers
Most Downloaded Papers
Newest Papers
People
- by
- •
- Working Memory, Memory, Reading and writing, Embedded processor
- by Stan Liao
- •
- Code Generation, Embedded processor, Code Optimization, Integrated Circuit
- by Benoit Meister
- •
- Temporal Data Mining, Optimization, Power Consumption, Embedded processor
- by Hasan Sohofi
- •
- Design Space Exploration, Embedded processor, FDL, Product Quality
- by IJERA Journal
- •
- Computer Science, Arm, AVR, Embedded processor
- by Malin Premaratne and +1
- •
- Design, Image Processing, Signal Processing, Face Recognition
- by Jason M Scott
- •
- Signal Processing, Flow Control, Design process, Design Tool

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

- by Marcelo Segura and +1
- •
- Digital Signal Processing, FPGA implementation, Field Programmable Gate Array, Embedded processor
- by P. Pucyk
- •
- Control system, Embedded processor
- by P. Pucyk
- •
- Control system, Embedded processor
- by Ian McLoughlin
- •
- Economics, Intellectual Property, Manufacturing, Reverse Engineering
- by Simon Matabva
- •
- Sensor Network, Low Power, Medical Care, Embedded processor

This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.

The potential of modern telecommunications and computing technologies as tools in the delivery and evaluation of assistive technology (AT) has been discussed and has been termed telerehabilitation. The problems of providing AT in rural areas parallels the delivery of health care to rural areas where the proportion of people with chronic illnesses is higher and the means to pay for them is reduced. Large distances mean long travel times, increasing costs associated with any service delivery, and consuming valuable time skilled professionals could be using to provide services elsewhere. The technology available for practising telerehabilitation is significant and expanding at a rapid rate. Currently, plain old telephone systems (POTS) and broad-band videoconferencing equipment, Internet and World Wide Web, and embedded processor systems are most widely available. These technologies continue to evolve as well as emerging technologies such as wearable sensors that will have telehabilitation applications. Issues of payment, safety liability, and licensure need to be resolved, as legislation lags the development of new technologies

- by David Brienza
- •
- Biomedical Engineering, Assistive Technology, Chronic illness, Video Conferencing
- by baker mohammad
- •
- Embedded Systems, Embedded processor, Integrated Circuit Design
- by Mehmet R Eskicioglu
- •
- Health Care, Query Optimization, Sensor Network, Embedded processor
- by Jason Tong
- •
- Embedded Systems, Hardware Description Languages, Open Source, Embedded processor
- by Ray Cheung
- •
- Reconfigurable Computing, Embedded Systems, Embedded processor, Data representation
- by Dimitrios Serpanos
- •
- Embedded Systems, Packet Switching, Memory Management, Parallel Processing
- by Ramon Vios
- •
- Parallel Computing, Intellectual Property, Production, VLSI
- by Jelena Trajkovic
- •
- Distributed Computing, Energy Consumption, Computer Hardware, Computer Software
- by Yervant Zorian
- •
- Computer Aided Design, System on Chip, Cost effectiveness, Embedded processor

Sorting is an important operation for a number of embedded applications. As sorting large datasets may impose undesired performance degradation, acceleration units coupled to the embedded processor can be an interesting solution for speeding-up the computations. This paper presents and evaluates three hardware sorting units, bearing in mind embedded computing systems implemented with FPGAs. The proposed architectures take advantage of specific FPGA hardware resources to increase efficiency. Experimental results show the ...

Abstract—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor de- sign tool sets. The emphasis,is onthe applicability of the gener- ated tools in the ,design space exploration (DSE) phase of de- signing a new,embedded,processor. APDL descriptions can be used for generating cycle-accurate instruction set simulators, assembler/disassembler tools, production quality compilers and architecture verification tools. The paper

- by Zainalabedin Navabi
- •
- Design Space Exploration, Embedded processor, Product Quality

Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines the best instruction set to use for a given program and... more

- by Guido Bertoni and +1
- •
- Tate pairing, White Paper, Embedded processor, Smartcard
- by Rajendra Hegadi
- •
- Signal Processing, Low Power, Embedded processor, High performance
- by Mahdi Fazeli
- •
- Embedded Systems, Energy Consumption, Memory Management, Predictability
- by Dimitrios Serpanos
- •
- Embedded Systems, Packet Switching, Memory Management, Parallel Processing

In this paper, we introduce a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today's hardware technology, may be implemented on a single chip (SoC–System on a Chip). Existing approaches for mapping computational-intensive ...

Abstract. We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. This in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. This results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance. 1

- by Amirali Baniasadi
- •
- Samos, Embedded processor, Power Optimization, Leakage Power
- by Serdar Yilmaz
- •
- Architecture, Embedded Systems, Memory Management, Energy efficiency
- by John Kalomiros
- •
- Image Processing, FPGA, System Integration, Computer Hardware
- by Theo Ungerer
- •
- Software Development, OPERATING SYSTEM, Data Structure, Embedded processor