FPGA Architecture Research Papers - Academia.edu (original) (raw)

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  • Logic Synthesis, Technology Mapping, FPGA Architecture, Functional Decomposition
• • by Pedro Diniz
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  • Image Processing, Machine Vision, Parallelizing Compilers, Parallel Computer
• • by Joseph R Cavallaro
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  • Signal Processing, Hardware/Software Co-Design, Case Study, Design Space Exploration
• • by Scott Gould and +1
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  • Routing, Field-Programmable Gate Arrays, Network Routing, Logic Design
• • by Mariusz Rawski
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  • Digital Signal Processing, Design process, Digital Signal Processor, Distributed arithmetic
• • by fir da
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  • FPGA Architecture and CAD, Hardware Design, Field Programmable Gate Array, FIR filter
• • by Yaser Jararweh and +1
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  • Satellite Communication, Algorithm Design, FPGA Architecture

This work presents a Hardware/Software FPGA Robotics Architecture for applications on Mobile Robotics. A test mobile robot was built and it is based in a commercial programmable robot called Create from iRobot, also the test platform has... more

This work presents a Hardware/Software FPGA Robotics Architecture for applications on Mobile Robotics. A test mobile robot was built and it is based in a commercial programmable robot called Create from iRobot, also the test platform has additional components like sonars, infrared sensors and a robotic arm, these components are used to increase robot’s functionality and to show that it is feasible to build any kind of hybrid robot. The Hardware/Software Architecture is a complete Embedded System (ES). Hardware side includes processor, buses, memory and peripherals like co-processors, sensors, robotic arm, controllers, UARTs, etc., Software side includes a Linux OS with a set of libraries that performs different functionalities and to control all components in FPGA, these functions are easy-understanding for robotic programmers. The main purpose of this work is to show the advantages of using FPGAs to implement Robotics Platforms. Some of these advantages are parallelism, flexibility and scalability. Finally some experiments was performed to show these advantages.

• • by Miguel Arias-Estrada
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  • Software Architecture, Mobile Robot, Robot Arm, Infrared
• • by Amara Amara
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  • Intellectual Property, Microelectronics, Power Consumption, Low Energy Buildngs
• • by Costas Argyrides
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  • Remote Sensing, Error Correction, Circuit Design, IPDPS
• • by Grzegorz Borowik and +2
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  • Digital Circuits, Information Processing, Digital Systems Design, Logic Synthesis
• • by Malgorzata Marek-sadowska
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  • Logic Gate, FPGA Architecture

This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications... more

This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals under bundled-data delay assumption. The size and shape of each locally synchronous block are programmable so that different modules in a design can be effectively implemented. By dividing the FPGA area into smaller blocks, the delays of long interconnect wires, which could easily dominate other delays in conventional FPGAs, only come into picture when there are communications between blocks. Therefore, each block could run at higher speed. The area overhead of adopting the GALS style in GAPLA architecture is estimated to be very small (about 7%). Experimental results show an up to 55% performance improvement compared to the conventional FPGAs.

• • by Ranga Vemuri and +1
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  • Performance Evaluation, Data Communication, Performance Improvement, Programmable logic array

In the past, prior to the availability of simulation techniques for large ASIC designs, designers relied on prototypes of their systems for design verification. The prototypes were usually built early in the design cycle to allow software... more

In the past, prior to the availability of simulation techniques for large ASIC designs, designers relied on prototypes of their systems for design verification. The prototypes were usually built early in the design cycle to allow software debugging. More recently, ASIC design relied ...

• • by Joseph Hughes
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  • Field Programmable Gate Array, Application Specific Integrated Circuit (ASIC), FPGA Architecture
• • by Dzmitry Stsepankou
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  • Parallel Processing, Image Quality, Real Time, Floating Point
• • by Dimitrios Soudris
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  • Graphic User Interface Design, Reconfigurable Hardware, Low Power, Digital Logic

An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on the characteristics of spectral images and... more

An adaptive FPGA architecture based on the NoC (Network-on-Chip) approach is used for the multispectral image correlation. This architecture must contain several distance algorithms depending on the characteristics of spectral images and the precision of the authentication. The analysis of distance algorithms is required which bases on the algorithmic complexity, result precision, execution time and the adaptability of the implementation.

• • by Virginie Fresse
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  • Network on chip, Multispectral Images, Spectral Imaging, FPGA Architecture
• • by Amine Chohra
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  • Decision Making, Fuzzy Logic, Back Propagation, Soft Computing

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient... more

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to

• • by Ricardo Augusto da Luz Reis
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  • Fault Injection, Space Application, Fault Tolerant, Power Dissipation
• • by F Christopher Reynolds
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  • FPGA, Field-Programmable Gate Arrays, Codesign, Formal Verification

Abstract. The dynamically reconfigurable hardware can be changed during run-time and more areas of an application can be mapped to the hardware in sharing fashion with potential of parallel processing. This leads to an overall improvement... more

Abstract. The dynamically reconfigurable hardware can be changed during run-time and more areas of an application can be mapped to the hardware in sharing fashion with potential of parallel processing. This leads to an overall improvement in performance of reconfigurable FPGA fabric as the hardware accelerator. But the concurrence in sharing FPGA architecture is becoming an important issue. In this context, we develop a simple and intuitive algorithm to explain when and why a dynamic reconfiguration solution is lead to ...

• • by Phan Cong-Vinh
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  • Computer Science, Parallel Processing, Field Programmable Gate Array, Control Reconfiguration
• • by Badie Ghavami
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  • Engineering, Embedded Systems, Cryptography, Field-Programmable Gate Arrays

Abstract—This paper studies power modeling for field program-mable gate arrays (FPGAs) and investigates FPGA power char-acteristics in nanometer technologies. Considering both dynamic and leakage power, a mixed-level power model that... more

Abstract—This paper studies power modeling for field program-mable gate arrays (FPGAs) and investigates FPGA power char-acteristics in nanometer technologies. Considering both dynamic and leakage power, a mixed-level power model that combines switch-level models for ...

• • by Deming Chen
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  • Computer Aided Design, Computer Hardware, Field-Programmable Gate Arrays, Power Analysis
• • by Mohammad Ali Mirzaei
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  • Distributed Computing, Architecture, Computer Aided Design, VLSI

Software defined radio (SDR) is an important element of wireless technology and fast becoming a hot topic in the telecommunication field. Determining the digital hardware composition of a software radio is a key design step in its... more

Software defined radio (SDR) is an important element of wireless technology and fast becoming a hot topic in the telecommunication field. Determining the digital hardware composition of a software radio is a key design step in its creation. Hybrid GPP/DSP/FPGA architecture is a viable solution for software defined radio technology. This paper demonstrates a practical design and implementation procedure for a wireless digital modem on software defined radio platforms and reports a detailed description of the baseband signal processing logic design in the FPGA portion of it. Design verification is performed through hardware in the loop testing methodology. A framework for designing wireless digital modems on hybrid software radio platforms is discussed.

• • by Yahia Tachwali
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  • Computer Architecture, Signal Processing, FPGA, Digital Signal Processing
• • by Mariusz Rawski
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  • Digital Signal Processing, Design process, Digital Signal Processor, Distributed arithmetic
• • by Nikolay Laptev
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  • Resource Allocation, System Architecture, Design Space Exploration, Matrix Decomposition
• • by Davide Pandini
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  • Hybrid Architecture, DESIGN SPACE, FPGA Architecture
• • by Magdy Saeb
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  • Architecture, FPGA, Process Control, Cryptography

The paper presents an integration of both encryption and authentication algorithms in one chip. The proposed unit is designed using Mentor Graphics FPGA Adv. Pro tools and implemented on XILINX XC4085XL chip. The encryption system used is... more

The paper presents an integration of both encryption and authentication algorithms in one chip. The proposed unit is designed using Mentor Graphics FPGA Adv. Pro tools and implemented on XILINX XC4085XL chip. The encryption system used is based on the synchronous stream cipher algorithm. Both functional and timing simulation are performed. The output of the unit passed the randomness tests performed namely frequency, serial and poker tests

• • by Ufuah John
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  • Architecture, FPGA, Process Control, Cryptography
• • by Alex Jones
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  • Speech Recognition, hidden Markov model, Real Time, Electrical And Electronic Engineering
• • by Mohamed Basuony
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  • Nanotechnology, Multidisciplinary, Nanowires, Power Consumption
• • by Joseph R Cavallaro
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  • Computer Architecture, Wireless Systems, VLSI, Hardware Description Languages
• • by Tadeusz Łuba and +1
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  • Digital Circuits, Information Processing, Digital Systems Design, Logic Synthesis
• • by Imran Yildiz
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  • Mobile Video, Motion estimation, Power Consumption, Low Power

RISPs (Reconfigurable Instruction Set Processors) are increasingly becoming popular as they can be customized to meet design constraints. However, existing instruction set customization methodologies do not lend well for mapping custom... more

RISPs (Reconfigurable Instruction Set Processors) are increasingly becoming popular as they can be customized to meet design constraints. However, existing instruction set customization methodologies do not lend well for mapping custom instructions on to commercial FPGA architectures. In this paper, we propose a design exploration framework that provides for rapid identification of a reduced set of profitable custom instructions and their area costs on commercial architectures without the need for time consuming hardware synthesis process. A novel clustering strategy is used to estimate the utilization of the LUT (Look-Up Table) based FPGAs for the chosen custom instructions. Our investigations show that the area costs computations using the proposed hardware estimation technique on 20 custom instructions are shown to be within 8% of those obtained using hardware synthesis. A systematic approach has been adopted to select the most profitable custom instruction candidates. Our investigations show that this leads to notable reduction in the number of custom instructions with only marginal degradation in performance. Simulations based on domain-specific application sets from the MiBench and MediaBench benchmark suites show that on average, more than 25% area utilization efficiency (performance/area) can be achieved with the proposed technique.

• • by Siew Kei Lam
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  • FPGA, Computer Software, Profitability, Look up Table
• • by Ryan Kastner
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  • Computer Architecture, Intellectual Property, Static Analysis, Embedded Systems
• • by Abhishek Das
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  • Principal Component Analysis, Anomaly Detection, FPGA implementation, Principle component analysis
• • by Dimitrios Soudris
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  • Information Systems, Law, Power Consumption, Low Power
• • by Mariusz Rawski and +2
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  • High performance, Digital Filter Design, Distributed arithmetic, FPGA Architecture

Computing systems designed using reconfigurable hardware are increasingly composed using a number of different Intellectual Property (IP) cores, which are often provided by third-party vendors that may have different levels of trust.... more

Computing systems designed using reconfigurable hardware are increasingly composed using a number of different Intellectual Property (IP) cores, which are often provided by third-party vendors that may have different levels of trust. Unlike traditional software where hardware resources are mediated using an operating system, IP cores have fine-grain control over the underlying reconfigurable hardware. To address this problem, the embedded systems community requires novel security primitives that address the realities of modern reconfigurable hardware. In this work, we propose security primitives using ideas centered around the notion of “moats and drawbridges.” The primitives encompass four design properties: logical isolation, interconnect traceability, secure reconfigurable broadcast, and configuration scrubbing. Each of these is a fundamental operation with easily understood formal properties, yet they map cleanly and efficiently to a wide variety of reconfigurable devices. We ca...

• • by thuy nguyen
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  • Computer Science, Computer Architecture, Intellectual Property, Static Analysis
• • by Abhishek Ranjan
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  • Computer Architecture, Government, FPGA, Biology

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an... more

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.

• • by Alex Marcelo
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  • Signal Processing, Digital Signal Processing, Application Integration (Computer Science), System on Chip
• • by Ryan Kastner
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  • Statistical Analysis, Power Consumption, Leakage Power, FPGA Architecture
• • by Abhishek Das
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  • Principal Component Analysis, Anomaly Detection, FPGA implementation, Principle component analysis
• • by G. Memik
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  • Computer Science, Analytic Network Process, Software Implementation, Feature Extraction

The goal of this paper is to promote application of logic synthesis methods and tools in different tasks of modern digital designing. The paper discusses functional decomposition methods, which are currently being investigated, with... more

The goal of this paper is to promote application of logic synthesis methods and tools in different tasks of modern digital designing. The paper discusses functional decomposition methods, which are currently being investigated, with special attention to balanced decomposition. Since technological and computer experiments with application of these methods produce promising results, this kind of logic synthesis will probably dominate the development of digital circuits for FPGA structures. Many examples confirming effectiveness of decomposition method in technology mapping in digital circuits design for cryptography and DSP applications are presented.

• • by Mariusz Rawski
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  • Engineering, Signal Processing, FPGA, Cryptography
• • by Jean-Michel Muller
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  • Computer Architecture, FPGA implementation, Field Programmable Gate Array, Floating Point
• • by Deming Chen
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  • Simulated Annealing, Field-Programmable Gate Arrays, High Level Synthesis, Low Power Design

In this paper we exploit FPGA flexibility in the context of accelerating the solution of many small systems of linear equations, a problem central to model predictive control (MPC). The main observation exploited by this work is the... more

In this paper we exploit FPGA flexibility in the context of accelerating the solution of many small systems of linear equations, a problem central to model predictive control (MPC). The main observation exploited by this work is the distinction between accuracy (meaning the degree of correctness of a final computational result) and precision (meaning the degree of correctness of each atomic computation). Using iterative methods for solving linear systems, one can obtain improved accuracy either by running more iterations or by ...

• • by Amir Shahzad
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  • Computer Architecture, Model Predictive Control, Iterative Methods, FPGA