ARMFrameLowering.cpp File Reference (original) (raw)

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Macros
#define	DEBUG_TYPE "arm-frame-lowering"

Enumerations
enum class	SpillArea { GPRCS1, GPRCS2, FPStatus, DPRCS1, DPRCS2, GPRCS3, FPCXT }

Functions
static MachineBasicBlock::iterator	skipAlignedDPRCS2Spills (MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs)
	Skip past the code inserted by emitAlignedDPRCS2Spills, and return an iterator to the following instruction.
SpillArea	getSpillArea (Register Reg, ARMSubtarget::PushPopSplitVariation Variation, unsigned NumAlignedDPRCS2Regs, const ARMBaseRegisterInfo *RegInfo)
	Get the spill area that Reg should be saved into in the prologue.
static int	getArgumentStackToRestore (MachineFunction &MF, MachineBasicBlock &MBB)
static bool	needsWinCFI (const MachineFunction &MF)
static MachineBasicBlock::iterator	insertSEH (MachineBasicBlock::iterator MBBI, const TargetInstrInfo &TII, unsigned Flags)
static MachineBasicBlock::iterator	initMBBRange (MachineBasicBlock &MBB, const MachineBasicBlock::iterator &MBBI)
static void	insertSEHRange (MachineBasicBlock &MBB, MachineBasicBlock::iterator Start, const MachineBasicBlock::iterator &End, const ARMBaseInstrInfo &TII, unsigned MIFlags)
static void	emitRegPlusImmediate (bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
static void	emitSPUpdate (bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
static int	sizeOfSPAdjustment (const MachineInstr &MI)
static bool	WindowsRequiresStackProbe (const MachineFunction &MF, size_t StackSizeInBytes)
static void	emitAligningInstructions (MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction)
	Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bits.
static int	getMaxFPOffset (const ARMSubtarget &STI, const ARMFunctionInfo &AFI, const MachineFunction &MF)
	We need the offset of the frame pointer relative to other MachineFrameInfo offsets which are encoded relative to SP at function begin.
static void	emitAlignedDPRCS2Spills (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
	Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
static void	emitAlignedDPRCS2Restores (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
	Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
static unsigned	EstimateFunctionSizeInBytes (const MachineFunction &MF, const ARMBaseInstrInfo &TII)
static unsigned	estimateRSStackSizeLimit (MachineFunction &MF, const TargetFrameLowering *TFI, bool &HasNonSPFrameIndex)
	estimateRSStackSizeLimit - Look at each instruction that references stack frames and return the stack size limit beyond which some of these instructions will require a scratch register during their expansion later.
static void	checkNumAlignedDPRCS2Regs (MachineFunction &MF, BitVector &SavedRegs)
static bool	canSpillOnFrameIndexAccess (const MachineFunction &MF, const TargetFrameLowering &TFI)
static uint32_t	alignToARMConstant (uint32_t Value)
	Get the minimum constant for ARM that is greater than or equal to the argument.

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-frame-lowering"

◆ SpillArea

◆ alignToARMConstant()

◆ canSpillOnFrameIndexAccess()

◆ checkNumAlignedDPRCS2Regs()

Definition at line 2423 of file ARMFrameLowering.cpp.

References llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasFnAttribute(), llvm::BitVector::set(), SpillAlignedNEONRegs, and llvm::BitVector::test().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves().

◆ emitAlignedDPRCS2Restores()

Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers starting from d8.

These instructions are assumed to execute while the stack is still aligned, unlike the code inserted by emitPopInst.

Definition at line 2112 of file ARMFrameLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), llvm::dwarf_linker::DebugLoc, llvm::RegState::Define, DL, llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getSubtarget(), I, llvm::RegState::ImplicitDefine, isThumb(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::RegState::Kill, MBB, MI, Opc, llvm::predOps(), TII, and TRI.

Referenced by llvm::ARMFrameLowering::restoreCalleeSavedRegisters().

◆ emitAlignedDPRCS2Spills()

Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers starting from d8.

Also insert stack realignment code and leave the stack pointer pointing to the d8 spill slot.

Definition at line 1939 of file ARMFrameLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), llvm::dwarf_linker::DebugLoc, DL, emitAligningInstructions(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFrameInfo::getMaxAlign(), llvm::MachineFunction::getSubtarget(), I, llvm::RegState::ImplicitKill, isThumb(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::RegState::Kill, MBB, MI, Opc, llvm::predOps(), llvm::MachineFrameInfo::setObjectAlignment(), llvm::ARMFunctionInfo::setShouldRestoreSPFromFP(), TII, and TRI.

Referenced by llvm::ARMFrameLowering::spillCalleeSavedRegisters().

◆ emitAligningInstructions()

Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bits.

For versions of the architecture that support Neon, this must be done in a single instruction, since skipAlignedDPRCS2Spills assumes it is done in a single instruction. That function only gets called when optimizing spilling of D registers on a core with the Neon instruction set present.

Definition at line 796 of file ARMFrameLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), DL, llvm::ARM_AM::getSORegOpc(), llvm::MachineFunction::getSubtarget(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::RegState::Kill, llvm::Log2(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, MBB, MBBI, llvm::predOps(), Reg, TII, and llvm::Align::value().

Referenced by emitAlignedDPRCS2Spills(), and llvm::ARMFrameLowering::emitPrologue().

◆ emitRegPlusImmediate()

void emitRegPlusImmediate ( bool isARM, MachineBasicBlock & MBB, MachineBasicBlock::iterator & MBBI, const DebugLoc & dl, const ARMBaseInstrInfo & TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0 )	static

◆ emitSPUpdate()

◆ EstimateFunctionSizeInBytes()

◆ estimateRSStackSizeLimit()

estimateRSStackSizeLimit - Look at each instruction that references stack frames and return the stack size limit beyond which some of these instructions will require a scratch register during their expansion later.

Definition at line 2339 of file ARMFrameLowering.cpp.