LLVM: llvm::TargetPassConfig Class Reference (original) (raw)

Target-Independent Code Generator Pass Configuration Options. More...

#include "[llvm/CodeGen/TargetPassConfig.h](TargetPassConfig%5F8h%5Fsource.html)"

Public Member Functions
	TargetPassConfig (TargetMachine &TM, PassManagerBase &PM)
	TargetPassConfig ()
	~TargetPassConfig () override
template
TMC &	getTM () const
	Get the right type of TargetMachine for this target.
void	setInitialized ()
CodeGenOptLevel	getOptLevel () const
void	setDisableVerify (bool Disable)
bool	getEnableTailMerge () const
void	setEnableTailMerge (bool Enable)
bool	getEnableSinkAndFold () const
void	setEnableSinkAndFold (bool Enable)
bool	requiresCodeGenSCCOrder () const
void	setRequiresCodeGenSCCOrder (bool Enable=true)
void	substitutePass (AnalysisID StandardID, IdentifyingPassPtr TargetID)
	Allow the target to override a specific pass without overriding the pass pipeline.
void	insertPass (AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
	Insert InsertedPassID pass after TargetPassID pass.
void	enablePass (AnalysisID PassID)
	Allow the target to enable a specific standard pass by default.
void	disablePass (AnalysisID PassID)
	Allow the target to disable a specific standard pass by default.
IdentifyingPassPtr	getPassSubstitution (AnalysisID StandardID) const
	Return the pass substituted for StandardID by the target.
bool	isPassSubstitutedOrOverridden (AnalysisID ID) const
	Return true if the pass has been substituted by the target or overridden on the command line.
bool	getOptimizeRegAlloc () const
	Return true if the optimized regalloc pipeline is enabled.
bool	usingDefaultRegAlloc () const
	Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'.
bool	addISelPasses ()
	High level function that adds all passes necessary to go from llvm IR representation to the MI representation.
virtual void	addIRPasses ()
	Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.
void	addPassesToHandleExceptions ()
	Add passes to lower exception handling for the code generator.
virtual void	addCodeGenPrepare ()
	Add pass to prepare the LLVM IR for code generation.
virtual void	addISelPrepare ()
	Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
virtual bool	addInstSelector ()
	addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.
virtual bool	addIRTranslator ()
	This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.
virtual void	addPreLegalizeMachineIR ()
	This method may be implemented by targets that want to run passes immediately before legalization.
virtual bool	addLegalizeMachineIR ()
	This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.
virtual void	addPreRegBankSelect ()
	This method may be implemented by targets that want to run passes immediately before the register bank selection.
virtual bool	addRegBankSelect ()
	This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.
virtual void	addPreGlobalInstructionSelect ()
	This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.
virtual bool	addGlobalInstructionSelect ()
	This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.
virtual void	addMachinePasses ()
	Add the complete, standard set of LLVM CodeGen passes.
virtual ScheduleDAGInstrs *	createMachineScheduler (MachineSchedContext *C) const
	Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level.
virtual ScheduleDAGInstrs *	createPostMachineScheduler (MachineSchedContext *C) const
	Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
void	printAndVerify (const std::string &Banner)
	printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
void	addPrintPass (const std::string &Banner)
	Add a pass to print the machine function if printing is enabled.
void	addVerifyPass (const std::string &Banner)
	Add a pass to perform basic verification of the machine function if verification is enabled.
void	addDebugifyPass ()
	Add a pass to add synthesized debug info to the MIR.
void	addStripDebugPass ()
	Add a pass to remove debug info from the MIR.
void	addCheckDebugPass ()
	Add a pass to check synthesized debug info for MIR.
void	addMachinePrePasses (bool AllowDebugify=true)
	Add standard passes before a pass that's about to be added.
void	addMachinePostPasses (const std::string &Banner)
	Add standard passes after a pass that has just been added.
bool	isGlobalISelAbortEnabled () const
	Check whether or not GlobalISel should abort on error.
virtual bool	reportDiagnosticWhenGlobalISelFallback () const
	Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool	isGISelCSEEnabled () const
	Check whether continuous CSE should be enabled in GISel passes.
virtual std::unique_ptr< CSEConfigBase >	getCSEConfig () const
	Returns the CSEConfig object to use for the current optimization level.
Public Member Functions inherited from llvm::ImmutablePass
	ImmutablePass (char &pid)
	~ImmutablePass () override
virtual void	initializePass ()
	initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require.
ImmutablePass *	getAsImmutablePass () override
bool	runOnModule (Module &) override
	ImmutablePasses are never run.
Public Member Functions inherited from llvm::ModulePass
	ModulePass (char &pid)
	~ModulePass () override
Pass *	createPrinterPass (raw_ostream &OS, const std::string &Banner) const override
	createPrinterPass - Get a module printer pass.
virtual bool	runOnModule (Module &M)=0
	runOnModule - Virtual method overriden by subclasses to process the module being operated on.
void	assignPassManager (PMStack &PMS, PassManagerType T) override
	Find appropriate Module Pass Manager in the PM Stack and add self into that manager.
PassManagerType	getPotentialPassManagerType () const override
	Return what kind of Pass Manager can manage this pass.
Public Member Functions inherited from llvm::Pass
	Pass (PassKind K, char &pid)
	Pass (const Pass &)=delete
Pass &	operator= (const Pass &)=delete
virtual	~Pass ()
PassKind	getPassKind () const
virtual StringRef	getPassName () const
	getPassName - Return a nice clean name for a pass.
AnalysisID	getPassID () const
	getPassID - Return the PassID number that corresponds to this pass.
virtual bool	doInitialization (Module &)
	doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run.
virtual bool	doFinalization (Module &)
	doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run.
virtual void	print (raw_ostream &OS, const Module *M) const
	print - Print out the internal state of the pass.
void	dump () const
virtual Pass *	createPrinterPass (raw_ostream &OS, const std::string &Banner) const =0
	createPrinterPass - Get a Pass appropriate to print the IR this pass operates on (Module, Function or MachineFunction).
virtual void	assignPassManager (PMStack &, PassManagerType)
	Each pass is responsible for assigning a pass manager to itself.
virtual void	preparePassManager (PMStack &)
	Check if available pass managers are suitable for this pass or not.
virtual PassManagerType	getPotentialPassManagerType () const
	Return what kind of Pass Manager can manage this pass.
void	setResolver (AnalysisResolver *AR)
AnalysisResolver *	getResolver () const
virtual void	getAnalysisUsage (AnalysisUsage &) const
	getAnalysisUsage - This function should be overriden by passes that need analysis information to do their job.
virtual void	releaseMemory ()
	releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed.
virtual void *	getAdjustedAnalysisPointer (AnalysisID ID)
	getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance.
virtual ImmutablePass *	getAsImmutablePass ()
virtual PMDataManager *	getAsPMDataManager ()
virtual void	verifyAnalysis () const
	verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information.
virtual void	dumpPassStructure (unsigned Offset=0)
template
AnalysisType *	getAnalysisIfAvailable () const
	getAnalysisIfAvailable() - Subclasses use this function to get analysis information that might be around, for example to update it.
bool	mustPreserveAnalysisID (char &AID) const
	mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID.
template
AnalysisType &	getAnalysis () const
	getAnalysis() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
template
AnalysisType &	getAnalysis (Function &F, bool *Changed=nullptr)
	getAnalysis() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
template
AnalysisType &	getAnalysisID (AnalysisID PI) const
template
AnalysisType &	getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)

Static Public Member Functions
static bool	hasLimitedCodeGenPipeline ()
	Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
static bool	willCompleteCodeGenPipeline ()
	Returns true if none of the -stop-before and -stop-after options is set.
static std::string	getLimitedCodeGenPipelineReason ()
	If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that caused this pipeline to be limited.
static Expected< StartStopInfo >	getStartStopInfo (PassInstrumentationCallbacks &PIC)
	Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
Static Public Member Functions inherited from llvm::Pass
static const PassInfo *	lookupPassInfo (const void *TI)
static const PassInfo *	lookupPassInfo (StringRef Arg)
static Pass *	createPass (AnalysisID ID)

Protected Member Functions
bool	addCoreISelPasses ()
	Add the actual instruction selection passes.
void	setOpt (bool &Opt, bool Val)
bool	isCustomizedRegAlloc ()
	Return true if register allocator is specified by -regalloc=override.
virtual bool	addPreISel ()
	Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes.
virtual void	addMachineSSAOptimization ()
	addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool	addILPOpts ()
	Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void	addPreRegAlloc ()
	This method may be implemented by targets that want to run passes immediately before register allocation.
virtual FunctionPass *	createTargetRegisterAllocator (bool Optimized)
	createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.
virtual void	addFastRegAlloc ()
	addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation.
virtual void	addOptimizedRegAlloc ()
	addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool	addPreRewrite ()
	addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers.
virtual bool	addPostFastRegAllocRewrite ()
	addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete.
virtual void	addPostRewrite ()
	Add passes to be run immediately after virtual registers are rewritten to physical registers.
virtual void	addPostRegAlloc ()
	This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.
virtual void	addMachineLateOptimization ()
	Add passes that optimize machine instructions after register allocation.
virtual void	addPreSched2 ()
	This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.
virtual bool	addGCPasses ()
	addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual void	addBlockPlacement ()
	Add standard basic block placement passes.
virtual void	addPreEmitPass ()
	This pass may be implemented by targets that want to run passes immediately before machine code is emitted.
virtual void	addPostBBSections ()
	This pass may be implemented by targets that want to run passes immediately after basic block sections are assigned.
virtual void	addPreEmitPass2 ()
	Targets may add passes immediately before machine code is emitted in this callback.
AnalysisID	addPass (AnalysisID PassID)
	Utilities for targets to add passes to the pass manager.
void	addPass (Pass *P)
	Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options.
virtual FunctionPass *	createRegAllocPass (bool Optimized)
	addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual bool	addRegAssignAndRewriteFast ()
	Add core register allocator passes which do the actual register assignment and rewriting.
virtual bool	addRegAssignAndRewriteOptimized ()
Protected Member Functions inherited from llvm::ModulePass
bool	skipModule (Module &M) const
	Optional passes call this function to check whether the pass should be skipped.

Target-Independent Code Generator Pass Configuration Options.

This is an ImmutablePass solely for the purpose of exposing CodeGen options to the internals of other CodeGen passes.

Definition at line 85 of file TargetPassConfig.h.

Definition at line 578 of file TargetPassConfig.cpp.

References EnableGlobalISelAbort, llvm::TargetOptions::EnableIPRA, EnableIPRA, llvm:🆑:Option::getNumOccurrences(), llvm::PassRegistry::getPassRegistry(), llvm::TargetOptions::GlobalISelAbort, Impl, llvm::initializeAAResultsWrapperPassPass(), llvm::initializeBasicAAWrapperPassPass(), llvm::initializeCodeGen(), llvm::TargetMachine::Options, setRequiresCodeGenSCCOrder(), TM, and llvm::TargetMachine::useIPRA().

◆ TargetPassConfig() [2/2]

◆ ~TargetPassConfig()

◆ addBlockPlacement()

Add standard basic block placement passes.

Definition at line 1524 of file TargetPassConfig.cpp.

References addPass(), llvm::createMIRAddFSDiscriminatorsPass(), llvm::createMIRProfileLoaderPass(), DisableLayoutFSProfileLoader, EnableBlockPlacementStats, llvm::EnableFSDiscriminator, getFSProfileFile(), getFSRemappingFile(), llvm::MachineBlockPlacementID, llvm::MachineBlockPlacementStatsID, llvm::sampleprof::Pass2, and TM.

Referenced by addMachinePasses().

◆ addCheckDebugPass()

◆ addCodeGenPrepare()

◆ addCoreISelPasses()

Add the actual instruction selection passes.

This does not include preparation passes on IR.

Definition at line 973 of file TargetPassConfig.cpp.

References addGlobalInstructionSelect(), addInstSelector(), addIRTranslator(), addLegalizeMachineIR(), addPass(), addPreGlobalInstructionSelect(), addPreLegalizeMachineIR(), addPreRegBankSelect(), addRegBankSelect(), llvm:🆑:BOU_FALSE, llvm:🆑:BOU_TRUE, llvm::createResetMachineFunctionPass(), EnableFastISelOption, llvm::TargetOptions::EnableGlobalISel, EnableGlobalISelOption, llvm::FinalizeISelID, llvm::TargetMachine::getO0WantsFastISel(), llvm::TargetMachine::getOptLevel(), isGlobalISelAbortEnabled(), llvm::None, llvm::TargetMachine::Options, printAndVerify(), reportDiagnosticWhenGlobalISelFallback(), llvm::TargetMachine::setFastISel(), llvm::TargetMachine::setGlobalISel(), llvm::TargetMachine::setO0WantsFastISel(), and TM.

Referenced by addISelPasses().

◆ addDebugifyPass()

◆ addFastRegAlloc()

◆ addGCPasses()

◆ addGlobalInstructionSelect()

This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.

Definition at line 297 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addILPOpts()

◆ addInstSelector()

◆ addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 815 of file TargetPassConfig.cpp.

References addPass(), llvm::createBasicAAWrapperPass(), llvm::createCanonicalizeFreezeInLoopsPass(), llvm::createConstantHoistingPass(), llvm::createExpandMemCmpLegacyPass(), llvm::createExpandReductionsPass(), llvm::createGlobalMergeFuncPass(), llvm::createLoopStrengthReducePass(), llvm::createLoopTermFoldPass(), llvm::createLowerGlobalDtorsLegacyPass(), llvm::createMergeICmpsLegacyPass(), llvm::createPartiallyInlineLibCallsPass(), llvm::createPostInlineEntryExitInstrumenterPass(), llvm::createReplaceWithVeclibLegacyPass(), llvm::createScalarizeMaskedMemIntrinLegacyPass(), llvm::createScopedNoAliasAAWrapperPass(), llvm::createSelectOptimizePass(), llvm::createTypeBasedAAWrapperPass(), llvm::createUnreachableBlockEliminationPass(), llvm::createVerifierPass(), DisableAtExitBasedGlobalDtorLowering, DisableConstantHoisting, DisableExpandReductions, DisableLSR, DisableMergeICmps, DisablePartialLibcallInlining, DisableReplaceWithVecLib, DisableSelectOptimize, DisableVerify, EnableGlobalMergeFunc, EnableLoopTermFold, llvm::GCLoweringID, getOptLevel(), llvm::TargetMachine::getTargetTriple(), llvm::Triple::isOSBinFormatMachO(), llvm::None, llvm::ShadowStackGCLoweringID, and TM.

Referenced by llvm::AMDGPUPassConfig::addIRPasses(), and addISelPasses().

◆ addIRTranslator()

This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.

Definition at line 270 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addISelPasses()

High level function that adds all passes necessary to go from llvm IR representation to the MI representation.

Adds IR based lowering and target specific optimization passes and finally the core instruction selection passes.

Returns

true if an error occurred, false otherwise.

Definition at line 1060 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addCodeGenPrepare(), addCoreISelPasses(), addIRPasses(), addISelPrepare(), addPass(), addPassesToHandleExceptions(), llvm::createExpandLargeDivRemPass(), llvm::createExpandLargeFpConvertPass(), llvm::createLowerEmuTLSPass(), llvm::createPreISelIntrinsicLoweringPass(), llvm::createTargetTransformInfoWrapperPass(), llvm::TargetMachine::getTargetIRAnalysis(), TM, and llvm::TargetMachine::useEmulatedTLS().

Referenced by addPassesToGenerateCode().

◆ addISelPrepare()

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.

Definition at line 946 of file TargetPassConfig.cpp.

References addPass(), addPreISel(), llvm::createCallBrPass(), llvm::createObjCARCContractPass(), llvm::createPrintFunctionPass(), llvm::createSafeStackPass(), llvm::createStackProtectorPass(), llvm::createVerifierPass(), llvm::dbgs(), DisableVerify, getOptLevel(), llvm::None, PrintISelInput, and requiresCodeGenSCCOrder().

Referenced by addISelPasses().

◆ addLegalizeMachineIR()

This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.

Definition at line 278 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addMachineLateOptimization()

◆ addMachinePasses()

Add the complete, standard set of LLVM CodeGen passes.

Add the complete set of target-independent postISel code generator passes.

Fully developed targets will not generally override this.

This can be read as the standard order of major LLVM CodeGen stages. Stages with nontrivial configuration or multiple passes are broken out below in addStage routines.

Any TargetPassConfig::addXX routine may be overriden by the Target. The addPre/Post methods with empty header implementations allow injecting target-specific fixups just before or after major stages. Additionally, targets have the flexibility to change pass order within a stage by overriding default implementation of addStage routines below. Each technique has maintainability tradeoffs because alternate pass orders are not well supported. addPre/Post works better if the target pass is easily tied to a common pass. But if it has subtle dependencies on multiple passes, the target should override the stage instead.

TODO: We could use a single addPre/Post(ID) hook to allow pass injection before/after any target-independent pass. But it's currently overkill.

Add passes that optimize machine instructions after register allocation.

Definition at line 1101 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addBlockPlacement(), addFastRegAlloc(), addGCPasses(), addMachineLateOptimization(), addMachineSSAOptimization(), addOptimizedRegAlloc(), addPass(), addPostBBSections(), addPostRegAlloc(), addPreEmitPass(), addPreEmitPass2(), addPreRegAlloc(), addPreSched2(), llvm::AlwaysOutline, llvm::TargetOptions::BBAddrMap, llvm::createBasicBlockPathCloningPass(), llvm::createBasicBlockSectionsPass(), llvm::createBasicBlockSectionsProfileReaderWrapperPass(), llvm::createCFIFixup(), llvm::createGCEmptyBasicBlocksPass(), llvm::createMachineFunctionSplitterPass(), llvm::createMachineOutlinerPass(), llvm::createMIRAddFSDiscriminatorsPass(), llvm::createMIRProfileLoaderPass(), llvm::createPrologEpilogInserterPass(), llvm::createRegUsageInfoCollector(), llvm::createRegUsageInfoPropPass(), llvm::createStackFrameLayoutAnalysisPass(), DisableCFIFixup, DisableRAFSProfileLoader, llvm::TargetOptions::EnableCFIFixup, llvm::EnableFSDiscriminator, EnableImplicitNullChecks, llvm::TargetOptions::EnableIPRA, llvm::TargetOptions::EnableMachineFunctionSplitter, EnableMachineFunctionSplitter, llvm::TargetOptions::EnableMachineOutliner, EnableMachineOutliner, llvm::ExpandPostRAPseudosID, llvm::FEntryInserterID, llvm::FixupStatepointCallerSavedID, llvm::FuncletLayoutID, GCEmptyBlocks, llvm::TargetMachine::getBBSectionsFuncListBuf(), llvm::TargetMachine::getBBSectionsType(), getFSProfileFile(), getFSRemappingFile(), getOptimizeRegAlloc(), getOptLevel(), llvm::ImplicitNullChecksID, isPassSubstitutedOrOverridden(), llvm::List, llvm::LiveDebugValuesID, llvm::LocalStackSlotAllocationID, llvm::MachineSanitizerBinaryMetadataID, MISchedPostRA, llvm::NeverOutline, llvm::None, llvm::TargetMachine::Options, llvm::sampleprof::Pass1, llvm::sampleprof::PassLast, llvm::PatchableFunctionID, llvm::PostMachineSchedulerID, llvm::PostRAMachineSinkingID, llvm::PostRASchedulerID, llvm::PrologEpilogCodeInserterID, llvm::RemoveLoadsIntoFakeUsesID, llvm::RemoveRedundantDebugValuesID, llvm::ShrinkWrapID, llvm::StackMapLivenessID, llvm::TargetOptions::SupportsDefaultOutlining, llvm::TargetMachine::targetSchedulesPostRAScheduling(), TM, llvm::WithColor::warning(), and llvm::XRayInstrumentationID.

Referenced by addPassesToGenerateCode().

◆ addMachinePostPasses()

◆ addMachinePrePasses()

◆ addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

Add passes that optimize machine instructions in SSA form.

Definition at line 1281 of file TargetPassConfig.cpp.

References addILPOpts(), addPass(), llvm::DeadMachineInstructionElimID, llvm::EarlyMachineLICMID, llvm::EarlyTailDuplicateLegacyID, llvm::LocalStackSlotAllocationID, llvm::MachineCSELegacyID, llvm::MachineSinkingID, llvm::OptimizePHIsLegacyID, llvm::PeepholeOptimizerLegacyID, and llvm::StackColoringLegacyID.

Referenced by addMachinePasses().

◆ addOptimizedRegAlloc()

addOptimizedRegAlloc - Add passes related to register allocation.

Add standard target-independent passes that are tightly coupled with optimized register allocation, including coalescing, machine instruction scheduling, and register allocation itself.

CodeGenTargetMachineImpl provides standard regalloc passes for most targets.

Definition at line 1436 of file TargetPassConfig.cpp.

References addPass(), addPostRewrite(), addRegAssignAndRewriteOptimized(), llvm::DetectDeadLanesID, EarlyLiveIntervals, llvm::InitUndefID, llvm::LiveIntervalsID, llvm::LiveVariablesID, llvm::MachineCopyPropagationID, llvm::MachineLICMID, llvm::MachineLoopInfoID, llvm::MachineSchedulerID, llvm::PHIEliminationID, llvm::ProcessImplicitDefsID, llvm::RegisterCoalescerID, llvm::RenameIndependentSubregsID, llvm::StackSlotColoringID, llvm::TwoAddressInstructionPassID, and llvm::UnreachableMachineBlockElimID.

Referenced by addMachinePasses().

◆ addPass() [1/2]

Utilities for targets to add passes to the pass manager.

Add a CodeGen pass at this point in the pipeline after checking for target and command line overrides.

Add a CodeGen pass at this point in the pipeline after checking overrides. Return the pass that was added, or zero if no pass was added.

addPass cannot return a pointer to the pass instance because is internal the PassManager and the instance we create here may already be freed.

Definition at line 743 of file TargetPassConfig.cpp.

References addPass(), llvm::Pass::createPass(), llvm::IdentifyingPassPtr::getID(), llvm::IdentifyingPassPtr::getInstance(), getPassSubstitution(), llvm::IdentifyingPassPtr::isInstance(), llvm::IdentifyingPassPtr::isValid(), llvm_unreachable, overridePass(), and P.

Referenced by addBlockPlacement(), addCodeGenPrepare(), llvm::AMDGPUPassConfig::addCodeGenPrepare(), DirectXPassConfig::addCodeGenPrepare(), addCoreISelPasses(), llvm::AMDGPUPassConfig::addEarlyCSEOrGVNPass(), addFastRegAlloc(), addGCPasses(), llvm::AMDGPUPassConfig::addInstSelector(), addIRPasses(), llvm::AMDGPUPassConfig::addIRPasses(), addISelPasses(), addISelPrepare(), addMachineLateOptimization(), addMachinePasses(), addMachineSSAOptimization(), addOptimizedRegAlloc(), addPass(), addPassesToHandleExceptions(), llvm::AMDGPUPassConfig::addPreISel(), addRegAssignAndRewriteFast(), addRegAssignAndRewriteOptimized(), and llvm::AMDGPUPassConfig::addStraightLineScalarOptimizationPasses().

◆ addPass() [2/2]

Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options.

Add a pass to the PassManager if that pass is supposed to be run.

Takes ownership of the pass.

If the Started/Stopped flags indicate either that the compilation should start at a later pass or that it should stop after an earlier pass, then do not add the pass. Finally, compare the current pass against the StartAfter and StopAfter options and change the Started/Stopped flags accordingly.

Definition at line 696 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addMachinePostPasses(), addMachinePrePasses(), addPass(), assert(), Impl, Initialized, llvm::PassConfigImpl::InsertedPasses, P, and llvm::report_fatal_error().

◆ addPassesToHandleExceptions()

Add passes to lower exception handling for the code generator.

Turn exception handling constructs into something the code generators can handle.

Definition at line 894 of file TargetPassConfig.cpp.

References addPass(), llvm::AIX, llvm::ARM, assert(), llvm::createDwarfEHPass(), llvm::createLowerInvokePass(), llvm::createSjLjEHPreparePass(), llvm::createUnreachableBlockEliminationPass(), llvm::createWasmEHPass(), llvm::createWinEHPass(), llvm::DwarfCFI, llvm::MCAsmInfo::getExceptionHandlingType(), llvm::TargetMachine::getMCAsmInfo(), getOptLevel(), llvm::None, llvm::SjLj, TM, llvm::Wasm, llvm::WinEH, and llvm::ZOS.

Referenced by addISelPasses().

◆ addPostBBSections()

This pass may be implemented by targets that want to run passes immediately after basic block sections are assigned.

Definition at line 469 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPostFastRegAllocRewrite()

◆ addPostRegAlloc()

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.

Definition at line 446 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPostRewrite()

◆ addPreEmitPass()

◆ addPreEmitPass2()

Targets may add passes immediately before machine code is emitted in this callback.

This is called even later than addPreEmitPass.

Definition at line 476 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPreGlobalInstructionSelect()

This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.

Definition at line 291 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addPreISel()

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes.

Methods with out-of-line standard implementations are major CodeGen stages called by addMachinePasses. Some targets may override major stages when inserting passes is insufficient, but maintaining overriden stages is more work. addPreISelPasses - This method should add any "last minute" LLVM->LLVM passes (which are run just before instruction selector).

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 385 of file TargetPassConfig.h.

Referenced by addISelPrepare().

◆ addPreLegalizeMachineIR()

◆ addPreRegAlloc()

◆ addPreRegBankSelect()

◆ addPreRewrite()

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers.

These passes must preserve VirtRegMap and LiveIntervals, and when running after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. When these passes run, VirtRegMap contains legal physreg assignments for all virtual registers.

Note if the target overloads addRegAssignAndRewriteOptimized, this may not be honored. This is also not generally used for the fast variant, where the allocation and rewriting are done in one pass.

Definition at line 432 of file TargetPassConfig.h.

Referenced by addRegAssignAndRewriteOptimized().

◆ addPreSched2()

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.

Definition at line 453 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPrintPass()

◆ addRegAssignAndRewriteFast()

◆ addRegAssignAndRewriteOptimized()

◆ addRegBankSelect()

This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.

Definition at line 287 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addStripDebugPass()

◆ addVerifyPass()

◆ createMachineScheduler()

◆ createPostMachineScheduler()

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition at line 320 of file TargetPassConfig.h.

◆ createRegAllocPass()

◆ createTargetRegisterAllocator()

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.

Instantiate the default register allocator pass for this target for either the optimized or unoptimized allocation path.

This will be added to the pass manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc in the optimized case.

A target that uses the standard regalloc pass order for fast or optimized allocation may still override this for per-target regalloc selection. But -regalloc=... always takes precedence.

Reimplemented in DirectXPassConfig.

Definition at line 1355 of file TargetPassConfig.cpp.

References llvm::createFastRegisterAllocator(), and llvm::createGreedyRegisterAllocator().

Referenced by createRegAllocPass().

◆ disablePass()

◆ enablePass()

◆ getCSEConfig()

◆ getEnableSinkAndFold()

◆ getEnableTailMerge()

◆ getLimitedCodeGenPipelineReason()

If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that caused this pipeline to be limited.

Definition at line 646 of file TargetPassConfig.cpp.

References hasLimitedCodeGenPipeline(), Idx, StartAfterOpt, StartAfterOptName, StartBeforeOpt, StartBeforeOptName, StopAfterOpt, StopAfterOptName, StopBeforeOpt, and StopBeforeOptName.

◆ getOptimizeRegAlloc()

◆ getOptLevel()

◆ getPassSubstitution()

◆ getStartStopInfo()

◆ getTM()

template

◆ hasLimitedCodeGenPipeline()

◆ insertPass()

◆ isCustomizedRegAlloc()

◆ isGISelCSEEnabled()

◆ isGlobalISelAbortEnabled()

◆ isPassSubstitutedOrOverridden()

◆ printAndVerify()

◆ reportDiagnosticWhenGlobalISelFallback()

◆ requiresCodeGenSCCOrder()

◆ setDisableVerify()

◆ setEnableSinkAndFold()

◆ setEnableTailMerge()

◆ setInitialized()

◆ setOpt()

◆ setRequiresCodeGenSCCOrder()

◆ substitutePass()

◆ usingDefaultRegAlloc()

Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'.

Definition at line 1420 of file TargetPassConfig.cpp.

References RegAlloc.

◆ willCompleteCodeGenPipeline()

◆ DisableVerify

◆ EnableLoopTermFold

◆ EnableSinkAndFold

◆ EnableTailMerge

◆ ID

◆ Impl

◆ Initialized

◆ RequireCodeGenSCCOrder

◆ TM

Definition at line 123 of file TargetPassConfig.h.

Referenced by addBlockPlacement(), llvm::AMDGPUPassConfig::addCodeGenPrepare(), addCoreISelPasses(), addIRPasses(), llvm::AMDGPUPassConfig::addIRPasses(), addISelPasses(), addMachineLateOptimization(), addMachinePasses(), addPassesToHandleExceptions(), llvm::AMDGPUPassConfig::addPreISel(), addVerifyPass(), llvm::AMDGPUPassConfig::getCSEConfig(), getOptLevel(), getTM(), isGlobalISelAbortEnabled(), llvm::AMDGPUPassConfig::isPassEnabled(), reportDiagnosticWhenGlobalISelFallback(), and TargetPassConfig().

The documentation for this class was generated from the following files:

• include/llvm/CodeGen/TargetPassConfig.h
• lib/CodeGen/TargetPassConfig.cpp